Armadeus Systems APF6_SP SoM Combines Freescale i.MX6 Processor and Altera Cyclone V GX FPGA

Xilinx Zynq and Altera Cyclone V are both SoC families combining an ARM processor (Hard Processor System  – HPS) with FPGA fabric into a single chip. But Armadeus Systems, a French company designing industrial ARM Linux processor modules, has unveiled a new module where the CPU and FPGA are two separate chips, namely Freescale i.MX6 (single to quad) and Altera Cyclone V GX FPGA, in order to provide more flexibility, and extra features like a GPU with OpenCL support, an hardware video processing unit, a dedicated SATA port, and so on.

Block Diagram for APF6_SP Module
Block Diagram for APF6_SP Module (Click to Enlarge)

Armadeus APF6_SP SoM specifications:

  • SoC – Freescale i.MX6 single, dual or quad core Cortex A9 processor with Vivante GPUs
  • FPGA – Altera Cyclone V GX (C4/C5/C7/C9)
  • System Memory Armadeus_APF6_SP
    • 512MB to 1GB DDR3 32-bit @ 800 MHz for i.MX6 Solo or Duallite
    • 512MB to 2GB DDR3 64-bit @ 1066MHz for i.MX6 Dual or Quad
    • Optional up to 768MB RAM dedicated to the FPGA
  • Storage – 2 GB to 64 GB eMMC 8bits (MLC type) + SATA II for i.MX6 Dual or Quad
  • Connectivity – 1x 10/100/1000M bits Ethernet, optional Wi-Fi 802.11 b/g/n and Bluetooth 4.0
  • Other Peripherals
    • Up to 5x UART (one for debug), up to 3x I2C, up to 5x SPI
    • Up to 3x MMC/SD port
    • Up to 4x PWM
    • Up to 1x SPDIF, up to 2x Audio port
    • Up to 2x CAN controllers
    • 1x USB OTG Hi-Speed, 1x USB Host (Hi-Speed)
    • 1x LCD controller 24bits parallel and LVDS interfaces resolution up to 1920×1200 @ 60Hz and an HMDI controller
    • 1x high speed MIPI Camera interface
    • Up to 83x General Purpose IOs (3.3V compatible)
    • JTAG (Debug (ICE) and test)
  • Transceivers
    • USB OTG high speed (1x)
    • USB Host high speed (1x)
    • Gigabit Ethernet 10/100/1000 Mbits autoMDX
  • SoM Connectors – 2x Hirose 120 pins fine pitch (0.6 mm); 1x Hirose 140 pins fine pitch (0.6 mm) dedicated to the FPGA and compliant with HSMC standard.
  • Power Supply – +3.3VDC 5%
  • Dimensions – 90 x 50 mm
  • Operating Temperature Range –  0°C..70°C; optional -40 to +85°C.

The company provide source code and binary for Linux 3.15 and u-boot for the module. If you’re not sure why you’d choose Armadeus solution against platforms based on Xilinx Zynq or Cyclione V ARM + FPGA SoCs, the company has made a side by side comparison table with APF6_SP, Xilinx Zynq 7010/7015/7020 SoC and Altera Cyclone V SX SoC.

Freescale+FPGA_vs_Xilinx_Zynq_vs_Altera_Cyclone_FPGA
Click to Enlarge

APF6_SP_Dev baseboard is also available to evaluate the system-on-module with the following connectors:

  • SoM Connectors – 2x 120-pin hirose receptacles for APF6/APF6_SP boards, 1x 140-pin hirose connector for APF6_SP board only
  • Storage – 1x SATA connector;  1x SATA power connector, 1x microSD card slot
  • Connectivity – Ethernet (RJ45) with integrated isolation transformer and state ledsAPF6_Dev
  • Video / Display – 1x HDMI, LCD and touchscreen connector,  LVDS TFT connector
  • Audio – 1x S/PDIF output, 3.5mm stereo audio jack, 3.5mm mono jack for microphone
  • Camera – CSI MIPI FPC
  • USB – 1x USB host port, 2x mini USB ports
  • Expansion
    • One PCIexpress 1 lane (usable only with APF6 not with APF6_SP boards)
    • Three (2×10 2.54mm pins) GPIO connectors (I²C, SPI, SSI, 5xUARTs, CAN …)
  • Debugging – JTAG (2.54mm pins)
  • Power – 12V DC Input via 2.5mm jack
  • Dimensions – 160 x 110 mm

APF6 is the company Freescale i.MX6 module without FPGA, and the PCIe connector can’t be used with APF6_SP module, simply because the PCIe interface is used to interface the Freescale processor with Altera FPGA.

The modules and baseboard are available starting at respectively 212 Euros and 130 Euros. Further details, including links to documentation,  can be found on Armadeus Systems APF6_SP SoM and APF6_Dev baseboard pages.

Via EDN Europe.

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1 Comment
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rasz_pl
rasz_pl
8 years ago

> extra features like a GPU with OpenCL support

no, Vivante claims OpenCL support, but pathetic memory makes it a non starter. Theoretical performance is ~13Gflops, but ONLY reachable when computing on registers, and not touching memory at all :). When you try to do actual work on actual data fetched from actual memory performance drops to 0.6Gflops = about 2x ARM A9, or one 10 year old x86 Intel based laptop.

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