Posts Tagged ‘armv8’

ARM TechCon 2014 Schedule – 64-Bit, IoT, Optimization & Debugging, Security and More

July 23rd, 2014 No comments

ARM Technology Conference (TechCon) 2014 will take place on October 1 – 3, 2014, in Santa Clara, and as every year, there will be a conference with various sessions for suitable engineers and managers, as well as an exposition where companies showcase their latest ARM based products and solutions. The detailed schedule for the conference has just been made available. Last year,  there were 90 sessions organized into 15 tracks, but this year, despite received 300 applications,  the organizers decided to scale it down a bit, and there will be 75 session in the following 11 tracks:ARM_TechCon_2014

  • Chip Implementation
  • Debugging
  • Graphics
  • Heterogeneous Compute
  • New Frontiers
  • Power Efficiency
  • Safety and Security
  • Software Development and Optimization
  • Software Optimization for Infrastructure and Cloud
  • System Design
  • Verification

There are also some paid workshops that take all day with topics such as “Android (NDK) and ARM overview”, “ARM and the Internet of Things”, or “ARM Accredited Engineer Programs”.

As usual, I’ve gone through the schedule builder, and come up with some interesting sessions with my virtual schedule during the 3-day event:

Wednesday – 1st of October

In this session, Dr. Saied Tehrani will discuss how Spansion’s approach to utilize the ARM Cortex-R line of processors to deliver energy efficient solutions for the automotive MCU market has led the company to become a vital part of the movement toward connectivity in cars. Beginning with an overview of the auto industry’s innovation and growth in connected car features, he will explain how these systems require high performance processing to give drivers the fluid experience they expect. Highlights in security and reliability with ARM Cortex-R, including Spansion’s Traveo Family of MCU’s will also be presented.

HEVC and VP9 are the latest video compression standards that significantly improves compression ratio compared to its widely used predecessors H.264 and VP8 standard. In this session the following will be discussed:

  • The market need for GPU accelerated HEVC and VP9 decoders
  • Challenges involved in offloading video decoding algorithms to a GPU, and how Mali GPU is well suited to tackle them
  • Improvement in power consumption and performance of Mali GPU accelerated decoder
  • big.LITTLE architecture and CCI/CCN’s complementing roles in improving the GPU accelerated video decoder’s power consumption

ARM’s Cortex-M family of embedded processors are delivering energy-efficient, highly responsive solutions in a wide variety of application areas right from the lowest-power, general-purpose microcontrollers to specialised devices in advanced SoC designs. This talk will examine how ARM plans to grow the ARM Cortex-M processor family to provide high performance together with flexible memory systems, whilst still maintaining the low-power, low-latency characteristics of ARM’s architecture v7M.

IoT devices as embedded systems cover a large range of devices from low-power, low-performance sensors to high-end gateways. This presentation will highlight the elements an embedded engineer needs to analyse before selecting the MCU for his design. Software is fundamental in IoT: from networking to power management, from vertical market protocols to IoT Cloud protocols and services, from programming languages to remote firmware update, these are all design criteria influencing an IoT device design. Several challenges specific to IoT design will be addressed:

  • Code size and RAM requirements for the major networking stacks
  • Optimizing TCP/IP resources versus performance
  • Using Java from Oracle or from other vendors versus C
  • WiFi (radio only or integrated module)
  • Bluetooth (Classis versus LE) IoT protocols

Thursday – 2nd of October

Amongst ARM’s IP portfolio we have CPUs, GPUs, video engines and display processors, together with fabric interconnect and POP IP, all co-designed, co-verified and co-optimized to produce energy-efficient implementations. In this talk, we will present some of the innovations ARM has introduced to reduce memory bandwidth and system power, both in the IP blocks themselves and the interactions between them, and how this strategy now extends to the new ARM Mali display processors.

Designing a system that has to run on coin cells? There’s little accurate information available about how these batteries behave in systems that spend most of their time sleeping. This class will give design guidance on the batteries, plus examine the many other places power leakages occur, and offer some mitigation strategies.

64-bit is the “new black” across the electronics industry, from server to mobile devices. So if you are building or considering building an ARMv8-A SoC, you shall attend this talk to either check that you know everything or find out what you shall know! Using the ARMv8 Juno ARM Development Platform (ADP) as reference, this session will cover:

  • The ARMv8-A hardware compute subsystem architecture for Cortex-A57, Cortex-A53 & Mali based SoC
  • The associated ARMv8-A software stack
  • The resources available to 64-bit software developers
  • Demonstration of the Android Open Source Project for ARMv8 running on Juno.

Rapid prototyping platforms have become a standard path to develop initial design concepts. They provide an easy-to-use interface with a minimal learning curve and allow ideas to flourish and quickly become reality. Transitioning from a simple, easy-to-use rapid prototyping system can be daunting, but shouldn’t be. This session presents options for starting with mbed as a prototyping environment and moving to full production with the use of development hardware, the open-source mbed SDK and HDK, and the rich ARM ecosystem of hardware and software tools.Attendees will learn how to move from the mbed online prototyping environment to full production software, including:

  • Exporting from mbed to a professional IDE
  • Full run-time control with debugging capabilities
  • Leveraging an expanded SDK with a wider range of integration points
  • Portability of applications from an mbed-enabled HDK to your custom hardware

Statistics is often perceived as scary and dull… but not when you apply it to optimizing your code! You can learn so much about your system and your application by using relatively simple techniques that there’s no excuse not to know them.This presentation will use no slides but will step through a fun and engaging demo of progressively optimizing OpenCL applications on a ARM-powered Chromebook using IPython. Highlights will include analyzing performance counters using radar diagrams, reducing performance variability by optimizing for caches and predicting which program transformations will make a real difference before actually implementing them.

Friday – 3rd of October

The proliferation of mobile devices has led to the need of squeezing every last micro-amp-hour out of batteries. Minimizing the energy profile of a micro-controller is not always straight forward. A combination of sleep modes, peripheral control and other techniques can be used to maximize battery life. In this session, strategies for optimizing micro-controller energy profiles will be examined which will extend battery life while maintaining the integrity of the system. The techniques will be demonstrated on an ARM Cortex-M processor, and include a combination of power modes, software architecture design techniques and various tips and tricks that reduce the energy profile.

One of the obstacles to IoT market growth is guaranteeing interoperability between devices and services . Today, most solutions address applications requirements for specific verticals in isolation from others. Overcoming this shortcoming requires adoption of open standards for data communication, security and device management. Economics, scalability and usability demand a platform that can be used across multiple applications and verticals. This talk covers some of the key standards like constrained application protocol (CoAP), OMA Lightweight M2M and 6LoWPAN. The key features of these standards like Caching Proxy, Eventing, Grouping, Security and Web Resource Model for creating efficient, secure, and open standards based IoT systems will also be discussed.

Virtual Prototypes are gaining widespread acceptance as a strategy for developing and debugging software removing the dependence on the availability of hardware. In this session we will explore how a virtual prototype can be used productively for software debug. We will explain the interfaces that exist for debugging and tracing activity in the virtual prototype, how these are used to attach debug and analysis tools and how these differ from (and improve upon) equivalent hardware capabilities. We will look in depth at strategies for debug and trace and how to leverage the advantages that the virtual environment offers. The presentation will further explore how the virtual prototype connects to hardware simulators to provide cross-domain (hardware and software) debug. The techniques will be illustrated through case studies garnered from experiences working with partners on projects over the last few years.

Attendees will learn:

  • How to set up a Virtual Prototype for debug and trace
  • Connecting debuggers and other analysis tools.
  • Strategies for productive debug of software in a virtual prototype.
  • How to setup trace on a virtual platform, and analysing the results.
  • Hardware in the loop: cross domain debug.
  • Use of Python to control the simulation and trace interfaces for a virtual platform.
  • 14:30 – 15:20 – GPGPU on ARM Systems by Michael Anderson, Chief Scientist, The PTR Group, Inc.

ARM platforms are increasingly coupled with high-performance Graphics Processor Units (GPUs). However the GPU can do more than just render graphics, Today’s GPUs are highly-integrated multi-core processors in their own right and are capable of much more than updating the display. In this session, we will discuss the rationale for harnessing GPUs as compute engines and their implementations. We’ll examine Nvidia’s CUDA, OpenCL and RenderScript as a means to incorporate high-performance computing into low power draw platforms. This session will include some demonstrations of various applications that can leverage the general-purpose GPU compute approach.

Abstract currently not available.

That’s 14 sessions out of the 75 available, and you can make your own schedule depending on your interests with the schedule builder.

In order to attend ARM TechCon 2014, you can register online, although you could always show up and pay the regular on-site, but it will cost you, or your company, extra.

Super Early Bird Rare
Ended June 27
Early Bird Rate
Ends August 8
Advanced Rate
Ends September 19
Regular Rate
VIP $999 $1,299 $1,499 $1,699
All-Access $799 $999 $1,199 $1,399
General Admission $699 $899 $1,099 $1,299
AAE Training $249 $299 $349 $399
Software Developers Workshop $99 $149 $199 $249
Expo FREE FREE $29 $59

There are more types of pass this year, but the 2-day and 1-day pass have gone out of the window. The expo pass used to be free at any time, but this year, you need to register before August 8. VIP and All-access provides access to all events, General Admission excludes AAE workshops and software developer workshops, AAE Training and Software Developers Workshop passes give access to the expo plus specific workshops. Further discounts are available for groups, up to 30% discount.

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Mediatek MT6795 Octa Core ARM Cortex A53 Processor to Launch in Q4 2014

July 11th, 2014 4 comments

Mediatek had already announced two 64-bit ARM SoCs with MT6732 and MT6752 boasting respectively four and eight Cortex A53 cores for mainstream and premium smartphones. There are now reports that the company will launch an eight core 64-bit LTE SoC with HMP architecture. Since HMP (Heterogeneous Multi-Processing) is only used for big.LITTLE processing, and Mediatek does not have an history of making their own custom ARM cores, we can safely assume the processor will feature four Cortex A53 little core, and four Cortex A57 big cores. [Update: finally it's eight ARM Cortex A53 cores, no HMP here].

MTK6795What we know about MT6795 so far:

  • Processor – 64-bit Octa core ARM Cortex A53 cores @ 2.2 GHz
  • GPU- Imagination Technology G6200 @ 700 MHz
  • Memory I/F – 2x LPDDR3 @ 933 MHz (PoP)
  • Camera I/F – 20MP@30fps using a dual ISP
  • Display – Up to WQXGA (2560×1600)
  • Video
    • Decoding – 4K2K @ 30 fps (H.265 and H.264)
    • Encoding – 4K2K @ 30 fps (H.265)
  • Modem – LTE FDD/TDD R9 Cat4, DC-HSPA+ 42/11Mpbs, TD-SCDMA/EDGE
  • Connectivity – Wi-Fi 802.11ac, Bluetooth, FM, GPS, Glonass and Beidou via MT6630 chip (external)
  • Process – 28 nm

That’s only the second mobile SoC I’ve heard with ARMv8 big.LITTLE, the other being Qualcomm Snapdragon 810, and it looks like MT6795 will be a direct competitor with LTE support. The Adreno 430 GPU is however likely to outperform Imagination Technology G6200 GPU chosen in the new Mediatek SoC. The company also claims MT6795 will provide an easy upgrade for OEM from their MT6595 LTE SoC, a big.LITTLE ARMv7 processor (Cortex A17 + Cortex A7).

MT6795 mass production is scheduled for December 2014, so actual products will probably be available in Q1 2015. Devices based on Snapdragon 810 are also planned for Q1/H1 2015.


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Linaro Announces 64-bit ARM Android Port on Juno ARM Development Platform

July 3rd, 2014 2 comments

Last week, Linaro 14.06 was released and one of the highlights was Android booting on ARMv8 models, but the organization has actually ported Android to a new 64-bit ARM platform. Juno ARM Development Platform is actually software development platform for ARMv8-A, including Juno Versatile Express board and an ARMv8-A reference software port developed by Linaro.

Juno Versatile Express Board (Click to Enlarge)

Juno Versatile Express Board (Click to Enlarge)

Juno VExpress Board has the following key hardware features:

Juno SoC Block Diagram (Click to Enlarge)

Juno SoC Simplified Block Diagram (Click to Enlarge)

  • SoC – 2x ARM Cortex A57 cores @ 1.1 GHz (2MB L2 cache), 4x Cortex A53 cores @ 850 MHz (1MB L2 cache) in big.LITTLE configuration with Mali-T624 GPU @ 600 MHz. Compliant with SBSA specifications Level 1.
  • I/O FPGA – Xilinx SPARTAN-6
  • MCU – ARM Cortex M3 for Motherboard Configuration Controller (MCC)
  • System Memory – 8GB DDR3L @ 1600 MHz
  • Storage – User and configuration micro SD card lots, 64MB NOR flash, configuration EEPROM
  • Connectivity – 10/100M Ethernet + 10M “configuration” Ethernet
  • Video Output – 2x HDMI
  • USB – 4x USB 2.0 host port + “configuration USB”
  • Serial – 2x UART (1x DB9 interface)
  • Debugging – P-JTAG (Processor CoreSight debug) port, coresight trace port
  • Expansion – 2 headers (HDRX and HDRY) for LogicTile Express FPGA daughterboard
  • Misc – Push buttons, LEDs, energy monitors, etc…

The hardware enables development of ARMv8-A AArch64 kernel and tools, secure OS & hypervisors through ARM Trusted Firmware, 3D graphics and GPU compute with native big.LITTLE and Mali support, Middleware & file systems porting and optimization to 64-bit, and real-time debug, trace and performance tuning with CoreSight technology. Expansion is also provided with LogicTile Express 20MG FPGA board that connects directly to the platform and can be used for driver development and prototyping.

Juno Board Block Diagram (Click to Enlarge)

Juno Board Block Diagram

This type of board is not for everybody, and mostly reserved to silicon vendors, and people working on ARMv8 software development that can’t wait for actual silicon. Juno SoC is not optimized for performance (see relatively low frequencies) and most probably not for power consumption, it’s just to let people run and optimize software for ARMv8. The other reason it’s not for everyone is the price which should be several thousand dollars, and I would not be surprised if this board cost over $10,000, as older versatile express board sell for about $6,000. You can find more details on ARM’s Juno product page.

Linaro’s ARMv8 ports are based on Linux kernel 3.10 (Linaro Stable Kernel), and compiled with GCC 4.9 and can run both Juno and ARMv8 fast models. You can download ARMv8 ports for OpenEmbedded and Android Open Source Project (AOSP).

The OpenEmbedded ARMv8 release supports on-chip USB, non-secure UART, HDMI output, keyboard and mouse functionality of P/S2, and Ethernet. The big.LITTLE multiprocessing implementation supports all 6 cores (optimizations still required), boot is done via UEFI using the NOR flash, USB mass storage, or Ethernet, ARM trusted firmware and SCP firmware are both supported.

The Android ARMv8 release supports all OpenEmbedded features, and comes with a unified kernel and kernel config for Android and Linux, and the AOSP file system based on a snapshot from the 1st of June 2014, with ART Runtime enabled as default and booting in 64-bit primary mode, GPU and HDLCD support, although there are still some bugs leading to visual artifacts.

In theory, it should be possible to run Android or OpenEmbedded ARMv8 ports on any computers using ARMv8 fast models, but be prepared to be very very patient. I won’t try it…

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Linaro 14.06 Release with Linux Kernel 3.15 and Android 4.4.3

July 1st, 2014 No comments

Linaro 14.06 has been released last week with Linux Kernel 3.15 (baseline), Linux Kernel 3.10.44 (LSK), and Android has been updated to 4.4.3.

One interesting development this month is that Android for ARMv8 (64-bit ARM) is booting on the fast models using ARM Trusted firmware and U-Boot.  SELinux has been enabled in Android. I could not see much new member hardware, except possibly B2120 (HDK) reference board for STMicro STiH407 “Monaco” STB SoC.

Here are the highlights of this release:

  • Linux Linaro 3.15-2014.06
    • GATOR version 5.18 (same version as in 2014.04)
    • updated basic Capri board support from Broadcom LT
    • cortex-strings-arm64 topic (same as in 2014.02)
    • updated Versatile Express ARM64 support (FVP Base and Foundation models, Juno) from ARM LT.
    • updated Versatile Express patches from ARM LT
    • more HiP0x Cortex A15 family updates from HiSilicon LT (hip04_eth, hip04_defconfig)
    • updated LLVM topic
    • Big endian support (same as in 2014.05)
    • ftrace_audit topic from the Kernel WG (same as in 2014.05)
    • config fragments changes – android: Enable SELinux related configurations
  • Linaro Toolchain Binaries 2014.06
    • based on GCC 4.9 and updated to latest Linaro TCWG releases
    • Linaro GCC 4.9-2014.06
    • Linaro Binutils 2.24.0-2014.06
    • Linaro GDB 7.7.1-2014.06
  • Linaro Android 14.06 – Built with Linaro GCC 4.8-2014.05, upgraded to Android 4.4.3
  • Linaro OpenEmbedded 2014.06
    • integrated Linaro GCC 4.9-2014.06
    • integrated Linaro EGLIBC 2.19-2014.06
    • integrated Linaro binutils 2.24-2014.06
    • integrated Linaro GDB 7.7.1-2014.06
    • integrated powerdebug 0.7.3
    • several ODP updates
    • upstreaming: fixed hwlatdetect metadata,  fixed recipes related to oe-core binconfig changes: apache2, php and swig, and updated PM QA to 0.4.11
  • Linaro Ubuntu 14.06
    • added openssh-server to the images, SSH keys are generated on first boot.
    • updated packages: ARM trusted firmware (0.7), openssl (1.0.1h), PM QA (0.4.11), powerdebug (0.7.3), powertop (2.6.1), LSK 3.10.44 and linux-linaro 3.15 kernels.
  • ARMv8 Ubuntu engineering build for Enterprise
  • Android for ARMv8 is booting with ARM Trusted firmware and U-Boot on Models
  • CI loop has been setup for Juno Android member build
  • CI bring up: ST B2120 engineering build
  • Build rootfs image for toolchain benchmarking
  • CI bring up: HiSilicon Hi3716cv200
  • CI bring up: ARM64 kexec build and regression test setup
  • CI bring up: Juno OpenEmbedded member build
  • LSK: add RT patchset CI loop
  • LSK: add Juno CI loop
  • Build Ubuntu rootfs image for toolchain automation framework
  • SELinux is enabled on LSK with Android 4.4.3 for ARMv7

You can visit for a list of known issues, and further release details about the LEB and community builds, Android, Kernel, Graphics, Multimedia, Landing Team, Platform, Power management and Toolchain (GCC / Qemu) components.

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Google Releases Android L (Lollipop?) Developer Preview

June 26th, 2014 2 comments

Google I/O is taking place right now in San Francisco, and the company made several announcements. Although they have not announced the full codename of Android 5.0, referring to the next version as “Android L” (Lollipop would be nice though), but they’ve already documented the key changes made to Android L, and a developer preview will be released later today (26 June), together with binary images for Google Nexus 5 and Nexus 7.


Beside the smartphone and tablet developer preview, there will be 3 other SDKs for Android L:

  • Android Wear SDK – Android for wearables with sync notifications, wearable apps, data transfer APIs, and voice actions, e.g. “Ok Google, call mum”.
  • Android TV Preview SDK – Android for TVs with pre-built fragments for browsing and interacting with media catalogs, in-app search, and recommendations.
  • Android Auto SDK – Android for the car with apps featuring consistent user experience between vehicles, and minimizing distractions.

I’ll go through various software and hardware announcements for Android Wear and TV in separate blog posts, and probably skip Android Auto for now.

So what’s new in Android L Developer Preview?

Material Design

Material Design is is a new design language that will let developer create app which look similar to Google Now. Google chose the name “Material” as it is apparently inspired from real materials such as paper and ink. Android L user interface will be entirely designed with Material Design. The best is to look at an example.

Gmail Now vs Gmail "L"

Gmail Now vs Gmail “L”

On the left, we’ve got the current Gmail app, and on the right the newly designed app for Android L. Lots of it looks like cosmetic changes, but you’ll have noticed the three dot and new mail icons are gone, and all menu will be accessible via the top left icon. There are also some light and shadow effects that will make users feel like they’re touching real elements.

More details can be found in this Material Design presentation (PDF).

Improved Notifications

Notifications have also changed with a new design based on Material, and the ability to display notifications on the lock screen.


I understand lockscreen notifications are optional, and if you don’t like to show them in the lock screen using visibility controls. As you can see from the screenshot above it works very similar to Google Now which cards that you can discard once you’re done. Notifications will also be able to pop-up in games or other full screen apps, and you’ll be able o take action within the notification, for example by declining or accepting a video call request.


The list of recent apps will become the list of recent everything, simply called “Recents”, as it will include both apps, web pages, and documents.

Better Tools for Improving Battery Life

As devices become more powerful, they also become more power hungry despite efforts by SoC designers to reduce energy usage. Badly programmed apps are however the main culprit of short battery life, so Google has introduced Project Volta to help user and developers optimize power consumption. Developers can use “Battery Historian” tool to monitor power consumption of different processes, and which hardware block (e.g. Cellular radio) is currently being used.

Battery_HistorianUsers will also have their own app / feature dubbed “Battery Saver” to improve battery life, and Google claims their Nexus 5 should be able to last an extra 90 minutes on a charge with Battery Saver enabled. This is achieved by reducing the performance of the device once the battery has dropped below 20% charge. At that time, a notification would pop-up to let the user select he wants to enable Battery Saver mode.

Under the hood improvements

As as been widely reported, Google recently killed Dalvik in a recent commit in AOSP, and ART will become the default JAVA runtime using ahead-of-time compilation for speedier application loading time, and memory usage improvements. Google also claims it provides true cross platform support for ARM, MIPS and x86.

Android L will support 64-bit instructions including ARMv8, x86-64 and MIPS64. This will provide a larger number of registers, and increased addressable memory space. Java developers won’t needto change their apps for 64-bit support. One the first Android64 devices is likely to be the Nexus 9 tablet powered by Nvidia Tegra K1 Denver as previously reported.

On the graphics side, Android L adds support for OpenGL ES 3.1, and includes Android Extension Pack for developers with tesselation and geometry shaders and other features that should bring PC and console class graphics to Android games according to Google.

Via Anandtech and Liliputing

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64-bit ARM Server Motherboards by SoftIron

June 20th, 2014 8 comments

We’ve already seen development board such as X-Gene XC-1, and 64-bit ARM servers have been demonstrated by Dell and HP, but SoftIron, a British startup, claims to be the first to provide a production ready ARMv8 solutions for the enterprise server market (e.g. data centers), with its SoftIron 64-0400 and 64-0800 server motherboards powered by Applied Micro X-Gene quad and octa SoC.


Although the company did not release complete pictures of the board, they seem to have done a better job with specifications:

  • SoC
    • SoftIron 64-0400 – Applied Micro X-Gene APM883204 with 4x 64-bit ARMv8 cores @ 2.4 GHz, 4x 32-bit ARMv5 cores for Network/Security offloads and Acceleration, and 1x Cortex M3 for server management
    • SoftIron 64-0800 – Applied Micro X-Gene APM883208 with 8x 64-bit ARMv8 cores @ 2.4 GHz, 4x 32-bit ARMv5 cores for Network/Security offloads and Acceleration, and 1x Cortex M3 for server management
  • System Memory – Up to 128GB ECC DDR3L at 1600MT/s
  • Interfaces
    • 2 x USB 3.0 Superspeed hosts
    • 2 x 10/100/1000 Ethernet RJ-45, and 1 x 100/1000 Ethernet RJ-45 for Server Management (includes Virtual Serial Port)
    • 1 x 10 GbE SFP+
    • 1 x 8 Lane PCIe3.0
    • 4 x SATA 3.0 SSD ports
  • Power supply – + 12 VDC at <7A, Voltage range: 110-240 V AC, Frequency range:50-60 Hz
  • Dimensions – 244 × 244mm (Micro ATX form factor)
  • Enclosure – Rack or Pedestal

SoftIron motherboards only feature one processor socket, and will run Fedora or Ubuntu with Linux 3.x with support for hardware virtualization. I’ve actually just discovered that X-Gene SoCs had ARMv5 and Cortex M3 companion cores to assist with security and server management, actually making APM883208 a 13 cores ARM SoC. If you are interested in the security features allowed by the ARMv5, please refer to “Server Boards –Security Features” (PDF), as I won’t reproduce here the long list of cypher, hash and other security protocols supported by the systems.

SoftIron launched their server motherboards today, but I’m not sure it means it’s already available. Pricing has not been disclosed, but it’s not surprising, as it’s not something individuals will be able to put their hands on. The company will showcase the boards at the 2014 International Supercomputing Conference (ISC), in Leipzig, Germany on June 22-26, 2014. More information is available on SoftIron Products page.

Thanks to David for the tip.

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Cavium ThunderX Server SoC Features up to 48 ARM 64-bit Cores

June 4th, 2014 4 comments

ARM SBSA specification for server supports up to 268,435,456 CPU cores for the second level of standardization on one or a combination of SoCs. We’re not quite up there just yet, but Cavium ThunderX is an ARM server SoC with up to 48 cores on a single chip, which is the highest number of cores I’ve ever heard of in an ARM SoC.

Cavium Thunder X Block Diagram

Simplified Cavium ThunderX Block Diagram

The company created their own custom processor cores using an ARMv8 architecture license, designing an SoC complies with ARM’s Server Base System Architecture (SBSA) standard with the following key features:

  • ARM based SoC that scales up from 8 to 48 cores with up to 2.5 GHz core frequency with 78K I-Cache, 32K D-Cache, and 16MB L2 cache.
  • Fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI)
  • Integrated I/O capacity with 100s of Gigabits of I/O bandwidth
  • 4x DDR3/4 72-bit memory controllers supporting up to 1TB RAM @ 2400 MHz in a dual socket configuration
  • Hundreds of integrated hardware accelerators for security, storage, networking and virtualization applications.
  • Cavium virtSOC technology allowing full system virtualization for low latency from virtual machine to I/O.
  • Best in class performance per watt and performance per dollar for the target applications

ThunderX processor family is comprised of several models depending on target applications: Compute, Storage, Secure Compute, and Networking as well as server chips (CN88XX_X)with 24 to 48 cores, and low-end server chips (CN87XX_X) with 8 to 16 cores.

The server chips are available in 4 SKU families:

  • ThunderX_CP (Compute)
    • Up to 48 cores along with integrated virtSOC, dual socket coherency, multiple 10/40 GbE and high memory bandwidth.
    • Optimized for private and public cloud web servers, content delivery, web caching, search and social media workloads.
  • ThunderX_ST (Storage)

    • Up to 48 cores along with integrated virtSOC, multiple SATAv3 controllers, 10/40 GbE & PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes hardware accelerators for data protection/ integrity/security, user to user efficient data movement (RoCE) and compressed storage.
    • Optimized for Hadoop, block & object storage, distributed file storage and hot/warm/cold storage type workloads.
  • Thunder_SC (Secure Compute)

    • Up to 48 cores along with integrated virtSOC, 10/40 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes Cavium’s 4th generation NITROX and TurboDPI technology with acceleration for IPSec, SSL, Anti-virus, Anti-malware, firewall and DPI.
    • Optimized for Secure Web front-end, security appliances and Cloud RAN type workloads.
  • Thunder_NT (Networking)

    • Up to 48 cores along with integrated virtSOC, 10/40/100 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric with feature rich capabilities for bandwidth provisioning , QoS, traffic Shaping and tunnel termination.
    • Hardware accelerators include high packet throughput processing, network virtualization and data monitoring.
    • Optimized for media servers, scale-out embedded applications and NFV (Network Functions Virtualization) type workloads.

The cost and power optimized ThunderX CN87xx family with 8 to 16 cores will be available in single socket configuration with two DDR3/4 controllers, multiple 10GbE, SATAv3 and PCIe Gen3 interfaces. It will be used for cold storage, distributed content delivery, dedicated hosting, distributed memory caching and embedded and control plane.

Cavium has partnered with several companies, including ODM and OEM partners such as GIGABYTE and Hewlett Packard, is part of Linaro, the Linux Foundation, OpenStack, UEFI, Xen, etc.. industry groups.  Supported operating systems include Canonical’s Ubuntu, RedHat’s Fedora,  MontaVista Linux and openSUSE.  Oracale Java, OpenJDK and GNU toolchain have been ported to the platform, as well as KVM and Xen virtualization platforms.

The company expects ThunderX processors and hardware reference platforms to be available in Q4 2014. Further details may be available on Cavium’s ThunderX page.

Via EETimes

[Update: Here's the pic of the dual socket board (96 cores: 48 + 48) via There's also a single socket version. They all require an heatsink as shown in the bottom left corner of the pi (red/orange heatsink]

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)

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