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Posts Tagged ‘armv8’

ARM based Acer Chromebook R13 is Now up for Sale for $349 and up with Chrome OS or Windows 10

December 29th, 2016 25 comments

Acer Chromebook R13 was unveiled in September as one of the first 64-bit ARM Chromebook. Based on Mediatek MT8173C quad core Cortex A72/A53 processor with 4GB RAM, the “Chromebook” now ships in three variants running either Chrome OS as expected, but also Windows 10 Home.

acer-chromebook-r13All three models share the same specifications, except for storage and operating system options:

  • SoC – Mediatek M8173C quad core processor with 2x ARM Cortex A72 cores @ up to 2.1 GHz, 2x ARM Cortex A53 cores, and a PowerVR GX6250 GPU
  • System Memory – 4GB LPDDR3 RAM
  • Storage
    • CB5-312T-K8Z9 / K6TF – 32 GB eMMC flash + micro SD slot
    • CB5-312T-K0YQ- 64GB eMMC flash + micro SD slot
  • Display – 13.3″ touchscreen IPS LED display; 1920×1080 resolution; 10-point touch; 360-degree hinge design
  • Audio – Integrated microphone, dual built-in speakers, microphone and headphone jacks
  • Video Output – HDMI
  • Camera – HD webcam (1280×720 resolution) with HDR and 720p HD audio/video recording
  • Wireless Connectivity – 2×2 MIMO 802.11ac WiFi and Bluetooth 4.0
  • USB – 1x USB 3.0 port, 1x USB 3.1 type C port for data, video, and power
  • User Input – Touchpad and keyboard
  • Battery – 4670 mAh LiPo battery good for up to 12 hours
  • Power Supply – 45W max
  • Dimensions – 326 x 228 x 15.5 mm
  • Weight – 1.49kg

Acer_Chromebook_R13The official prices listed on Acer website for the three models above are respectively $399.99, $429.99 (64GB storage), and $399.99 (Windows 10 Home), but CB5-312T-K8Z9 (32GB + Chrome OS) model is now on sale on BestBuy for $349, while the 64GB model is sold for $439.99 on TigerDirect, and CB5-312T-K6TF Windows 10 “ChromeBook” goes for $407.99 on TigerDirect.

Thanks to Martin for the tip.

Avantek H270-T70 384-core ARM Server Powered by Cavium ThunderX SoCs Can Be Bought Online

December 14th, 2016 10 comments

ARM servers have been around for a while, but usually it’s pretty hard to buy for individuals, and developer’s boards such as LeMaker Cello are never in stock, probably because the project has been canceled or suffered from further delays. However, if you have some uses for ARM servers and the cash that goes with it, Avantek Computer (UK) is selling some ARM based servers starting from an 1U Rack with a quad core Annapurna Alpine AL5140 processor up to Avantek H270-T70 with a 2U rack equipped with multiple Cavium ThunderX SoCs providing 384 ARMv8 cores to play with.

cavium-thunderx-arm-server-rackAvantek H270-T70 server key features and specifications:

  • SoCs – 8x Cavium ThunderX CN8890 processors with 48 custom ARMv8 cores each
  • System Memory – 64x DDR4 ECC slots for up to 8TB memory
  • Storage – 16x 2.5” hot-swappable HDD/SSD bays
  • Connectivity – 8x 40GbE QSFP+ fiber ports (Cortina CS4343 controllers)
  • Power Supply – 1600W 80 PLUS Platinum redundant PSU
  • 2U Rack System with 4 nodes with front access to the node trays

The server is compliant with ARM’s Server Base System Architecture (SBSA) and Server Base Boot Requirements (SBBR), which means you can load any compliant OS on the server such as Red Hat Enterprise Linux Server, SUSE Linux Enterprise Server 12, FreeBSD 11 and others.

64-bit-arm-server-for-saleSo I went through the check out process for Avantek 384 core server and I could go until the process payment step without issues, except I had to use a UK address. However, I did not press the “Place Order” button since 1. I don’t actually have a UK address (a forwarder could provide that), and 2. I don’t feel like spending around 15,000 GBP (~$19,000 US) for the system, plus whatever is needed for the hard drives and memory :). If your budget is also restrained, but would like a ThunderX server, you can opt to get Avantek 32-core 1U rack system for about 1,500 GBP (~$1900 US) and up.

Thanks to Sander for the tip.

Qualcomm Starts Sampling of Qualcomm Centriq 2400 ARM Server SoC with Up to 48 ARMv8 Cores

December 8th, 2016 3 comments

Qualcomm has announced commercial sampling of Qualcomm Centriq 2400 series server SoC built with 10nm FinFET process technology and featuring up to 48 Qualcomm Falkor custom ARMv8 CPU cores “highly optimized to both high performance and power efficiency, and designed to tackle the most common datacenter workloads”.

qualcomm-centriq-2400-series-soc

Qualcomm Datacenter Technologies demonstrated the new processor in a Live demo showing Apache, Spark, Java, and Hadoop on Linux running on a SBSA compliant server powered by Qualcomm Centriq 2400 processor, but the company did not provide any further technical details or preliminary benchmark results for the solution.

The Qualcomm Centriq 2400 processor series is now sampling to select customers and is expected to be commercially available in H2 2017. That’s about all we know from the press release. However, Linaro have been working on Qualcomm Technologies QDF2432 based board for several months with support for Debian 8.x ‘Jessie’ and CentOS 7 operating systems, as well as Hadoop and OpenStack. It’s not 100% clear if this is indeed related to Centriq 2400, albeit the name QDF2432 seems to indicate so, and it would probably have started on some FPGA board to simulate Centriq 2400 (32-core?) processor, unless they had engineering samples for nearly a year. There’s also a basically empty page on Centos.org for “Qualcomm QDF2432 Server Dev Platform”. It’s close to impossible to find much details since those things are developed under NDAs.

Intel Has Started Sampling Altera Stratix 10 ARM Cortex A53 + FPGA SoC

October 12th, 2016 5 comments

Intel bought Altera last year, which means Intel is now in the FPGA business, and the company has recently announced they had started to provide samples of Startix 10 SoC manufactured using Intel 14 nm tri-gate process. The interesting part if that beside FPGA fabric, the SoC also includes four ARM Cortex A53 cores.

intel-stratix-10-fpga-arm

Intel / Altera Stratix 10 SoC key features and specifications:

  • Processor – Quad-core ARM Cortex-A53 MP Core up to 1.5 GHz
  • Logic Core Performance –  1 GHz
  • Logic Density Range – 500K LE – 5.5M LE
  • Embedded Memory – 229 Mb
  • Up to 11,520 18 x 19 Multipliers
  • Up to 144 Transceivers up to 30 Gbps data rate (Chip to Chip)
  • Memory Devices Supported – DDR4 SDRAM @ 1,333 MHz,DDR3 SDRAM @ 1066 MHz, LPDDR3 @ 800 MHz, RLDRAM 3 @ 1200 MHz, QDR IV SRAM @ 1066 MHz, QDR II+ SRAM @ 633 MHz, Hybrid Memory Cube
  • Hard Protocol IP – 3 EMACs, PCI Express Gen3 X 8, 10/40G BaseKR- forward error correction (FEC), Interlaken physical coding sublayer (PCS)
  • Security – AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, multi-factor key infrastructure with layered hierarchy for root of trust, side channel attack protection

Compared to the previous FPGA generation (Stratix V), Intel claims twice the core performance, five times the density, up to 70% lower power consumption, up to 10 TFLOPS single-precision floating point DSP performance, and up to 1 TBps memory bandwidth with integrated High-Bandwidth Memory (HBM2) in-package.

The new FPGA family targets data centers and networking infrastructures, which require high-bandwidth, multiple protocols and modulation schemes support, with a high performance-per-watt ratio.

You’ll find more details on Altera Stratix 10 FPGA product page.

Categories: Altera Cyclone, Hardware Tags: altera, arm, armv8, fpga, intel

Linux 4.8 Release – Main Changes, ARM & MIPS Architectures

October 4th, 2016 4 comments

Linus Torvalds has officially released Linux 4.8 last Sunday:

So the last week was really quiet, which maybe means that I could probably just have skipped rc8 after all. Oh well, no real harm done.

This obviously means that the merge window for 4.9 is open, and I appreciate the people who already sent in some pull requests early due to upcoming travel or other reasons. I’ll start pulling things tomorrow, and have even the most eager developers and testers hopefully test the final 4.8 release before the next development kernels start coming 😉

Anyway, there’s a few stragging fixes since rc8 listed below: it’s a mixture of arch fixes (arm, mips, sparc, x86), drivers (networking, nvdimm, gpu) and generic code (some core networking, with a few filesystem, cgroup and and vm things).

All of it pretty small, and there really aren’t that many of them. Go forth and test,
Linus

Linux 4.7 introduced support for AMD Radeon RX480 GPUs, parallel directory lookups, the new “schedutil” frequency governor with lower latency, EFI ‘Capsule’ firmware updates, and much more.

linux-4-8-changelogSome notable Linux 4.8 changes include:

  • HDMI-CEC framework
  • Kernel documentation system is now based on Sphinx
  • GPIO subsystem has a new user-space ABI for the management of general-purpose I/O lines; it is based on char devices and replaces the long-deprecated sysfs interface. You can check out tools/gpio/ directory with lsgpio, gpio-hammer, and gpio-event-mon for examples
  • Various file systems improvements for Btrfs, EXT-4 (unified encryption), OrangeFS (better in-kernel caching), Ceph (RADOS namespace support), XFS (Reverse-mapping support), etc…

Some improvements and new features specific to the ARM architecture and corresponding hardware platforms:

  • Allwinner:
    • Allwinner A10/A20 – Display engine clocks (TCON, FE, DE), I2S audio interface (ASoC) driver, added NFC node to DTS
    • Allwinner H3 – Clocks (through sunxi-ng), USB multi-reset lines support
    • AXP2xx driver – External drivebus support, AXP223 USB power supply support, AXP809 PMIC support
    • Broadcom BCM53125 support as it’s used in Lamobo / Banana Pi R1 router board.
    • New boards – Polaroid MID2407PXE03 & inet86dz (Allwinner A23 tablets), Banana Pi M1+, Banana Pi M2+, Allwinner Parrot (Allwinner R16 EVB)
  • Rockchip:
    • Many new peripherals added to RK3399 (eDP, clock controller, etc…)
    • Preparations to use generic DMA mapping code in the Rockchip IOMMU driver
    • Fixes for eMMC controller, SPI controller, eDP controller, and I2C
  • Amlogic
    • AmLogic meson8b clock controller (rewritten)
    • AmLogic gxbb clock controller
    • Reset controller driver for Amlogic Meson
    • New watchdog driver for Amlogic Meson GXBB (S905) SoC
    • Added support for Amlogic Meson RNG in crypto drivers
    • Some Amlogic ARM64 DTS updates
  • Samsung
    • Enable drivers for Exynos7 and Exynos5433 based boards: S2MPS clock driver, SoC: RTC, SPI, watchdog, EHCI, OHCI, DWC3, ADC and PWM, Enable Samsung SoC sound
    • Samsung ARM64 DTS Changes – Adjust the voltage of CPU buck regulator so scaling could work.
    • Samsung DTS changes
      • Add missing async bridge for MFC power domain on Exynos5420. This fixes imprecise abort on s5p-mfc re-bind.
      • Define regulator supplies for MMC nodes on Exynos4412 Odroid boards and for TMU on Exynos542x Peach boards.
      • Thermal cleanups on Odroid XU3-family (Exynos5422).
      • Enable AX88760 USB hub on Origen board (Exynos4412)
      • Disable big.LITTLE switcher so the cpufreq-dt could be enabled.
      • Enable Samsung media platform drivers.
      • Enable some board-specific drivers for boards: Trats2, Universal C210.
      • Enable Virtual Video Test Driver on nulti_v7 and exynos defconfigs. Useful for testing
    • Samsung drivers/soc updates:
      • Move the power domain driver from arm/mach-exynos and prepare for supporting ARMv8.
      • Add COMPILE_TEST.
      • Make SROMC driver explicitly non-module.
      • Endian-friendly fixes.
      • Fix size of allocation for Exynos SROM registers (too much was allocated)
    • Add CEC interface driver present in the Samsung Exynos SoCs
    • Added support for Exynos 5410 Odroid XU board
  • Qualcomm
    • Added MDM9615 support
    • Qualcomm ARM Based Driver Updates:
      • Rework of SCM driver
      • Add file patterns for Qualcomm Maintainers entry
      • Add worker for wcnss_ctrl signaling
      • Fixes for smp2p
      • Update smem_state properties to match documentation
      • Add SCM Peripheral Authentication service
      • Expose SCM PAS command 10 as a reset controller
      • Fix probe order issue in SCM
      • Add missing qcom_scm_is_available() API
    • Qualcomm ARM64 Updates
      •  Enable assorted peripherals on APQ8016 SBC
      • Update reserved memory on MSM8916
      • Add MSM8996 peripheral support
      • Add SCM firmware node on MSM8916
      • Add PMU node on MSM8916
      • Add PSCI cpuidle support on MSM8916
    • Qualcomm Device Tree Changes:
      • Reverse BAM dma node reverts
      • Add BAM remote control options for affected platforms
      • Enable peripherals on APQ8074 dragonboard
      • Enable PMA8084 pwrky
      • Fix PMIC reg entries by removing unnecessary size element
      • Add SCM binding and support for all currently supported boards
      • Add Qualcomm WCNSS binding documentation
      • Rename db600c to SD_600eval and add peripheral nodes
      • Remove gpio key entry from Nexus7
      • Add APQ8060 based dragonboard and associated peripherals
      • Add ARMv7 PMU for IPQ4019
      • Update smem state cells to match documentation
    • ARM64 defconfig: Enable PM8xxx pwrkey support, enable MSM8996 support
    • ARM defconfig: Enable MSM9615 board support, enable MSM8660 pinctrl support
  • Mediatek
    • Added Mediatek MT6755
    • Display subsystem added to MT8173
    • Support for Mediatek generation one IOMMU hardware
    • New drivers for Mediatek MT6323 regulator
    • new encoding codec driver for Mediatek SoC (linux-media): H.264/VP8/V4L2 video encoder drivers for MT8173
  • ARM64 – arm64 architecture has gained support for the kexec mechanism (allowing one kernel to boot directly into another) and kernel probes.
  • Other new ARM hardware or SoCs – NXP i.MX 7Solo, Broadcom BCM23550, Cirrus Logic EP7209 and EP7211 (clps711x platforms), Hisilicon HI3519, Renesas R8A7792, Apalis Tegra K1 board, LG LG1313, Renesas r8a7796, Broadcom BCM2837 (used in Raspberry Pi 3)

MIPS architecture changelog:

  • Fix memory regions reaching top of physical
  • MAAR: Fix address alignment
  • vDSO: Fix Malta EVA mapping to vDSO page structs
  • uprobes: fix incorrect uprobe brk handling, select HAVE_REGS_AND_STACK_ACCESS_API
  • Avoid a BUG warning during PR_SET_FP_MODE prctl
  • SMP: Fix possibility of deadlock when bringing CPUs online
  • R6: Remove compact branch policy Kconfig entries
  • Fix size calc when avoiding IPIs for small icache flushes
  • Fix pre-r6 emulation FPU initialisation
  • Fix delay slot emulation count in debugfs
  • CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems
  • CPS: Avoid BUG() when offlining pre-r6 CPUs
  • DEC: Avoid gas warnings due to suspicious instruction scheduling by manually expanding assembler macros.
  • FTLB: Fix configuration by moving configuration after probing, clear execution hazard after changing FTLB enable
  • Highmem: Fix detection of unsupported highmem with cache aliases
  • I6400: Don’t touch FTLBP chicken bits
  • microMIPS: Fix BUILD_ROLLBACK_PROLOGUE
  • Malta: Fix IOCU disable switch read for MIPS64
  • Octeon: Fix probing of devices attached to GPIO lines, fix kernel header to work for VDSO build, fix initialization of platform device probing.

You can find the full list of changes in Linux 4.8 changelog with comments only generated using git log v4.7..v4.8 --stat. A list of changes for Linux 4.8 will also soon be found on kernelnewbies.org.

Nvidia Unveils Xavier Automotive & AI Octa-core SoC with 512-Core Volta GPU, 8K Video Decode & Encode

September 29th, 2016 2 comments

Nvidia has introduced the successor to their Parker SoC mostly targeting self-driving cars and artificial intelligence applications, with Xavier SoC featuring 8 custom ARMv8 cores, a 512-core Volta GPU, a VPU (Video Processing Unit) supporting 8K video decode and encode and HDR (High Dynamic Range), as well as a computer vision accelerator (CVA).

nvidia-xavier The processor will deliver 20 TOPS (trillion operations per second) of performance, while consuming only 20 watts of power, and since it’s designed specifically for autonomous cars, it will comply with automotive safety standards such as ISO 26262 functional safety specification.

Anandtech published a comparison table with Tegra X1 (Erista), Parker, and Xavier using currently available information.

Xavier Parker Erista (Tegra X1)
CPU 8x NVIDIA Custom ARM 2x NVIDIA Denver +
4x ARM Cortex-A57
4x ARM Cortex-A57 +
4x ARM Cortex-A53
GPU Volta, 512 CUDA Cores Pascal, 256 CUDA Cores Maxwell, 256 CUDA Cores
Memory ? LPDDR4, 128-bit Bus LPDDR3, 64-bit Bus
Video Processing 7680×4320 Encode & Decode 3840x2160p60 Decode
3840x2160p60 Encode
3840x2160p60 Decode
3840x2160p30 Encode
Transistors 7B ? ?
Manufacturing Process TSMC 16nm FinFET+ TSMC 16nm FinFET+ TSMC 20nm Planar

The company goes on to say a single Xavier-based AI car supercomputer will be able to replace today’s fully configured DRIVE PX 2 with two Parker SoCs and two Pascal GPUs. The new platform will be much smaller as illustrated below, consumes much less power at 20 Watt, or 25% of the power consumption of PX DRIVE 2, and deliver the same AI performance (20 TOPS), as well as around 33% better integer performance (160 SPECINT).

nvidia-px-drive-2-vs-xavier-board

Xavier will start sampling in Q4 2017, and be available to automakers, tier 1 suppliers, startups and research institutions working on self-driving cars.

Nvidia has also uploaded a video showing the deep learning capabilities of their PX DRIVE 2 computer on a self-driving car that learned to drive in California, before driving in New Jersey.

Nvidia Provides More Details About Parker Automotive SoC with ARMv8 Cores, Pascal GPU

August 23rd, 2016 9 comments

Nvidia demonstrated DRIVE PX2 platform for self-driving cars at CES 2016, but did not give many details about the SoC used in the board. Today, the company has finally provided more information about Parker hexa-core SoC combining two Denver 2 cores, and four Cortex A57 cores combining with a 256-core Pascal GPU.

Nvidia_Parker_Block_DiagramNvidia Parker SoC specifications:

  • CPU – 2x Denver 2 ARMv8 cores, and 4x ARM Cortex A57 cores with 2MB + 2 MB L2 cache, coherent HMP architecture (meaning all 6 cores can work at the same time)
  • GPUs – Nvidia Pascal Geforce GPU with 256 CUDA cores supporting DirectX 12, OpenGL 4.5, Nvidia CUDA 8.0, OpenGL ES 3.1, AEP, and Vulkan + 2D graphics engine
  • Memory – 128-bit LPDDR4 with ECC
  • Display – Triple display pipeline, each at up to 4K 60fps.
  • VPU – 4K60 H.265 and VP9 hardware video decoder and encoder
  • Others:
    • Gigabit Ethernet MAC
    • Dual-CAN (controller area network)
    • Audio engine
    • Security & safety engines including a dual-lockstep processor for reliable fault detection and processing
    • Image processor
  • ISO 26262 functional safety standard for electrical and electronic (E/E) systems compliance
  • Process – 16nm FinFet
PX Drive 2 Board with two Parker SoCs

PX Drive 2 Board with two Parker SoCs

Parker is said to deliver up to 1.5 teraflops (native FP16 processing) of performance for “deep learning-based self-driving AI cockpit systems”.

This type of board and processor is normally only available to car and part manufacturer, and the company claims than 80 carmakers, tier 1 suppliers and university research centers are now using DRIVE PX 2 systems to develop autonomous vehicles. That means the platform should find its way into cars, trucks and buses soon, including in some 100 Volvo XC90 SUVs part of an autonomous-car pilot program in Sweden slated to start next year.

Allwinner A64 based Pine A64 and Banana Pi M64 Boards Can Now Run Windows 10 IoT Core

August 4th, 2016 8 comments

Windows IoT is a version of Windows 10 that’s optimized for smaller devices with or without a display, and was fist released for Raspberry Pi 2 and MinnowBoard MAX. Since then a few more boards are now officially supported, including DragonBoard 410c, and Raspberry Pi 3. But there’s been some recent developments as two Allwinner A64 64-bit ARM boards are now supported according to two wiki entries (here and there) explaining how to run a simple Csharp sample on Windows 10 IoT Core on either Banana Pi M64 or Pine A64 boards.

Windows_10_IoT_Allwinner_A64The guide shows how to configure Azure IoT Hub, register the IoT device, and build and deploy Azure IoT SDK on the board.

But basically if all you want to is to run Windows IoT core on either board, you’ll need to download either:

  • Windows 10 IoT Core for Banana Pi M64: Windows10IoT_BPI-M64.ffu (Link removed as Microsoft does not allow redistribution of ffu for now, despite the link being available directly on github without SLA)
  • Windows 10 IoT Core for Pine A64/A64+: Windows10IoT_Pine64.ffu (Link removed as Microsoft does not allow redistribution of ffu for now, despite the link being available directly on github without SLA)

Then install and run IoT Dashboard in a Windows computer, select the Setup new device tab, then Customize, and load the FFU firmware file to flash it to an 8GB micro SD card. Once it’s done, insert the micro SD card into the board, and it should run Windows 10 IoT Core at next boot.

Windows 10 IoT Core has also been ported to few other Intel based embedded computers, as well as Toradex Colibri T30 Tegra 3 system-on-module.

[Update: Allwinner has uploaded a video showing Pine A64 with Windows 10 IoT Core (Video removed, as Microsoft does not like that video being published together with the press release. Maybe because it shows they’ve yet to implement Ethernet….)]

Via Bird on SMEoT Facebook Group