Posts Tagged ‘automotive’

Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

October 13th, 2016 No comments

Imagination has just unveiled the successor of MIPS I6400 64-Bit Warrior Core with MIPS Warrior I-class I6500 heterogeneous CPU supporting up to 64 cluster, with up to 6 cores each (384 cores max), themselves up to 4 thread (1536 max), combining with IOCU (IO coherence units), and external IP such as PowerVR GPU or other hardware accelerators.

mips-i6500-scalable-computeThe main features of MIPS I6400 processor are listed as follows:


  • Heterogeneous Inside – In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels.
  • Heterogeneous Outside – The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system efficiency.
  • Simultaneous Multi-threading (SMT) – Based on a superscalar dual issue design implemented across generations of MIPS CPUs, this  feature enables execution of multiple instructions from multiple threads every clock cycle, providing higher utilization and CPU efficiency.
  • Hardware virtualization (VZ) – I6500 builds on the real time hardware virtualization capability pioneered in the MIPS I6400 core. Designers can save costs by safely and securely consolidating multiple CPU cores with a single core, save power where multiple cores are required, and dynamically and deterministically allocate CPU bandwidth per application.
  • SMT + VZ – The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, makes the I6500 ideal for applications which require deterministic code execution.
  • Designed for compute intensive, data processing and networking applications – The I6500 is designed for high-performance/high-efficiency data transfers to localized compute resources with data scratchpad memories per CPU, and features for fast path message/data passing between threads and cores.
  • OmniShield-ready – Imagination’s multi-domain security technology used across its processing families enables isolation of applications in trusted environments, providing a foundation for security by separation.

The processor is also based on the standard MIPS ISA, so developer will be able to leverage existing software and tools such as compilers, debuggers, operating systems, hypervisors and application software already optimized for the MIPS ISA.



The figure above shows what an SoC based on MIPS I6500 may look like with one cluster with 4 CPU cores, 2 IOCUs, another cluster with any CPU cores but instead eight IOCUs interlinked with third party accelerators, and one PowerVR GPU.

Target applications include advanced driver assistance systems (ADAS), autonomous vehicles, networking, drones, industrial automation, security, video analytics, machine learning, and more. One of the first customer for the new processor is Mobileye EyeQ5 SoC designed for  Fully Autonomous Driving (interestingly shortened as “FAD”) vehicles will eight multi-threaded MIPS CPU cores coupled with eighteen cores of Mobileye’s Vision Processors (VPs). EyeQ5 SoC should be found in vehicles as early as 2021.

MIPS I6500 CPU can be licensed now, with general availability planned for Q1 2017.You’ll find more technical details on the product page, and blog post for the announcement.

Meet NXP i.MX8 Processor Families: i.MX 8 for High performance, i.MX 8M for Audio/Video & i.MX 8X for Low Power

October 6th, 2016 4 comments

Freescale and then NXP have been talking about i.MX8 processors for several years, and this spring unveiled i.MX 8 Multisensory Enablement Kit without giving much details about the processor except it would include both Cortex A72 & A53 cores. But NXP put out a press release yesterday about “Multisensory Automotive eCockpit Platform to Advance Multimedia Experiences in Future Cars” which appears to be the same news but with different words, except the content of the PR has more interesting bits such as:

The new family, which is based on up to six 64-bit ARMv8-A technology processor cores and includes a HiFi 4 DSP, LPDDR4 and DDR4 memory support as well as dual Gigabit Ethernet with audio video bridging (AVB) capability, is designed to advance automotive dashboard graphics such as instrument clusters, infotainment visuals, heads-up displays, rear-seat screens and more. Capable of driving four HD screens with independent content or a 4K screen, the new devices introduced today include:

  • i.MX 8QuadMax which integrates two ARM Cortex®-A72 cores, four Cortex-A53 cores, two Cortex-M4F cores and two GC7000XS/VX GPUs
  • i.MX 8QuadPlus which integrates one ARM Cortex-A72 core, four Cortex-A53 cores, two Cortex-M4F cores and two GC7000LiteXS/VX GPUs
  • i.MX 8Quad which integrates four Cortex-A53 cores, two Cortex-M4F cores and two GC7000LiteXS/VX GPUs
Click to Enlarge - Source NXP and EETimes

Click to Enlarge – Source NXP and EETimes

Hmm… SoCs with two identical GPUs? That’s because automotive applications often require multiple operating systems running on a single processor, with maybe one part handling the “infotainment” screen, and another taking care of the dashboard, which has to be 100% stable. This is usually handled by a software hypervisor but i.MX 8 processors can do this mostly using hardware virtualization, and does not require safety critical and non-safety critical software to share the same part of the hardware.

The new processors currently support for Android, Linux, FreeRTOS, QNX, Green Hills, and Dornerworks XEN, multiple temperature grades including automotive AEC-Q100 grade 3 (-40° to 125° C Tj), industrial (-40° to 105° C Tj), and consumer (-20° to 105° C Tj), and are fully supported on NXP’s 10 and 15-year Longevity Program. You’ll find a few more details about NXP i.MX8 processors slated to go into mass production in Q1 2017 on the product page.

However, while searching for more details about i.MX 8, I’ve come across a PDF file dated July 15, 2016, revealing more i.MX8 processor families are on the way with i.MX 8M series for audio/video applications with 4K VP9/H.265 and HDR support, and i.MX 8X series based on  ARM Cortex A35 / M4 cores for low power applications.

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The document also informs us that two more i.MX 8 processors are planned with i.MX 8Dual and i.MX 8DualLite dual core Cortex A53 SoCs.

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But let’s go back to i.MX 8M series with four SKUs namely 8M Quad Video, 8M Dual Video, 8M Quad Audio, and 8M Solo Audio.

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All features one, two or four Cortex A53 cores, a real-time Cortex M4 cores, 1080p to 4K video support, 20 channels audio, USB 2.0 or 3.0 interfaces, and DTS and Dolby Atmos support. The processors will be used in streaming media clients, networked speakers, soundbars or AV receivers, or some embedded clients in consumer or industrial sectors.

NXP i.MX 8X series will first include 3 SKUs: i.MX 8QuadXPlus, i.MX 8DualXPlus, and i.MX 8DualX all powered by one to four ARM Cortex A35 cores and supporting up to 3 displays.

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Click to Enlarge

The processors will target display and audio applications, 3D graphic display clusters, telematics and V2X (Vehicle to everything) applications.

NXP i.MX 8M and 8X are not listed on NXP website yet, but I’d assume they’d go to mass production sometimes in 2017, when they may have become Qualcomm i.MX 8 processors…

Nvidia Unveils Xavier Automotive & AI Octa-core SoC with 512-Core Volta GPU, 8K Video Decode & Encode

September 29th, 2016 2 comments

Nvidia has introduced the successor to their Parker SoC mostly targeting self-driving cars and artificial intelligence applications, with Xavier SoC featuring 8 custom ARMv8 cores, a 512-ore Volta GPU, a VPU (Video Processing Unit) supporting 8K video decode and encode and HDR (High Dynamic Range), as well as a computer vision accelerator (CVA).

nvidia-xavier The processor will deliver 20 TOPS (trillion operations per second) of performance, while consuming only 20 watts of power, and since it’s designed specifically for autonomous cars, it will comply with automotive safety standards such as ISO 26262 functional safety specification.

Anandtech published a comparison table with Tegra X1 (Erista), Parker, and Xavier using currently available information.

Xavier Parker Erista (Tegra X1)
CPU 8x NVIDIA Custom ARM 2x NVIDIA Denver +
4x ARM Cortex-A57
4x ARM Cortex-A57 +
4x ARM Cortex-A53
GPU Volta, 512 CUDA Cores Pascal, 256 CUDA Cores Maxwell, 256 CUDA Cores
Memory ? LPDDR4, 128-bit Bus LPDDR3, 64-bit Bus
Video Processing 7680×4320 Encode & Decode 3840x2160p60 Decode
3840x2160p60 Encode
3840x2160p60 Decode
3840x2160p30 Encode
Transistors 7B ? ?
Manufacturing Process TSMC 16nm FinFET+ TSMC 16nm FinFET+ TSMC 20nm Planar

The company goes on to say a single Xavier-based AI car supercomputer will be able to replace today’s fully configured DRIVE PX 2 with two Parker SoCs and two Pascal GPUs. The new platform will be much smaller as illustrated below, consumes much less power at 20 Watt, or 25% of the power consumption of PX DRIVE 2, and deliver the same AI performance (20 TOPS), as well as around 33% better integer performance (160 SPECINT).


Xavier will start sampling in Q4 2017, and be available to automakers, tier 1 suppliers, startups and research institutions working on self-driving cars.

Nvidia has also uploaded a video showing the deep learning capabilities of their PX DRIVE 2 computer on a self-driving car that learned to drive in California, before driving in New Jersey.

ARM Unveils Cortex-R52 ARMv8-R CPU Core for Safety-Critical Systems

September 20th, 2016 No comments

ARM has introduced their very first ARMv8-R real-time 32-bit CPU core with Cortex-R52 designed for safety-critical applications in the automotive, industrial and health-care markets. It has been designed to address higher workloads with increased performance (up to 35%) compared to Cortex-R5 processor.

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Click to Enlarge

The processor should be used in systems capable of fulfilling IEC 61508 SIL 3 and ISO 26262 ASIL D functional safety requirements. ARM explains the new processor address both random errors for example bit flipping from radiation, and systemic errors more related to software or design faults.


The latter can be addresses with the right development processes, including following aforementioned functional safety standards, but random errors require some extra hardware features such as ECC memory, or dual core lock step processors, where instructions are run on two processors simultaneously and results compared.

Normally, the whole software stack must be validated and certified on safety-critical systems, even for part of the code that may not be safety-critical. This is a time-consuming and costly endeavor however, and as software becomes ever more complex becomes an issue. So Cortex R52 cores also implement a Level 2 MPU running monitor or hypervisor software, which can help separating safety code, critical safety code and non-safety code.

arm-processor-real-time-coreCortex-R52 cores would typically be used in conjunction with Cortex-A cores running non-safety code, and offering higher performance, throughput, and more peripherals. Some current processors featuring Cortex-Rxx cores include Xilinx Zynq UltraScale+ MPSoC (Cortex-R5), and Renesas R-Car H3 automotive SoC (Cortex-R7).

You may want to visit ARM Cortex-R52 product page for a few more details.

Rockchip RK1108 Cortex A7 + DSP SoC is Made for Audio & Video Conference and Recording Applications

September 8th, 2016 No comments

Rockchip has introduced RK1108 ARM Cortex A7 SoC with a 600 MHz DSP targeting visual communication, consumer electronics, automotive DVR, and security applications thanks to its 8-channel I2S audio codec and 1440p H.264 video encoder and decoder.

rockchip-rk1108Detailed specifications can be found on the official Rockchip Wiki:

  • CPU – Single-core ARM Cortex-A7 Core processor with NEON and FPU,  32KB/32KB L1 I-Cache/D-Cache, Unified 128KB L2 Cache, and Trustzone
  • Video/Image DSP – Up to 600 MHz, 32KB I-TCM and 32KB I-cache, 128KB D-TCM
  • Memory
    • 12KB internal SRAM
    • DDR3/DDR3L interface – 16 Bits data width, 1 ranks (chip selects), up to 512 MB RAM
    • NAND Flash Interface – 8-bit async NAND flash, 16-bit hardware ECC
    • eMMC Interface – Compatible with standard iNAND interface, eMMC 4.51 standard.
    • SD/MMC Interface – Compatible with SD 3.0, MMC 4.41
  • System Component
    • 2x 64-bit timers with interrupt-based operation
    • 8x PWMs with interrupt-based operation
    • WatchDog timer
  • Video
    • Video decoder of H.264 up to HP level 5.0; [email protected] (2560×1440) max
    • Video encoder for H.264 up to HP level4.2
  • JPEG decoder and encoder up to respectively 8176×8176 and 8192×8192
  • Display
    • 10-bit DAC TV encoder up to 480i/576i (CVBS)
    • HDMI 1.4 up to 1080p60
    • 4-lane MIPI DSI interface up to 720p @ 60fps.
  • Camera interface – Up to 5M pixels, 8-bit BT656 (PAL/NTSC), 16-bit BT601, and 8-/10-/12-bit raw data interfaces
  • Audio
    • Codec – 24-bit DAC with Line-out, up to 96 KHz sampling rate, mono, stereo, and 5.1 audio support.
    • I2S0 with 8 channels – I2S0/I2S1 supports up to 8 channels (8xTX, 8xRX);
    • I2S1/I2S2 (PCM) with 2 channels – Up to 2 channels (2xTX, 2xRX) ; 16- to 32-bit audio resolution; up to 192KHz sample rate
  • Peripherals
    • SDIO 3.0 interface
    • GMAC 10/100M Ethernet Controller
    • 1x SPI Controller, 1x SFC, 3x UART controllers, 4x I2C controllers
    • 3x USB 2.0 host interfaces
    • 1x USB 2.0 OTG interface up to 480Mbps
  • Misc
    • Temperature Sensor (TS-ADC) – 10-bits ADC up to 50KS/s. -40~125C temperature range and 5C temperature resolution
    • SAR-ADC (Successive Approximation Register) – 10-bit ADC up to 1MS/s. 6 single-ended input channels. Current consumption: 0.5mA @ 1MS/s
    • eFuse –  2x 256-bit (32×8) high-density electrical fuses
Rockchip RK1108 Development Board (EVB)

Rockchip RK1108 Development Board (EVB)

There’s no much more information at this stage, and beside the evaluation board shown above, I could not find devices based on Rockchip RK1108 processor yet. Some code has been pushed to GeekboxZone Linux kernel repo in Github.

The company also unveiled Rockchip PX5 octa-core Cortex A53 processor for automotive applications with support for ADAS algorithms, and 4K60 video decoding, but there’s even less information than for RK1108 so far.

Via Rockchip Twitter account.

Nvidia Provides More Details About Parker Automotive SoC with ARMv8 Cores, Pascal GPU

August 23rd, 2016 9 comments

Nvidia demonstrated DRIVE PX2 platform for self-driving cars at CES 2016, but did not give many details about the SoC used in the board. Today, the company has finally provided more information about Parker hexa-core SoC combining two Denver 2 cores, and four Cortex A57 cores combining with a 256-core Pascal GPU.

Nvidia_Parker_Block_DiagramNvidia Parker SoC specifications:

  • CPU – 2x Denver 2 ARMv8 cores, and 4x ARM Cortex A57 cores with 2MB + 2 MB L2 cache, coherent HMP architecture (meaning all 6 cores can work at the same time)
  • GPUs – Nvidia Pascal Geforce GPU with 256 CUDA cores supporting DirectX 12, OpenGL 4.5, Nvidia CUDA 8.0, OpenGL ES 3.1, AEP, and Vulkan + 2D graphics engine
  • Memory – 128-bit LPDDR4 with ECC
  • Display – Triple display pipeline, each at up to 4K 60fps.
  • VPU – 4K60 H.265 and VP9 hardware video decoder and encoder
  • Others:
    • Gigabit Ethernet MAC
    • Dual-CAN (controller area network)
    • Audio engine
    • Security & safety engines including a dual-lockstep processor for reliable fault detection and processing
    • Image processor
  • ISO 26262 functional safety standard for electrical and electronic (E/E) systems compliance
  • Process – 16nm FinFet
PX Drive 2 Board with two Parker SoCs

PX Drive 2 Board with two Parker SoCs

Parker is said to deliver up to 1.5 teraflops (native FP16 processing) of performance for “deep learning-based self-driving AI cockpit systems”.

This type of board and processor is normally only available to car and part manufacturer, and the company claims than 80 carmakers, tier 1 suppliers and university research centers are now using DRIVE PX 2 systems to develop autonomous vehicles. That means the platform should find its way into cars, trucks and buses soon, including in some 100 Volvo XC90 SUVs part of an autonomous-car pilot program in Sweden slated to start next year.

NXP Unveils i.MX 8 Multisensory Enablement Kit with Hexa Core ARMv8 Processor

May 17th, 2016 8 comments

Freescale, now NXP, i.MX 8 processors have been a long time coming, but finally the company has now unveiled a Multisensory Enablement Kit based on i.MX 8 hexa core ARMv8 processor combined with a Vulkan-ready & OpenCL capable GPU.

i.MX8_Multisensory_Enablement_KitKey features of the development kit:

  • Multisensory Processor Board
  • Multisensory Expansion Board
  • Isolation and separation of secure, safe and open domains
  • Rich compute (6x ARMv8 64-bit main CPUs, OpenCL GPU)
  • Vulkan-ready GPU with HW tessellation and geometry shading
  • Efficient, multi-screen (4x) support via HW virtualization
  • Failover-ready display path
  • Up to 8x camera input for 360 degree vision
  • Integrated vision processing
  • HDR enhanced video
  • Multi-sensor fusion and expansion
  • Multi-core audio and speech processing
  • NXP radio solution integration

However, at the time of writing, there’s very little information about i.MX8 processors themselves, but I’m confident much more info should soon surface as NXP FTF 2016 is taking place now until May 19, 2016. The press release about i.MX8 MEK does mention 4K video and graphics, and some security features. The company expects the processor to be used for for intuitive gesture control, voice recognition, natural speech recognition and audio acceleration, as well as healthcare and industrial applications such as connected vehicles.

NXP i.MX 8 MEK is said to be available now, together with the BSPs and middleware. More details should eventually be posted on i.MX8 MEK page.

[Update: I found a slide about i.MX8 with some details. Source: NXP Forums.

Click to Enlarge

Click to Enlarge

Categories: Hardware, Linux, NXP i.MX Tags: 4k, armv8, automotive, devkit, nxp

Rockchip PX3 and PX4 Processors Are Designed for Automotive Infotainment & Dashboards

April 5th, 2016 No comments

Rockchip PX2 processor, similar to Rockchip RK3066 but targeting industrial and automotive applications, was launched in 2014. Rockchip now has at least two new member in their PX family with PX3 and PX4 specifically designed for automotive infotainment and car dashboards thanks to dual display support, at least according to one article on Elezine.

Rockchip_PX4_PX3_PX2Rockchip PX3 is definitely confirmed with its own page on Rockchip website, and features a quad core Cortex A9 @ 1.4 GHz with a Mali-400MP4 GPU, and while there’s no info about PX4 yet on the company website, the SoC should come with a quad core Cortex A53 processor @ 1.3 GHz with a Mali-T722 GPU, as well as HDMI 2.0 video output, and H.265 video decoding.

The article also lists 7 key function of Rockchip solutions:

  1. “Quick startup and fast revert track”
  2. Navigation system with free updates
  3. HD video recording (car DVR)
  4. Advanced ADAS algorithm to achieve the trajectory, distance between vehicles, license plate recognition, collision avoidance and other functions
  5. Dual screen support
  6. Mobile Internet control
  7. Support for 1080p H.264 decoding and voice recognition input

I could not find system or demo with dual display system with PX3 (dashboard + infotainment), but did find a video of a double DIN car stereo based on Rockchip PX3 processor and running Android 4.4.

Auto Pumpkin sells several PX3 based stereo for various car models on their website for $250 and up. Cold boot time is rather standard however (25 to 30 seconds). I found about PX3 processor via one IloveRockchip tweet boasting about a “large screen in-vehicle navigation for Dongfeng Kadjar”, but I could not find any details, as maybe the news is only reported in Chinese media.