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Embedded Systems Conference 2017 Schedule – May 3-4

April 5th, 2017 No comments

The Embedded Systems Conference 2017 will take place over two days in Boston, US on May 3-4, and the organizers have published the schedule of the event. Even if you’re not going to attend, you’ll often learn something or find new information by just checking out the talks and abstracts, so I’ve created my own virtual schedule with some of the most interesting sessions.

Wednesday, May 3rd

  • 08:00 – 08:45 – Combining OpenCV and High Level Synthesis to Accelerate your FPGA / SoC EV Application by Adam Taylor, Adiuvo Engineering & Training Ltd

This session will demonstrate how you can combine commonly used Open source frameworks such as OpenCV with High Level Synthesis to generate a embedded vision system using FPGA / SoC. The combination of OpenCV and HLS allows for a much faster algorithm development time and consequently a faster time to market for the end application.

  • 09:00 – 09:45 – Understanding the ARM Processor Roadmap by Bob Boys,   Product Manager, ARM

In 2008, the ARM processor ranged from the 32-bit ARM7 to the Cortex-A9. There were only three Cortex-M processors. Today the roadmap has extended up to the huge 64-bit Cortex-A72, down to the tiny Cortex-M0 and out to include in the winter 2016, the new Trustzone for ARMv8-M.

The ARM roadmap, in order to effectively service many markets, has grown rather complicated. This presentation will explain the ARM roadmap and offer insights into its features. Questions answered include where processors should be used and sometimes where it makes more sense to use a different processor as well as different instruction and core feature sets.

This will start at ARM 7 TDMI and how and why ARM turned into the Cortex family. Each of the three components: Application (Cortex-A), Real-Time (Cortex-R) and Microcontroller (Cortex-M) will be explained in turn.

  • 10:00 – 10:45 – Mixed Signal Analysis: digital, analog and RF by Mike Borsch,  Application Engineer, Rohde & Schwarz

Embedded systems increasingly employ both digital, analog and RF signals. Debugging and analyzing these systems can be challenging in that one needs to measure a number of different signals in one or more domains simultaneously and with tight time synchronization. This session will discuss how a digital oscilloscope can be used to effectively debug these systems, and some of the instrumentation challenges that go along with this.

  • 11:00 – 11:45 – Panel Discussion: The Extinction of the Human Worker? – The Future Role of Collaborative Robots in Smart Manufacturing
  • 12:00 – 12:45 – How Will MedTech Fare in our New Public Policy Environment by Scott Whittaker, President & Chief Executive Officer, Advanced Medical Technology Association (AdvaMed)
  • 13:00 – 13:45 – Embedded Systems Safety & Security: Dangerous Flaws in Safety-Critical Device Design by Michael Barr, Co-founder and CTO, Barr Group

When safety-critical devices come online, it is imperative that the devices are not only safe but also secure. Considering the many security concerns that exist in the IoT landscape, attacks on connected safety-critical devices are to be expected and the results could be deadly. By failing to design security into dangerous devices, too many engineers are placing life and limb at risk. Join us for a look at related industry trends and a discussion of how we can work together to put future embedded systems on a more secure path.

  • 14:00 – 14:45 – Intel EPID: An IoT ID Standard for Device Authentication & Privacy by Jennifer Gilburg, Director IoT Identity, Intel Platform Security Division

Approved as a TCG & ISO direct anonymous attestation method and open sourced by Intel—EPID (Enhanced Privacy ID) is a proven solution that has been shipped in over 2.5 billion processors since 2008. EPID authenticates platform identity through remote attestation using asymmetric cryptography with security operations protected in the processors isolated trusted execution environment. With EPID, a single public key can have multiple private keys (typically millions). Verifiers authenticate the device as an anonymous member of the larger group, which protects the privacy of the user and prevents attack maps that can be created from traditional PKI authentication. Learn how to utilize or embed EPID in a device and discover the wide range of use cases EPID enables for IoT including 0 touch secure onboarding to IoT control platforms.

  • 15:00 – 15:45 – Building A Brain With Raspberry Pi and Zulu Embedded JVM by Simon Ritter, Deputy CTO, Azul Systems

Machine and deep learning are very hot topics in the world of IT at the moment with many projects focusing on analyzing big data to make ‘intelligent’ decisions.

In this session, we’ll use a cluster of Raspberry Pis running Azul’s Zulu embedded JVM to build our very own brain. This will use a variety of programming techniques and open source libraries to emulate a brain in learning and adapting to data that is provided to it to solve problems. Since the Raspberry Pi makes connecting sensors straightforward we’ll include some of these to provide external stimulus to our artificial brain.

We’ll conclude with a demonstration of our brain in action learning and adapting to a variety of input data.

  • 16:00 – 16:45 – Vulnerabilities in IoT: Insecure Design Patterns and Steps to Improving Device Security by M. Carlton, VP of Research, Senrio

This talk will explore vulnerabilities resulting from insecure design patterns in internet-connected embedded devices using real-world examples. In the course of our research, we have observed a pattern of vendors incorporating remote configuration services, neglecting tamper proofing, and rampantly re-using code. We will explore how these design flaws resulted in vulnerabilities in a remote power supply, a web camera, and a router. This talk is intended for a wide audience, as these insecure design patterns exist across industries and market segments. Attendees will get an inside view into how attackers operate and walk away with an understanding of what must be done to improve the security of embedded devices.

Thursday, May 4th

  • 08:00 – 08:45 – Heterogeneous Software Architecture with OpenAMP by Shaun Purvis, Embedded Systems Specialist, Hardent

Single, high-performance embedded processors are often not adequate to meet today’s system-on-chip (SoC) demands for sustained high-performance and efficiency. As a result, chips increasingly feature multiple processor types to deliver flexible compute power, real-time features and energy conservation requirements. These so called heterogeneous multiprocessor devices yield an extremely robust SoC, but also require a more complex software architecture capable of orchestrating multiple dissimilar processors.

This technical session introduces the OpenAMP software framework designed to facilitate asynchronous multiprocessing (AMP) in a vendor agnostic manner. OpenAMP can be leveraged to run different software platforms concurrently, such as Linux and an RTOS, on different processors within the same SoC whether homogeneous (multi-core), or heterogeneous (multi-processor), or a combination of both.

  • 09:00 – 09:45 – How to Build Products Using Open Platform Firmware by Brian Richardson,  Technical Evangelist, Intel Corporation

Open hardware platforms are great reference designs, but they’re often not considered “product ready” due to debug features built into the firmware… but a few firmware changes can turn an open hardware board into a production-quality platform.

This session demonstrates how to optimize firmware for product delivery, using the MinnowBoard Max as a practical example, by disabling debug interfaces and optimizing the platform for an embedded software payload. Examples are also given for enabling signed firmware updates and secure firmware recovery, based on industry standard UEFI firmware.

  • 10:00 – 10:45 – Understanding Modern Flash Memory Systems by Thomas McCormick, Chief Engineer/Technologist, Swissbit

This session presents an in-depth look at the internals of modern flash memory systems. Specific focus is given to technologies that enable current generations of flash memory, both SLC and MLC, using < 30 nm process technologies to provide reliable code and data storage in embedded computer applications.

  • 11:00 – 11:45 – Implementing Secure Software Systems on ARMv8-M Microcontrollers by Chris Shore,  Director, Technical Marketing, ARM

Microcontrollers incorporating ARM TrustZone technology for ARMv8-M are here!. Now, software engineers developing on ARM Cortex-M processors have access to a level of hardware security which has not been available before. These features that a clear separation between secure and non-secure code, secure and non-secure data.

This presentation shows how software developers can write secure code which takes advantage of new hardware features in the architecture, drastically reducing the attack surface. Writing software carefully builds on those hardware features, avoiding bugs and/or holes which could compromise the system.

  • 12:00 – 12:30 – Keynote: State of the Medical Device Industry by Frost & Sullivan
  • 13:00 – 13:45 – Enabling the Next Era of Human Space Exploration by Jason Crusan, Director of the Advanced Exploration Systems Division within the Human Exploration and Operations Mission Directorate, NASA

Humankind is making plans to extend its reach further into the solar system than ever before. As human spaceflight moves beyond low Earth orbit NASA’s Advanced Exploration Systems is developing innovative tools to driving these new efforts and address the challenges that arise. Innovative technologies, simulations and software platforms related to crew and robotic autonomous operations, logistics management, vehicle systems automation, and life support systems management are being developed. This talk will outline the pioneering approaches that AES is using to develop prototype systems, advance key capabilities, and validate operational concepts for future human missions beyond Earth orbit.

  • 14:00 – 14:45 – Common Mistakes by Embedded System Designers: What They Are and How to Fix Them by Craig Hillman, CEO, DfR Solutions

Embedded system design is a multilevel engineering exercise. It requires synergy between software, electrical and mechanical engineers with the goal to create a system that meets customer requirements while remaining within budget and on time.

The propagation of embedded systems has been extremely successful. Many appliances today contain embedded systems. As an example, many fuel pumps contain single board computers whose sole purpose is credit transactions. Some companies doing positive train control (PTC) use ARM/RISC and ATOM based computer modules. And embedded systems are currently dominating the Internet of Things (IoT) space (ex. mobile gateways).

However, all of this success can tend to mask the challenges of designing a successful embedded system. These challenges are expected to increase dramatically with the integration of embedded systems into IoT applications, where environments can be much more severe than standard home / office installations.

This course presents the fundamentals of designing a reliable embedded device and the most common pitfalls encountered by the system designer.

  • 15:00 – 15:45 – Porting to 64-bit on ARM by Chris Shore, Director, Technical Marketing, ARM

The ARMv8-A architecture introduces 64-bit capability to the most widely used embedded architecture in the world today. Products built to this architecture are now mainstream and widely available. While they are capable of running legacy 32-bit software without recompilation, clearly developers will want to make maximum use of the increased and expanded capability offered by these processors.

This presentation examines the steps necessary in porting current 32-bit ARM software to the new 64-bit execution state. I will cover C porting, assembly language porting and implementation of hand-coded SIMD routines.


If you want to attend ESC ’17, you’ll need to register. The EXPO pass is free if you book in advance, and gives you access to the design and manufacturing suppliers booths, but won’t allow you to attend most of the talks (except sponsored ones), while the conference pass gives you access to all sessions including workshops and tutorials, as well as complimentary lunch vouchers.

CONFERENCE PASS EXPO PASS
SUPER EARLY BIRD
(Ends March 31st, 2017)
$949 FREE
STANDARD
(Ends May 2nd, 2017)
$1,149 FREE
REGULAR/ONSITE $1,299 $75

Intel: My 10nm Process is Denser Than Yours

March 30th, 2017 5 comments

Process technology is important as the lower the process node, the more efficient the processor becomes, which leads to either longer battery life for the same tasks on battery powered devices, or allows for higher frequencies extracting more performance. Qualcomm and Samsung recently announced Snapdragon 835 SoC was manufactured using 10nm process technology, but Mark Bohr, an Intel Senior Fellow and director of process architecture and integration at Intel Corporation. wrote a blog post explaining that while in the past process node size and density were progressing in a “linear” fashion, this is not the case anymore, as marketing has changed, and some companies advance node names, even in cases where there’s minimal or no density increase.

The chart above implies that some companies 10nm process is barely better than Intel’s 14 nm process, with their 10nm process capable of integrating about twice as much transistors per square millimeter compare to competitors’ 10nm process.

Mark goes on to say a metrics are needed, and manufacturers should disclose their logic transistor density in units of MTr/mm2 (millions of transistors per square millimeter), using the following formula combining NAND and Scan Flip Flop (SFF) cell areas.

He also explains SRAM cell size should be reported separately since there’s a wide variety of SRAM-to-logic ratios in different chips.

Categories: Hardware Tags: intel, process

isorespin.sh Script Updates Ubuntu ISO Files with Mainline Linux Kernel

March 29th, 2017 12 comments

Devices based on Intel Bay Trail and Cherry Trail processors have been popular due to their integration into low cost system (for an Intel platform), but Intel did not prioritize Linux development for those processors, so while Linux could run, you’d have various problems with HDMI audio, system freezes, and wireless drivers, unless you used a custom kernel. The goods news is that Linux 4.11 will feature fixes for HDMI audio and system freeze, and so you won’t need a custom kernel anymore. Ian Morrison (Linuxium), who has been working on improving Linux for those devices since they were first released, has now released isorespin.sh script to automatically update any Ubuntu ISO image to the latest mainline Linux RC kernel built by Canonical, but not integrated by default in the ISO.

Once you’ve downloaded isorepin.sh and your ISO of choice, e.g. ubuntu-16.04.2-desktop-amd64.iso, you can update the ISO with mainline Linux using the following command:

The script will update the ISO with the latest Linux-4.11-RC4 kernel, but as new Ubuntu mainline Linux kernel versions become available, you’ll be able to update two lines in the script to match the latest version:

If you run this image on Bay Trail or Cherry Trail mini PC, you should get HDMI audio and no problem with the “frequent freezes” bug, but if you also need WiFi and Bluetooth support, you may have to run a few more scripts for Broadcom or Realtek wireless modules, and analog audio (headphone jack) support.

Intel to Launch Optane Memory M.2 Cards for Desktop PCs Next Month for $44 and Up

March 28th, 2017 18 comments

Intel launched their first Optane SSD based on 3D Xpoint technology for the enterprise/datacenter market last week, and now the company has announced 16GB and 32GB consumer grade Optane memory will start selling in April starting at $44.

The cards will follow M.2 card (80mm) form factor, use a dual PCIe NVMe 3.0 interface, and currently only works with Optane compatible motherboards with 7th generation Intel Core processors. Intel promises boot times that are twice as fast, 28% better overall performance, and 65% faster game level loads thanks to vastly improved random I/O performance.

We can see some of the specs for both cards on Intel website. I reproduced some of the performance reliability data in the table below.

32GB Optane Memory 16GB Optane Memory
Sequential Read (up to)
Up to 1350 MB/s Up to 900 MB/s
Sequential Write (up to)
Up to 290 MB/s Up to 145 MB/s
Random Read (8GB & 100% span)
Up to 240000 IOPS Up to 190000 IOPS
Random Write (8GB & 100% span)
Up to 65000 IOPS Up to 35000 IOPS
Latency – Read
9 µs 7 µs
Latency – Write
30 µs 18 µs
Power – Active
3.5 Watts
Power – Idle
1 Watt
Endurance Rating (Lifetime Writes) 182.5 TB
Mean Time Between Failure (MTBF) 1.6
Uncorrectable Bit Error Rate (UBER) < 1 sector per 10^15 bits read

The read sequential performance looks good, but the write performance is lower than one some of cheap mini PCs I’ve reviewed in the last year. For example the 128GB FORESEE SSD inside Voyo V3 mini PC gets respectively 400 MB/s and 200 MB/s sequential read and write speed in actual benchmarks. What make Optane memories stands out are random read and write performance, as well as ultra-low latency, which explains why Intel promotes system boot time and app loading times. For example, Microsoft Outlook will launch up to nearly 6x faster, and the Chrome browser up to 5x faster.

I’m not too familiar with endurance data, and it’s really odd MTBF is expressed without unit, but if we look at an Intel 30GB consumer mSATA SSD for comparison, MTBF is expressed in hours (1.2 millions), so I guess that means the Optane memory MTBF is 1.6 millions hours, and the UBER number is less than 1 sector per 10^16 bits read, so endurance numbers are mixed, and there does not seem to be any clear advantage for the Optane memory in that respect. Power consumption of Optane memory is also much higher than the mSATA SSD I linked to (Idle: 250 mW; active: 300mW).

Intel Optane memory will start selling on April 24th for $44 for the 16GB version, and $77 for the 32GB version. You’ll be able to install the memory in one of the 130+  Intel Optane memory ready motherboards from manufacturers such as Asus, Gigabyte, MSI, ASRock and others, and in Q2 2017, several PC manufacturers will start selling computers equipped with the new 3D Xpoint memory cards. More details may be found on Optane memory product page.

Categories: Hardware, Intel Core Tags: 3d xpoint, intel, ssd

Intel Optane SSD DC P4800X is the First SSD based on 3D Xpoint Technology

March 20th, 2017 1 comment

3D Xpoint – pronounced “3D cross point” – was introduced in 2015 with the promise of delivering a 1000 times boost in performance and durability compared to NAND flash, and a density that 10 times better than DRAM. The next year, expectations were lowered quite a bit, when Intel presented a comparison between a high performance “NAND” SSD and a 3X point SSD prototype showing 7.23 times higher IOPS performance. The company has now launched its first 3D Xpoint product with Optane SSD DC P4800X with 375GB capacity.

Optane SSD DC P4800X specifications:

  • Capacity – 375GB
  • Interface – PCIe 3.0 x4, NVMe
  • Form Factor – Add-in-Card (AIC); Half-height, Half-length, Low-profile
  • Latency (typical) R/W – <10μs
  • Quality of Service (QoS)  99.999%
    • 4kB 5 Random Queue Depth 1, R/W: <60/100 μs
    • 4kB Random Queue Depth 16, R/W: <150/200 μs
  • Throughput
    • IOPS Random 4kB R/W – Up to 550/500k
    • IOPS Random 4kB 70/30 Mixed R/W – Up to 500k
  • Endurance
    • 30 Drive Writes per day (JESD219 workload)
    • 12.3 Petabytes Written (PBW)

Intel did not mention sequential throughput, that’s because Optane SSD are designed for specific datacenter applications where the important performance metrics are random I/Os, latency, QoS, and endurance.  It’s also possible to get the SSD with “Intel Memory Drive Technology” that integrates the drive into the memory subsystem and presents the SSD as DRAM to the operating system and applications.

Intel did not mention the price in the press release, but Anandtech reports the 375 GB model is selling for $1,520, which goes up to $1951 with Memory Drive support, and 750GB and 1.5 GB models are coming in respectively Q2 & H2 2017. All models with come with a 5-year warranty. More information should be available on Intel Optane SSD DC P4800X Series product page.

Categories: Hardware Tags: 3d xpoint, benchmark, intel, ssd

UP Core is a Low Cost & Compact Intel Maker Board Powered by an Atom x5-Z8350 SoC (Crowdfunding)

March 18th, 2017 19 comments

The UP community has already launched Intel Cherry Trail and Apollo Lake boards in the past with UP Board and UP2 (squared) boards, and they are now about to launch a cheaper and smaller board called UP Core powered by Intel Atom x5-Z8350 processor with to 1 to 4GB memory, up to 64GB eMMC flash, HDMI, USB 3.0, … and I/O expansion connectors.

Click to Enlarge

UP Core specifications:

  • SoC – Intel Atom x5-Z8350 “Cherry Trail” quad core processor @ 1.44 GHz / 1.92 GHz (Burst frequency) with Intel HD 400 graphics @ 200 / 500 MHz
  • System Memory –  1, 2 or 4 GB DDR3L-1600 (soldered on board)
  • Storage – 16, 32, or 64 GB eMMC flash, SPI flash ROM
  • Video Output / Display – HDMI 1.4 port, full eDP (embedded DisplayPort) connector
  • Audio I/O – Via HDMI, and I2S
  • Connectivity – 802.11 b/g/n WiFi  @ 2.4 GHz, Bluetooth 4.0 LE (AP614A)
  • USB – 1x USB 3.0 host port, 2x USB 2.0 via header
  • Camera I/F – 1x 2-lane MIPI CSI, 1x 4-lane MIPI CSI
  • Expansion
    • 100-pin docking connector with power signals, GPIOs, UART, SPI, I2C, PWM, SDIO, I2S, HDMI SMBUS, PMC signals, 2x USB HSIC, CSI, and PCIe Gen 2
    • 10-pin connector with 2x USB 2.0, 1x UART
  • Misc – Power & reset buttons, RTC battery header, fan connector, BIOS reflash connector
  • Power Supply – 5V/4A via 5.5/2.1mm power barrel
  • Dimensions – 66 x 56.50 mm
  • Temperature Range – Operating: 0 to 60 °C

The board will support Microsoft Windows 10, Windows 10 IoT Core, Linux including Ubilinux, Ubuntu, and the Yocto Project, as well as Android 6.0 Marshmallow.

Block Diagram – Click to Enlarge

If you look at the bottom right connector of the diagram above, we can see an extension HAT for the 100-pin docking port will be offered, as well as an IO board, both of which should be compatible with Raspberry Pi HATs with 40-pin connectors. But so far, I could not find details about the extension HAT, nor the IO board.

The UP core is coming soon to Kickstarter with price starting at 69 Euros with 1GB RAM, 16GB eMMC flash, and WiFi and Bluetooth. Other part of the documentation show a $89 price for the 1GB/16GB board, so maybe it’s the expected retail price out of the crowdfunding campaign. You’ll find a few more information on UP Core page, but we’ll probably have to wait for the Kickstarter campaign to launch to get the full details, especially with regards to add-on boards, and pricing for various options.

Thanks to Freire for the tip.

Arrow Chameleon96 Board To Feature Intel Altera Cyclone V SE FPGA + ARM SoC in 96Boards Form Factor

March 7th, 2017 No comments

Embedded World 2017 will start in about one week, and take place in March 14 – 16 in Nuremberg, Germany, so we can expect interesting embedded news coming soon. Arrow has written a blog post with plans to announce three 96Boards at the event: Meerkat based on NXP i.MX 7Dual, Chameleon96 based on Intel/Altera Cyclone V FPGA + ARM SoC, and Systart Oxalis 96Boards EE board powered by NXP LS1020A single core ARM Cortex A53 SoC. I’ll start with Chameleon (Chameleon96) today, as it’s the first with FPGA fabric, and I could find some technical details and photos about the board.

Click to Enlarge

Chameleon96 board specifications:

  • SoC – Intel PSG / Altera Cyclone V SE 5CSEBA6U19I7N with a dual core ARM Cortex A9 processor @ up to 800 MHz and FPGA fabric with 110K Logic Elements
  • Chips, Ports and Features connected to FPGA:
    • Integrated USB-Blaster II JTAG cable
    • Configuration sources: SD Card, JTAG
    • HDMI display output
    • WiFi 802.11 a/b/g/n + Bluetooth 4.1 module interface
  • Chips, Ports & Features connected to ARM system (HPS)
    • 512MB DDR3 SDRAM (16 bit data bus)
    • 2x USB 2.0 host ports, 1x micro USB OTG port
    • Micro SD card interface
    • Serial UART
    • User LEDs
    • Warm reset button
  • Expansion Connectors
    • 2x 20-pin Low speed expansion connector with UART, SPI, I2C, I2S, GPIO connectivity
    • 2x 30 High speed expansion connector with USB 2.0 Host, SPI, I2C, GPIO, and MIPI CSI-2 connectivity
  • Debugging – 3-pin UART connector
  • Misc – User LEDs, power button, reset button
  • Power Supply – 12V DC (8~18V supports as per 96Boards CE specifications)
  • Dimensions – 85 x 54 mm

The company will provide a Linux image and source code at launch with the board shipping with a 12V DC power supply, a USB to serial cable, a USB 2.0 AB cable, and a micro SD card pre-loaded with a Linux distribution with a graphical user interface, and source code.

One of the first use of the FPGA will be IoT security with the board including a “quantum-resistant” Ironwood Key Agreement Protocol, and WalnutDSA Digital Signature Algorithm reference design from SecureRF.

Block Diagram for Chameleon96 Board – Click to Enlarge

The board is not yet listed on Arrow Electronics website, but you can get some extra details on Rocketboard’s Chameleon96 Wiki page.

Spreadtrum SC9861G-IA is an Octa-core Intel Airmont LTE SoC for Smartphones

February 28th, 2017 3 comments

Do you member Rockchip & Intel partnership about “SoFia” SoC for smartphones? It did not pan out so well, and but Intel has apparently not given up on the idea of partnering with Chinese companies to design and launch Intel based smartphone application processors, as Speadtrum has just announced SC9861G-IA octa-core Intel Airmont processor @ up to 2.0 GHz with an LTE Cat. 7  modem, and manufactured using Intel’s 14nm process technology.

The Airmont architecture is also found in Intel’s own Cherry Trail and Braswell SoCs designed for respectively tablets and mini PCs, so they must have found some further power efficiencies in order to use it in a smartphone, and used some of technology developed for Intel canceled projects. SC9861G-IA withh support 5-mode full-band LTE (TDD-LTE / FDD-LTE / TD-SCDMA / WCDMA / EGG) Cat 7. as well as Carrier Aggregation and TDD/FDD hybrid networking, allowing for peak data transmission rate of 300 Mbps downlink and 100 Mbps uplink.

Other features of the SoC include support for dual cameras up to 26 megapixels with real-time rear/front camera capture/recording, up to 4K2K H.265 video recording, as well as displays up to 2560×1600 resolution. The SoC is also equipped with an Imagination PowerVR GT7200 GPU, an integrated sensor hub, and Intel Virtualization Technology to support a multi-domain security system architecture and provide security..

Spreadtrum SC9861G-IA is scheduled for mass production in Q2 2017, and targets the mid range and premium smartphones.