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Embedded Linux Conference 2014 Schedule

April 19th, 2014 No comments

The Tenth Embedded Linux Conference (ELC 2014) will take place on April 29 – May 1, 2014 at the San Jose Marriott in San Jose, California. The event will feature 90+ sessions on embedded Linux, Android and IoT with over 450 attendees expected to attend. It will also be co-located with Android Builders Summit and the AllSeen Alliance Hackfest. Even if you can’t attend it’s still interesting to see what will be discussed at the event to get a grasp of on-going developments, learn a few things about different optimization techniques, and so on. So I’ve gone through the sessions’ description, and I’ve designed my own virtual schedule with sessions that could be of interest.

Embedded_Linux_Conference_2014April 29

Linux has taken the embedded world by storm.  Billions (with a ‘B’) of devices have now shipped with a Linux kernel, and it seems unstoppable.  But will the next 10 billion devices ship with Linux or with something else?  How can Linux be specialized for deeply embedded projects, as characterized by the Internet of Things, while still maintaining the network effects of community cooperation and sharing?  Is this possible or even desirable?  The startling truth might be revealed at this keynote. Or, Tim might just rant a bit about device-tree… who knows?

The past year has seen a remarkable growth of interest in super-low-power and super-low-form-factor computing, in the form of ‘wearables’, the ‘Internet of Things’, and the release of exciting new hardware such as Intel’s Quark and Edison SoCs. Taking advantage of this super-small hardware also implies the need for super-small operating systems and applications to match. This talk will describe a super-small-footprint Linux distribution called ‘microYocto”. The main focus will be the kernel and how we achieved what we think is close to the minimal possible kernel footprint, both in terms of static text size and dynamic memory usage. We’ll talk about the tools and methodologies we used and developed to analyze the problem, such as tracing and machine simulation, and will describe the various technologies developed and applied to achieving this minimalistic system.

Many community resources exist about boot time reduction. However, few of them are up to date and share the exact time savings that can be achieved on recent systems. This talk will detail today’s most efficient techniques to reduce boot time. For each of them, figures will be shared, obtained from recent boot time reduction projects and from the preparation of Free Electrons new workshop on this topic. If you attend this talk, you will know which optimization techniques are worth using first, and will save time not exploring techniques that won’t make a significant difference in your project. Don’t tell your boss, and this will leave your more time to contribute to community projects!

In this talk, Chris will describe the internal workings of the Android graphics stack from the Application layer down through the stack to pixels on the screen. It is a fairly complex journey, taking in two different 2D rendering engines, applications calling OpenGL ES directory, passing buffers on to the system compositor, Surface Flinger, and then down to the display controller or frame buffer. All this requires careful synchronisation so that what appears on the screen is smooth, without jitter, and makes efficient use of memory, CPU, GPU and power resources.

Linux-based platforms such as the Beaglebone and Raspberry Pi are inexpensive powerhouses. But, beyond being cool on their own, what else can you do with them? This presentation will step you through the process of building a Wi-Fi enabled, Linux-based robot that you can build without breaking the bank and without special knowledge of robotics and robotic controls.

Since last year, we have been working on supporting the SoCs from Allwinner, a Chinese SoC vendor, in the mainline kernel. These SoCs are cheap, wide-spread, backed by a strong community and, until last year, only supported by an out-of-tree kernel. Through this talk, we would like to share the status of this effort: where we were a year ago, what solutions were in place, where we are currently, and what to expect from the future. We will also focus on the community around these SoCs, the work that is done there, etc.

April 30

GCC is an optimizing compiler, currently most common compiler to build software for Embedded Linux systems like Android, Yocto Project etc. This tutorial will introduce specific optimizations and features of GCC which are less known but could benefit optimizing software especially for embedded use while highlight the effect of common optimizations. While it will focus on squeezing most out of GCC, it will also cover some of “pessimizations” to avoid and will tip the developer to write code thats more conducive (compiler friendly) for general optimizations. They will also get some contrast with other compilers when needed.

Throughout the last two years, a team of engineers at Free Electrons has been involved in mainlining the support for several ARM processors from Marvell, converting the not-so-great vendor-specific BSP into mainline quality code progressively merged upstream. This effort of several hundreds working days, has led to the integration of hundreds of patches in the kernel. Through this talk we would like to share some lessons learned regarding this mainlining effort, which could be useful to other engineers involved in ARM SoC support, as well as detail the steps we have gone through, the mistakes we’ve made and how we solved them, and generally our experience on this project.

This BoFs is intended to bring together anybody that tests the Linux kernel to share best practices and brainstorm new ideas. Topics may range from .config testing, module/built-in drivers, test methods and tools for testing specific driver subsystems, VM/scheduler/interrupt stress testing, and beyond. The discussion is targeted at Linux kernel developers, test engineers, and embedded Linux product teams/consultants with the common task of testing Linux kernel integrity. Attendees should have a firm grasp of building and deploying the kernel as well as kernel/userspace kernel APIs.

Several vendors are getting ready to start enabling the upstream kernel for their upcoming 64-bit ARM platforms, and it opens up a few questions on things that are not quite sorted out yet, especially on the embedded and mobile platforms. This is an open discussion on the issues these maintainers are anticipating, and what we should do about it.

Communication between components is necessary for effective power management in mobile devices. The System Power Management Interface, also known as SPMI, is a standardized bus interface intended to provide power-management related connectivity between components. Josh Cartwright will provide a high-level architectural overview of SPMI and discuss how to leverage the Linux Kernel software interfaces (expected to land in 3.15) to communicate with devices on the bus.

May 1

While Android has been created for mobile devices — phones first and now tablets — it can, nonetheless, be used as the basis of any touch-screen system, whether it be mobile or not. Essentially, Android is a custom-built embedded Linux distribution with a very elaborate and rich set of user-space abstractions, APIs, services and virtual machine. This one-day workshop is aimed at embedded developers wanting to build embedded systems using Android. It will cover Android from the ground up, enabling developers to get a firm hold on the components that make up Android and how they need to be adapted to an embedded system. Specifically, we will start by introducing Android’s overall architecture and then proceed to peel Android’s layer one-by-one.

This half-day workshop is aimed at embedded developers that want to use Android in their embedded designs.

The MIPS processor cores are widely used in embedded platforms, including TVs and set-top-boxes. In most of those platforms dedicated graphics hardware exists but it may be specialized for its use in audio and video signal processing: rendering of web content has to be done in software. We implemented optimizations for the software-based QPainter renderer to improve the performance of Qt —including QtWebKit— in MIPS processors. The target platform was the modern 74kf cores, which include new SIMD instructions suitable for graphics operations (alpha blending, color space conversion and JPEG image decoding), and also for non-graphics operations: string functions were also improved. Our figures estimate that web pages are rendered up to 30% faster using hand-coded assembler fast-paths for those operations.

Software Freedom Conservancy announced last year a renewed effort for cross-project collaborative GPL compliance efforts, including copyright holders from BusyBox, Linux, and Samba. Conservancy uses an internal system of communication and collaboration to take input from stakeholders to discuss and engage in compliance activity to ensure compliance with the GPL throughout the technology industry and particularly in the embedded device market. Compliance with the GPL is the responsibility of copyright holders of the software, and Conservancy helps those copyright holders pursue the work, so those developers can focus on coding. In this talk, the President of Conservancy will discuss how Conservancy handles compliance matters, what matters it focuses on, and how the copyright holders that work with Conservancy engage in a collaborative effort to ensure compliance with the GPL.

Ubuntu Touch is the new Ubuntu-based OS for phones and tablets. Announced at the beginning of 2013, it gives a new UI and design proposal, but also a new way of developing and supporting many different devices, using either the Android HAL or the traditional Linux stack to build the platform. This talk will go over the Ubuntu Touch internals, presenting the technical decisions and also the work that was done to bootstrap this new platform (camera, radio, video decode, GLES and etc) and the future challenges to support a single stack across mobile and the traditional desktop.

These are just a few sessions out of the 90+ sessions available at the Embedded Linux Conference and Android Builder Summit. You can check the full schedule to find out which sessions are most interesting to you.

If you’d like to attend the event, you’ll need to register online.

The attendance fees have significantly gone up compared to last year, at least for hobbyists, but include entrance for both ELC and Android Builder Summit:

  • Professional Registration Fee - US$600 (Was US$500 until March 29, 2014)
  • Hobbyist Fee – US$150
  • Student FeeUS$150

After the events, many videos are usually uploaded by the Linux Foundation, and you should be able to find the list of talks with links to presentation slides oneLinux.org.

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Microchip Unveils chipKIT Wi-Fi Development Board and Motor Control Shield

December 4th, 2013 No comments

Microchip Technology has just announced two new boards by Diligent, part of its Arduino compatible chipKIT ecosystem: chipKIT WF32 board featuring a PIC32 MCU and a Wi-Fi module, and chipKIT Motor Control Shield for servos, steppers, and DC motors.

chipKIT WF32 Development Board

chipKIT W32 Wi-Fi Development Board

chipKIT WF32 Wi-Fi Development Board

Board specifications:

  • MCU – Microchip PIC32MX695F512L micro-controller (80 Mhz 32-bit MIPS, 512K Flash, 128K SRAM)
  • External Storage – Micro SD card connector
  • Wi-Fi – IEEE 802.11 b/g via Microchip MRF24WG0MA WiFi module
  • USB – USB 2.0 OTG controller with A and micro-AB connectors for debugging and programing.
  • 43 available I/O pins with 12 analog inputs
  • Misc – 4x user LEDs
  • PC connection uses a USB A > mini B cable (not included)
  • Power – 7V to 15V input voltage (recommended), 3.3V operating voltage, 30V input voltage (maximum), 0V to 3.3V analog input voltage range

Microchip has also released an embedded cloud software framework to create Internet of Things (IoT) applications with the board. There supposed to be a download link, but even after registration I was unable to download anything. The board can be programmed using the Multi-Platform Integrated Development Environment (MPIDE) based on Arduino IDE, but with PIC32 support, and available for WIndows, Linux, and Mac OS X. Alternatively, you could also use Microchip MPLAB IDE for development, and the board is also said to work with all MPLAB compatible in-system programmer/debuggers, such as the Microchip PICkit 3 or the Digilent chipKIT PGM.

Diligent provides the schematics (PDF and Eagle), PCB layout and gerber files, a reference manual, as well as necessary libraries and an HTTP server example on chipKIT WF32 product page.  The board is available now and sells for $69.

chipKIT Motor Control Shield

chipKit Motor Shield

chipKit Motor Shield

Key features:

  • Usable with the ChipKIT Uno32, uC32, and – I’d assume – WF32 boards.
  • 2 DC motor driver channels, accessible with either a JST 6-pin connector or a terminal block
  • 2 DC motor encoder input signals for each DC motor channel
  • 4 servo motor channels
  • I2C General purpose I/O expander with 4 LEDs 2 push buttons and 2 user settable jumpers
  • 1 4-wire unipolar stepper motor channel
  • Standard chipKIT Shield connectors

The schematics (PDF), EAGLE v6.5 files for manufacturing, and a library containing the functions to access the buttons and LEDs connected to the I2C I/O expander can be downloaded on the shield page. chipKIT Motor Shield is also available now for $29.99.

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Linux.Darlloz Worm Targets Embedded Linux Devices

November 29th, 2013 1 comment

Symantec has recently discovered a new Linux worm, called Linux.Darlloz, that targets Internet-enabled devices running Linux in addition to traditional computers. That means devices such as home routers, set-top boxes and security cameras could be at risk of infection, although no attacks against non-PC devices have been confirmed yet.

The worm exploits an “old” PHP vulnerability, which was patched in May 2012 (PHP 5.4.3, and PHP 5.3.13), and currently only affects Intel (x86) based systems. So you’d need an embedded system powered by an Intel processor, running Linux and PHP to be at risk. Having said that, Symantec also explains code for other architectures such as ARM, PPC, and MIPS, is also present in the worm, and these systems could potentially be at risk too with small modifications.

ARM ELF Binary Code found in Linux Worm

ARM ELF Binary Code found in Linux Worm

Here’s how the worm operates:

Upon execution, the worm generates IP addresses randomly, accesses a specific path on the machine with well-known ID and passwords, and sends HTTP POST requests, which exploit the vulnerability. If the target is unpatched, it downloads the worm from a malicious server and starts searching for its next target. Currently, the worm seems to infect only Intel x86 systems, because the downloaded URL in the exploit code is hard-coded to the ELF binary for Intel architectures.

So it seems the most obvious way to protect the system is to change the default password, and create a strong password. Unfortunately most people don’t seem to do that. I stayed in about 15 places during a recent trip, and most Wi-Fi routers could still be accessed with the usual “admin / admin”.

Contrary to computers, which nowadays automatically install security patches regularly, embedded devices seldom get firmware updates, and security is sometimes and afterthought. So beside making device passwords stronger, the company also recommends to following measures:

  1. Verify all devices connected to the network
  2. Update the software to the latest version
  3. Update the security software when it is made available on their devices
  4. Block incoming HTTP POST requests to -/cgi-bin/php* paths

To add to the complexity, many vendors do not disclose the operating systems running on their products, so it might be difficult for the average user to even know if their system is at risk.

Via Arstechnica

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Categories: Linux Tags: Linux, arm, intel, mips, router, security, x86

Imagination Technologies Announced MIPS P5600, the First “Warrior” Core

November 7th, 2013 1 comment

At the end of June, Imagination Technologies unveiled their MIPS Series5 ‘Warrior’ architecture, featuring 32-bit and 64-bit CPU cores, with features such as hardware and software virtualization, and Extended Virtual Addressing (EVA). The company has recently announced the first member of the family with their MIPS P5600 CPU IP core.

MIPS P5600 IP Core Block Diagram

MIPS P5600 IP Core Block Diagram

The MIPS P5600 core is a 32-bit CPU IP that is said to offer 1.2 to 2x more system performance compared to proAptiv cores, and it supports peak frequencies above 2GHz on TSMC’s 28HPM process node. Performance-wise the core achieves 5 CoreMark/MHz and 3.5 DMIPS/MHz for a single core, which appears to be equivalent to ARM Cortex A15 according to values listed in Wikipedia and EEMBC Coremark results.

MIPS P5600 features and benefits:

  • 32-bit MIPS32 Release 5 Instruction Set Architecture
  • 16-stage, wide issue, out-of-order (OoO) pipeline
    • Quad instruction fetch per cycle
    • Triple bonded dispatch per cycle
    • Instruction peak issue of 4 integer and 2 SIMD operations per cycle
    • Sophisticated branch prediction scheme, plus L0/L1/L2 branch target buffers (BTBs), Return Prediction Stack (RPS), Jump Register Cache (JRC)
    • Instruction bonding – merges two 32-bit integer accesses into one 64-bit access, or two 64-bit floating point accesses into one 128-bit access for up to 2x increase on memory-intensive data movement routines
  • L1 cache size for Instruction and Data of 32KB or 64KB each, 4-way set associative
  • New dual-issue 128-bit SIMD Unit (optional)
    • 32 x 128-bit register set, 128-bit loads/stores to/from SIMD unit
    • Native data types – 8-/16-/32-bit integer and fixed point, 16-/32-/64-bit floating point
    • IEEE-754 2008 compliant
    • Runs at full speed with CPU core
  • Full hardware virtualization
    • Provides root and guest privilege levels for kernel and user space
    • Supports multiple guests, with full virtual CPU per guest = guest OSs run unmodified
    • Separate TLBs, COP0 contexts for root and guests –> full isolation, fast context switching, exception and interrupt handling by root
    • HW table walk support in TLB for optimal performance
    • Complete SoC virtualization support (IOMMU and interrupt handling – see multi-core features)
  • Programmable Memory Management Unit (MMU)
    • Enhanced Virtual Address (EVA) – Programmable kernel and user segment sizese
    • eXtended Physical Address (XPA) – Provides extension to 40-bits of physical address bits (1 TB)
    • 1st level micro TLBs (uTLBs) – 16 entry instruction TLB, 32 entry data TLB
    • 2nd level TLBs – simultaneous access, variable and fixed page sizes
      • 64×2 entry VTLB, 512×2 entry 4-way set associative FTLB
    • Hardware table walk for fast page refills
  • Power Management Features
    • Multi-core cluster power controller (CPC):
      • Register-based, visible to/controllable by operating system
      • Per CPU voltage domain gating; per CPU clock gating
      • Cluster level DVFS capable
    • Core level
      • Course and fine-grained clock gating throughout core
      • Way prediction on data and instruction L1 caches
      • Instruction and register-based sleep modes
  • EJTAG/PDtrace debug blocks and interface

Up to 6 P5600 cores can be bundled together in a single cluster to form a multicore system with some other IP blocks including a coherence manager, 2 I/O Coherence Units (IOCU), … as shown in the diagram below. You can also add video and GPU IP cores to design a multimedia application processor.

MIPS_P5600_Multicore_CPU_ClusterIn case you wonder why they’re supporting 6 cores, and not just 4 or 8 cores like competitors, the following reason was given on Imagination Technologies blog:

A six-core cluster enables our partners to build a 4+2/4+1 solution where you have 4 cores running at maximum frequency for crunching down on demanding tasks and 2/1 cores clocked much lower to handle regular tasks. This enables a better scaling in performance while achieving obvious savings in power and area.

Target markets for P5600 include mobile (High-end tablet / smartphone SoCs),  digital home (High-end connected DTV / STB application processor), and Networking (802.11ac routers, residential gateways, CPE modems, 3G/4G cell infrastructure control plane, Network appliances and microservers).

The first devices featuring this technology should start to become available in H1 2015.

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Categories: Android, Linux, Processors Tags: imagination, mips

$27 TP-LINK TL-MR10U is an Hackable OpenWRT Wi-Fi Router with a Power Bank

September 29th, 2013 3 comments

TP-Link WR703N is a cheap 802.11 b/g/n router (you can now get it for about $20) that can easily be hacked to run openWRT and for example, act as an home automation gateway, printer server and more.  But if you need a battery powered router for your application, TP-Link TL-MR10U,  based on similar hardware as TL-703WR, should be a better match as it comes with a 2600 mAh battery, and costs just about $27 on DealExtreme.

Here are the specifications of the devTPLink_TL-MR10Uice:

  • CPU – Atheros AR9331 CPU @ 400Mhz
  • System Memory – 32MB RAM
  • Storage – 4 MB Flash
  • Connectivity:
    • 10/100 Mbit Ethernet port
    • 802.11 b/g/n 150Mbps
    • 3G support via external USB dongle
  • USB – USB 2.0 port + micro-USB port for power
  • Misc – Serial port access
  • Dimensions – 91mm x 43mm x 25.85mm(L x W x H)

The device comes with a microUSB cable and a user’s manual in English and Chinese.

TP-Link_TL_MR10U_PCB

TL-MR10U Internals (Click to Enlarge)

Instructions to install openWRT, perform hardware mods (including upgrading to 64MB RAM), and more are available on OpenWRT MR10U page. You can also visit TP-Link TL-MR10U page for further details about the product in Chinese.

If you need more battery capacity, another model called TL-MR12U comes with twice as much battery capacity (5200 mAh), but at $42 it does not seem as attractive price-wise.

Arnd who shared this product in G+ mini PC community, also mentioned that it could be used as a SqueezeBox slave when combined with a USB speaker, and after installing squeezeslave-alsa_1.2-r365AA_ar71xx.ipk.

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Categories: Hardware, Linux Tags: Linux, hack, mips, openwrt, router, tplink, wifi

Linux Kernel 3.10 Released

July 2nd, 2013 No comments

Linus Torvalds has announced the release of Linux Kernel 3.10:

So I delayed this by a day, considering whether to do another -rc, but decided that there wasn’t enough upside. Sure, it hasn’t been as quiet as I’d like, and we had this long discussion about an inode list locking scalability issue over the last week or two, but in the end that issue turned out to not be new, and while we may end up back-porting the eventual resolution to 3.10, it wasn’t a reason to delay the release.

Similarly, while I might wish for fewer pull requests during the late rc’s (and particularly the ones that came in Friday evening -inconvenient for a weekend release), at some point delaying things doesn’t really help things, and just makes the pent up demand for the next merge window worse.

In other words, I could really have gone either way, but decided that there wasn’t enough reason to break the normal pattern of “rc7 is the last rc before the release”. So here goes..

The appended changelog is (as usual) just the changes since the last rc. This time mainly from the networking pull (which includes drivers and core networking, as well as bluetooth), the rest were pretty small and scattered. We’ve got some arch updates, some acpi/pm fixes, and a scattering of other random fixes..

In the bigger picture (ie since 3.9) this release has been pretty typical and not particularly prone to problems, despite my waffling about the exact release date. As usual, the bulk patch-wise is all drivers (pretty much exactly two thirds), while the rest is evenly split between arch updates and “misc”. No major new subsystems this
time around, although there are individual new features. As usual, I’m sure H-Online and kernelnewbies will do better writeups of the details..

Linus

Linux 3.9 brought more file systems enhancement for Btrfs, XFS and ext-4, included better LZO compression, improvement for power management, ARM SoC, and got rid off CONFIG_EXPERIMENTAL.

Linux 3.10 brings the following key changes:

  • Timer free multitasking (Nearly tickless operation) - Up to now, Linux used preemptive multitasking where an hardware timer fires up at regular intervals (“ticks”), and can forcefully pause any program and run a OS routine that decides which task should continue running next.

    This multitasking method may pose problems with CPUs of laptops and mobile devices which require inactivity to enter in low power modes. Since preemptive multitasking fires the the timer often (1000 times per second in a typical Linux kernel) even when the system is not doing anything, the CPUs could not save as much power as it was possible. Virtualization added even more problems, since each VM runs its own timer. This Linux release adds support for not firing the timer (tickless) even when tasks are running. It’s not actually fully tickless in this release, as the the timer only fires up one time per second. The full tickless mode is disabled when a CPU runs more than one process, and a CPU must be kept running with full ticks to allow other CPUs to go into tickless mode. You can read ‘(Nearly) full tickless operation in 3.10‘ and the Documentation for details.

  • Bcache, a block layer cache for SSD caching – Bcache allows SSDs to cache other block devices, it does writeback caching (besides just write through caching), and is filesystem agnostic. By default it won’t cache sequential IO, just the random reads and writes. It can be used for desktops, servers, high-end storage arrays, and perhaps even embedded. For more details read the documentation or visit the wiki
  • Btrfs: smaller extents – Btrfs has incorporated a new key type for metadata extent references which uses disk space more efficiently and reduces the size from 51 bytes to 33 bytes per extent reference for each tree block. In practice, this results in a 30-35% decrease in the size of the extent tree, which means less copy-on-write operations, larger parts of the extent tree stored in memory which makes heavy metadata operations go much faster. It can be enabled with mkfs or with btrfstune -x.
  • XFS metadata checksums -  Experimental implementation of metadata CRC32c checksums. These metadata checksums are part of a bigger project that aims to implement what the XFS developers have called “self-describing metadata“ which aims at solving verification scalability (fsck takes too long to verify petabyte scale filesystems with billions of inodes). This feature is experimental and requires using experimental xfsprogs. For more information, you can read the metadata Documentation.
  • SysV IPC scalability improvements -  Linux used to lock much too big ranges, and it used to have a single IPC lock per IPC semaphore array. Most loads never cared, but some did. This release splits out locking and adds per-semaphore locks for greater scalability of the IPC semaphore code. Micro benchmarks show improvements of more than 10x in some cases.
  • rwsem locking scalability improvements -The rwsem (“read-writer semaphore”) locking scheme, used in many places in the Linux kernel, had performance problems because of strict, serialized, FIFO sequential write-ownership of the semaphore. In Linux 3.9, an “opportunistic lock stealing” patch was merged to fix it for the slow path, but in 3.10, opportunity lock stealing has been implemented in the fast path, improving the performance of pgbench with double digits in some cases.
  • mutex locking scalability improvements – The mutex locking scheme, used widely in the Linux kernel, has been improved with some scalability improvements due to the use of less atomic operations and some queuing changes that reduce reduce cacheline contention.
  • TCP optimization: Tail loss probe – This release adds the TCP Tail loss probe algorithm which aims at  reducing tail latency of short transactions.
  • ARM big.LITTLE supportSupport for b.L processing has been added to 3.10. See commit.
  • MIPS KVM support – KVM/MIPS supports MIPS32R2 and beyond. Read the release notes for details. See commit.
  • tracing: tracing snapshots, stack tracing – The tracing framework has got the ability to allow several tracing buffers, which can be used to take snapshots of the main tracing buffer. These tracing snapshots can be triggered manually or with function probes. It’s also possible to cause a stack trace to be traced in the ring buffer when a given function is called.

Further details on Linux 3.10 are available on Kernelnewbies.org.

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Imagination Technologies Unveils MIPS “Warrior” 32 and 64 Bit CPU Cores

June 27th, 2013 4 comments

Last year, MIPS announced Aptiv Cores, but since then, the company has been bought by Imagination Technologies, and they’ve recently announced updates to the family, as well as new MIPS Series5 ‘Warrior’ CPU cores during Imagination Summit in Asia.

MIPS Aptiv Warrior

Before I write about the update to Aptiv cores, let me remind you of the 3 Aptiv families:

  • proAptiv – High performance cores (3.5DMIPS/Mhz) to be used in SoC for smartphone, tablets, …. 1 to 6 cores. Roughly equivalent to ARM Cortex A15.
  • interAptiv – Medium performance core (1.7DMIPS/MHz) for mainstream STB, digital cameras, mid-range smartphones. 1 to 4 cores. Equivalent to ARM Cortex A5
  • microAptiv – Low power MCU and MPU cores

Imagination has added a small-footprint single-core version to the interAptiv family without the extra logic associated with multi-core coherency and L2 cache controller, as well as a floating point version to the microAptiv family for applications such as electric metering and motor control.

Most interestingly, Imagination also announced they will introduce MIPS Series5 ‘Warrior’ cores later this year. They will include 32-bit and 64-bit variants that like the Aptiv cores, will come with high-performance, mid-range and entry-level/microcontroller CPUs. Note that contrary to ARM, 64-bit MIPS core are not exactly new, as the first MIPS64 core became available in 1991, and Imaginations claims tools are already built for 64-Bit MIPS architecture.

The key ‘Warrior’ features include:

  • Hardware-assisted virtualization (VZ)
  • MIPS hardware multi-threading technology
  • Imagination security framework for applications including content protection on mobile devices, secure networking protocols and payment services
  • MIPS SIMD architecture (MSA) built on instructions designed to be easily supported within high-level languages such as C or OpenCL.

That’s about all we know at this time. A few more details about the MIPS Series5 features are explained on Imagination’s blog.

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