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Posts Tagged ‘mips’

Imagination Technologies Unveils MIPS I6400 64-Bit Warrior Core

September 3rd, 2014 No comments

Imagination technologies has just announced their MIPS I6400 64-bit core for applications including embedded, mobile, digital consumer, advanced communications, networking and storage. MIPS I-class I6400 CPU family features a 64-bit architecture, hardware virtualization, multi-threading, multi-core and multi-cluster coherent processing, and MIPS32 code will run on MIPS64.

MIPS I6400 Block Diagram (Click to Enlarge)

MIPS I6400 Block Diagram (Click to Enlarge)

The key features of these MIPS64 cores are listed as follows:

  • Efficient, scalable 64-bit performance – The company claims MIPS I6400 achieves over 50% higher CoreMark performance and 30% higher DMIPS compared to “leading competitors in its class”.
  • Hardware multi-threading – Supports up to four hardware threads per core, and  simultaneous multi-threading (SMT) technology leads to higher utilization and CPU efficiency. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% on benchmarks such as SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase.
  • Hardware virtualization – Includes support for up to 15 secure/non-secure guests.
  • Next-generation security – The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
  • Power management – With PowerGearing for MIPS, the I6400 has the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
  • FPU with single and double precision capabilities.
  • 128-bit SIMD – The I6400 features 128-bit SIMD support, built on MIPS SIMD architecture which adheres to true RISC philosophy, with instructions defined to be easily supported within high-level languages such as C or OpenCL. The SIMD in the I6400 supports a wide variety of integer (8, 16, 32 and 64-bit) and floating point (32, 64-bit) data types suitable for various computationally-intensive use cases.
  • Next-generation multicore coherency – Supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets, and operate at different clock frequencies and voltages. The Coherency Manager fabric implements hardware pre-fetching, wider buses and lower latencies compared to previous generations.
  • Scalable, multi-cluster coherency – I6400 cores are designed to be delivered in diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters.
MIPS_I6400_vs_ARMv8

Expected Performance of MIPS I6400 vs the Competition (ARMv8 or Intel Atom?)

The chart above shows better performance of MIPS I6400 with two threads compared to “competing 64-bit CPU”, which could either be ARM Cortex-53 / Cortex A57, or Intel Atom “Bay Trail” processors, so it’s difficult to get an idea of the actual performance compared to the competition. What’s clear is that multiple threads should improve performance in some benchmarks, and application such as web browsers.

MIPS Release 6 architecture also introduces new instructions that are said to accelerate performance for several workloads commonly found in Android, including JIT compilation, Javascript, web browsing, PIC (Position-Independent Code) for Android.

MIPS I6400 will be optimized for 32-bit and 64-bit operating systems including Android L which will support MIPS64. The company will provides software, tools and applications for the new cores, which will be supported by prpl open source foundation. MIPS64 r6 architecture is already supported in QEMU, and source code available on Prpl foundation’s github account.

MIPS I6400 license is already being used by “leading partners”, with general availability scheduled for December 2014, which probably means MIPS I6400 based SoCs should become available sometimes in H2 2015, or early 2016. You can also read Imagination’s blog post for a few more details.

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MIPS Creator CI20 Development Board Formally Announced, Free to Selected Developers

August 28th, 2014 9 comments

Earlier this month, I discovered MIPS Creator CI20 development board based on Ingenic JZ4780 dual core MIPS processor thanks to one of my reader.  Imagination Technologies has now launched the board, which will run Debian 7 first, soon support Android 4.4 and others Linux distributions, and the company places their MIPS board as a competitor to the popular ARM based boards such as the Raspberry Pi and BeagleBone Black. This is the first board part of Prpl initiative for open source Linux and Android software for the MIPS architecture.

MIPS_CI20_Development_BoardAs a reminder, I’ll list the hardware specifications again:

  • SoC – Ingenic JZ4780 dual core MIPS32 processor @ 1.2 GHz with Imagination PowerVR SGX540 GPU. 32kI + 32kD per core, 512K shared L2.
  • System Memory – 1GB DDR3
  • Storage – 8GB NOR flash, 1x SD card slot, 1x SD card slot via expansion
  • Video Output – HDMI up to 1080p
  • Audio I/O – HDMI, Audio In and Out via 3.5mm jack
  • Video Playback – Up to 1080p60
  • Connectivity – 10/100M Ethernet, Wi-Fi + Bt 4.0 module (IW8103)
  • USB – 1x USB OTG, 1x USB 2.0 Host.
  • Expansions Headers – Access to 23x GPIOs, 2x SPI, 1x I2S, 7x ADC on header, including 5-wire touch and battery monitoring function, 1x UART, Transport Stream I/F.
  • Debugging – UART, and 14-pin MIPS EJTAG header
  • Misc – IR receiver, power LED, and button
  • Power Supply – 5V via 4mm/1.7mm barrel connector
  • Dimensions – 90x95mm

One thing I did not mention the last time are the multimedia capabilities of the Ingenic SoC, as it can handle codec such as MPEG-4, H.264, VP8, MPEG-2, and RV9 thanks to the video hardware, “making it ideal for HTPC enthusiasts” according to Imagination. The Linux source code  (3.0.8 and 3.16 kernel) is currently available on github and Imagination plans to up-streamed support to mainline. Graphics support includes Xorg-compliant OpenGL 2.1 and OpenGL ES 1.1/2.0 drivers, which means Linux distributions available for the board should have 3D GPU acceleration. The complete documentation is available on eLinux.

MIPS_Creator_CI20_vs_Raspberry_Pi_vs_BeagleBone_BlackBased on the comparison table above, MIPS Creator CI20 are significantly higher than Raspberry Pi, and even BeagleBone Black, and the board size is about double, so it’s unlikely it will compete on price with either, unless it’s sponsored. Its specs are more akin to the Cubietruck (except for 2GB RAM, SATA support, GbE…) which sells for $89, so something between $70 to $80 could be expected.

With regards to availability there are good and bad news. The bad news is that you can’t buy it right now, and they haven’t announced the price yet. The good news is that if you are involved in an open source project, you may be able to get it for free by requesting one. Eventually MIPS Creator CI20 should sell via Imagination Technologies e-Store.

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$25 GL.iNet 6416A is an Hackable OpenWRT Router with Easy UART and GPIO Access

August 25th, 2014 5 comments

There are plenty of low cost routers supporting OpenWRT, but GL.iNet 6416A has several advantages compared to devices like TP-Link WR703N. Both are based on Atheros AR9931, but GL.iNet router has more memory and storage (64MB RAM + 16MB Flash vs 32MB RAM + 4MB Flash), two Ethernet ports instead of just one, and 6 GPIOs, the serial pins, and power signals (5V, 3.3V and GND) are all easily accessible via though holes or headers. Gl.iNet 6416A can be purchased for about $25 on DealExtreme or Amazon US, and it used to be listed on eBay, but is now out of stock.

GL.inet_6416AGl/iNET 6416A specifications:

  • Wi-Fi SoC – Atheros AR9331 MIPS processor @ 400 MHz
  • System Memory – 64MB RAM
  • Storage – 16MB Flash
  • Connectivity – 2x 10/100 Mbit Ethernet ports, 802.11 b/g/n Wi-FI up to 150Mbps
  • USB – 1x USB 2.0 port, 1x micro USB port for power
  • Debugging – Serial console via UART header (GND, Tx, Rx)
  • Expansion – 6 GPIOs, 5V, 3.3V, and GND.
  • Misc – Reset button, LED indicator
  • Power – 5V (micro USB)
  • Dimension – 5.8 x 5.8 x 2.2 cm
  • Weight 42 grams.

The device is also said to support USB webcams (MJPG or YUV), and USB mass storage with FAT32, EXFAT, EXT-2/3/4, and NTFS file systems using the stock firmware. There are also Android and iOS apps to manage the router.

GL.iNet_6416A_Board

GL.iNet 6416A Board Description – Source: Stian Eikeland

6416A router, and its little brother, 6408A, with 8 MB flash, are now part of mainline OpenWRT. You can also follow news and access short tutorials for the board on GL.iNet website, and check out the product page.

Thanks to Nanik for the tip.

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Ineda Systems Dhanush WPU is a MIPS based SoC Specifically Designed for Wearables

June 5th, 2014 No comments

What’s a WPU? It stands for Wearable Processor Unit, and as you may guess it’s a processor specifically designed to be used in wearables such as smartwatches or fitness trackers.  Currently many wearables are based on application processors that are used in smartphones (e.g. Galaxy Gear), and lower-end versions are based on standard low power MCUs (e.g. Pebble), but none of them are actually based on SoC specifically designed for wearables, and analysts are asserting that new types of SoC are definitely needed if companies are to provide wearables with the battery life and features consumers want. Ineda Systems Dhanush WPU is not the first Wearable SoC announced, as for instance AllWinner mentioned their WX quad core SoC for Wearables should become available in Q4 2014 in their roadmap, and Mediatek vaguely unveiled their Aster SoC at CES 2014, but it’s the first that I know of where we’ve got most of the details announced.

Dhanush WPU Block Diagram

Dhanush “Advanced” WPU Block Diagram

Now that block diagram looks interesting… In order to achieve maximum battery life, Ineda has adopted a sort of “big.LITTLE processing” concept to wearables which they call Hierarchical Computing Architecture (HCA) with up to 3 cores offering three levels of performance and power consumption: MIPS microAptiv (always on for sensors, ultra-low power), MIPS microAptive (low power), and MIPS interAptive application processor.

Dhanush SoCs actually comes in four flavor with only one core, 2-level HCA or 3-level HCA:

HCA Power / Features, and Speech Processing Example

HCA Power / Features, and Speech Processing Example

  • Dhanush Nano
    • microAptiv MCU
    • Memory – On-chip SRAM
    • For werable devices that require MCU class of compute and memory footprint such as smartbands
  • Dhanush Micro (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM
    • Typical application would be a Linux based or RTOS based smartwatch.
  • Dhanush Optima (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM + LPDDR2
    • For Linux based smartwatches requiring more features
  • Dhanush Advanced (3-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Dual-core, multi-threaded interAptiv CPU
    • Multimedia – PowerVR GPU and VPU for video encode/decode
    • Memory – On-chip SRAM + LPDDR2
    • For more advanced, high-end wearables that require high resolution rendering, handle complex image/video processing via GPU compute and also support low power video recording and playback. Typical applications would be a Android smartwatches or smart glasses.

Ineda Systems can provide two SHASTRA development kit:

  • SHASTRA-A for Dhanush Advanced (INCDHAD1) which can also be used to evaluate Dhanush Optima
  • SHASTRA-M for Dhanush Micro (INCDHMC1) which can also be used to evaluate Dhanush Nano
SHASTRA-A_Development_Kit

SHASTRA-A Development Board

The boards come with a software development kit (SDK) including a unified development environment (OS, Drivers, Services, APIs, Sample Applications), integrated resource & power management, a GUI framework, user guides, tools & build utilities and power profiling tools. There are two variants of SHASTRA SDK, one for evaluation, and one for product development.

Dhanush Advanced (INCDHAD1) and Micro (INCDHMC1) are now sampling for early customers. Production status of Nano and Optima versions are not been disclosed. I’d guess that means actual products may retail by the end of the year at the earliest. You can find more information on Ineda Systems’ Dhanush WPU page, as well as Imagination Technologies Blog.

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Prpl Non-Profit Organization to Work on Linux, Android, and OpenWRT for MIPS based Processors

May 28th, 2014 5 comments

prplIn what looks like an answer, albeit fairly late, to Linaro, the non-profit organization working on open source software for ARM based SoCs, a consortium of companies composed of Imagination Technologies, Broadcom, Cavium, Lantiq, Qualcomm, Ingenic, and a few others, has funded Prpl (pronounced Purple), “an open-source, community-driven, collaborative, non-profit foundation targeting and supporting the MIPS architecture—and open to others—with a focus on enabling next-generation datacenter-to-device portable software and virtualized architectures”.

The Prpl foundation will focus on three key objectives:

  • Portability – To create ISA agnostic software for rapid deployment across multiple architecture
  • Virtualization & security – To enable multi-tenant, secure, software, environments in datacenter, networking & storage, home, mobile and embedded
  • Heterogeneous Computing – To leverage compute resources enabling next generation big data analytics and mining

Initially there will PEG (Prpl Engineering Group) to take of the following projects for 4 market segments (datacenter, network & storage, connected consumers, and Embedded & IoT):

  • Linux -  Optimizations for enterprise, home and embedded Linux.
  • Android – Getting started with Android, and Android source code
  • Developer Tools – Used in conjunction with Android and Linux OS
  • Virtualization & Secure Supervisor – Secure multi-container frameworks
  • OpenWRT – Enabling carrier-grade features to complement OpenWRT
Arduino Yun

Arduino Yun

It also appears some low cost MIPS32 & MIPS64 development board and reference designs will be supported such as Newton wearable platform, Microchip chipKit WF32 board, and Arduino Yun.

Companies can join Prpl as Board Members or Contributors Members, and individuals can join the foundation for free to engage with the community and access source code and tools.

Since the the Prpl foundation has just been launched, there aren’t any tools or software available right now, but if you are interested in MIPS development, and possibly other architecture which may be part of Prpl later on, you can get more information and/or join the foundation on Prpl Foundation Website.

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Embedded Linux Conference 2014 Schedule

April 19th, 2014 1 comment

The Tenth Embedded Linux Conference (ELC 2014) will take place on April 29 – May 1, 2014 at the San Jose Marriott in San Jose, California. The event will feature 90+ sessions on embedded Linux, Android and IoT with over 450 attendees expected to attend. It will also be co-located with Android Builders Summit and the AllSeen Alliance Hackfest. Even if you can’t attend it’s still interesting to see what will be discussed at the event to get a grasp of on-going developments, learn a few things about different optimization techniques, and so on. So I’ve gone through the sessions’ description, and I’ve designed my own virtual schedule with sessions that could be of interest.

Embedded_Linux_Conference_2014April 29

Linux has taken the embedded world by storm.  Billions (with a ‘B’) of devices have now shipped with a Linux kernel, and it seems unstoppable.  But will the next 10 billion devices ship with Linux or with something else?  How can Linux be specialized for deeply embedded projects, as characterized by the Internet of Things, while still maintaining the network effects of community cooperation and sharing?  Is this possible or even desirable?  The startling truth might be revealed at this keynote. Or, Tim might just rant a bit about device-tree… who knows?

The past year has seen a remarkable growth of interest in super-low-power and super-low-form-factor computing, in the form of ‘wearables’, the ‘Internet of Things’, and the release of exciting new hardware such as Intel’s Quark and Edison SoCs. Taking advantage of this super-small hardware also implies the need for super-small operating systems and applications to match. This talk will describe a super-small-footprint Linux distribution called ‘microYocto”. The main focus will be the kernel and how we achieved what we think is close to the minimal possible kernel footprint, both in terms of static text size and dynamic memory usage. We’ll talk about the tools and methodologies we used and developed to analyze the problem, such as tracing and machine simulation, and will describe the various technologies developed and applied to achieving this minimalistic system.

Many community resources exist about boot time reduction. However, few of them are up to date and share the exact time savings that can be achieved on recent systems. This talk will detail today’s most efficient techniques to reduce boot time. For each of them, figures will be shared, obtained from recent boot time reduction projects and from the preparation of Free Electrons new workshop on this topic. If you attend this talk, you will know which optimization techniques are worth using first, and will save time not exploring techniques that won’t make a significant difference in your project. Don’t tell your boss, and this will leave your more time to contribute to community projects!

In this talk, Chris will describe the internal workings of the Android graphics stack from the Application layer down through the stack to pixels on the screen. It is a fairly complex journey, taking in two different 2D rendering engines, applications calling OpenGL ES directory, passing buffers on to the system compositor, Surface Flinger, and then down to the display controller or frame buffer. All this requires careful synchronisation so that what appears on the screen is smooth, without jitter, and makes efficient use of memory, CPU, GPU and power resources.

Linux-based platforms such as the Beaglebone and Raspberry Pi are inexpensive powerhouses. But, beyond being cool on their own, what else can you do with them? This presentation will step you through the process of building a Wi-Fi enabled, Linux-based robot that you can build without breaking the bank and without special knowledge of robotics and robotic controls.

Since last year, we have been working on supporting the SoCs from Allwinner, a Chinese SoC vendor, in the mainline kernel. These SoCs are cheap, wide-spread, backed by a strong community and, until last year, only supported by an out-of-tree kernel. Through this talk, we would like to share the status of this effort: where we were a year ago, what solutions were in place, where we are currently, and what to expect from the future. We will also focus on the community around these SoCs, the work that is done there, etc.

April 30

GCC is an optimizing compiler, currently most common compiler to build software for Embedded Linux systems like Android, Yocto Project etc. This tutorial will introduce specific optimizations and features of GCC which are less known but could benefit optimizing software especially for embedded use while highlight the effect of common optimizations. While it will focus on squeezing most out of GCC, it will also cover some of “pessimizations” to avoid and will tip the developer to write code thats more conducive (compiler friendly) for general optimizations. They will also get some contrast with other compilers when needed.

Throughout the last two years, a team of engineers at Free Electrons has been involved in mainlining the support for several ARM processors from Marvell, converting the not-so-great vendor-specific BSP into mainline quality code progressively merged upstream. This effort of several hundreds working days, has led to the integration of hundreds of patches in the kernel. Through this talk we would like to share some lessons learned regarding this mainlining effort, which could be useful to other engineers involved in ARM SoC support, as well as detail the steps we have gone through, the mistakes we’ve made and how we solved them, and generally our experience on this project.

This BoFs is intended to bring together anybody that tests the Linux kernel to share best practices and brainstorm new ideas. Topics may range from .config testing, module/built-in drivers, test methods and tools for testing specific driver subsystems, VM/scheduler/interrupt stress testing, and beyond. The discussion is targeted at Linux kernel developers, test engineers, and embedded Linux product teams/consultants with the common task of testing Linux kernel integrity. Attendees should have a firm grasp of building and deploying the kernel as well as kernel/userspace kernel APIs.

Several vendors are getting ready to start enabling the upstream kernel for their upcoming 64-bit ARM platforms, and it opens up a few questions on things that are not quite sorted out yet, especially on the embedded and mobile platforms. This is an open discussion on the issues these maintainers are anticipating, and what we should do about it.

Communication between components is necessary for effective power management in mobile devices. The System Power Management Interface, also known as SPMI, is a standardized bus interface intended to provide power-management related connectivity between components. Josh Cartwright will provide a high-level architectural overview of SPMI and discuss how to leverage the Linux Kernel software interfaces (expected to land in 3.15) to communicate with devices on the bus.

May 1

While Android has been created for mobile devices — phones first and now tablets — it can, nonetheless, be used as the basis of any touch-screen system, whether it be mobile or not. Essentially, Android is a custom-built embedded Linux distribution with a very elaborate and rich set of user-space abstractions, APIs, services and virtual machine. This one-day workshop is aimed at embedded developers wanting to build embedded systems using Android. It will cover Android from the ground up, enabling developers to get a firm hold on the components that make up Android and how they need to be adapted to an embedded system. Specifically, we will start by introducing Android’s overall architecture and then proceed to peel Android’s layer one-by-one.

This half-day workshop is aimed at embedded developers that want to use Android in their embedded designs.

The MIPS processor cores are widely used in embedded platforms, including TVs and set-top-boxes. In most of those platforms dedicated graphics hardware exists but it may be specialized for its use in audio and video signal processing: rendering of web content has to be done in software. We implemented optimizations for the software-based QPainter renderer to improve the performance of Qt —including QtWebKit— in MIPS processors. The target platform was the modern 74kf cores, which include new SIMD instructions suitable for graphics operations (alpha blending, color space conversion and JPEG image decoding), and also for non-graphics operations: string functions were also improved. Our figures estimate that web pages are rendered up to 30% faster using hand-coded assembler fast-paths for those operations.

Software Freedom Conservancy announced last year a renewed effort for cross-project collaborative GPL compliance efforts, including copyright holders from BusyBox, Linux, and Samba. Conservancy uses an internal system of communication and collaboration to take input from stakeholders to discuss and engage in compliance activity to ensure compliance with the GPL throughout the technology industry and particularly in the embedded device market. Compliance with the GPL is the responsibility of copyright holders of the software, and Conservancy helps those copyright holders pursue the work, so those developers can focus on coding. In this talk, the President of Conservancy will discuss how Conservancy handles compliance matters, what matters it focuses on, and how the copyright holders that work with Conservancy engage in a collaborative effort to ensure compliance with the GPL.

Ubuntu Touch is the new Ubuntu-based OS for phones and tablets. Announced at the beginning of 2013, it gives a new UI and design proposal, but also a new way of developing and supporting many different devices, using either the Android HAL or the traditional Linux stack to build the platform. This talk will go over the Ubuntu Touch internals, presenting the technical decisions and also the work that was done to bootstrap this new platform (camera, radio, video decode, GLES and etc) and the future challenges to support a single stack across mobile and the traditional desktop.

These are just a few sessions out of the 90+ sessions available at the Embedded Linux Conference and Android Builder Summit. You can check the full schedule to find out which sessions are most interesting to you.

If you’d like to attend the event, you’ll need to register online.

The attendance fees have significantly gone up compared to last year, at least for hobbyists, but include entrance for both ELC and Android Builder Summit:

  • Professional Registration Fee - US$600 (Was US$500 until March 29, 2014)
  • Hobbyist Fee – US$150
  • Student FeeUS$150

After the events, many videos are usually uploaded by the Linux Foundation, and you should be able to find the list of talks with links to presentation slides oneLinux.org.

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Microchip Unveils chipKIT Wi-Fi Development Board and Motor Control Shield

December 4th, 2013 No comments

Microchip Technology has just announced two new boards by Diligent, part of its Arduino compatible chipKIT ecosystem: chipKIT WF32 board featuring a PIC32 MCU and a Wi-Fi module, and chipKIT Motor Control Shield for servos, steppers, and DC motors.

chipKIT WF32 Development Board

chipKIT W32 Wi-Fi Development Board

chipKIT WF32 Wi-Fi Development Board

Board specifications:

  • MCU – Microchip PIC32MX695F512L micro-controller (80 Mhz 32-bit MIPS, 512K Flash, 128K SRAM)
  • External Storage – Micro SD card connector
  • Wi-Fi – IEEE 802.11 b/g via Microchip MRF24WG0MA WiFi module
  • USB – USB 2.0 OTG controller with A and micro-AB connectors for debugging and programing.
  • 43 available I/O pins with 12 analog inputs
  • Misc – 4x user LEDs
  • PC connection uses a USB A > mini B cable (not included)
  • Power – 7V to 15V input voltage (recommended), 3.3V operating voltage, 30V input voltage (maximum), 0V to 3.3V analog input voltage range

Microchip has also released an embedded cloud software framework to create Internet of Things (IoT) applications with the board. There supposed to be a download link, but even after registration I was unable to download anything. The board can be programmed using the Multi-Platform Integrated Development Environment (MPIDE) based on Arduino IDE, but with PIC32 support, and available for WIndows, Linux, and Mac OS X. Alternatively, you could also use Microchip MPLAB IDE for development, and the board is also said to work with all MPLAB compatible in-system programmer/debuggers, such as the Microchip PICkit 3 or the Digilent chipKIT PGM.

Diligent provides the schematics (PDF and Eagle), PCB layout and gerber files, a reference manual, as well as necessary libraries and an HTTP server example on chipKIT WF32 product page.  The board is available now and sells for $69.

chipKIT Motor Control Shield

chipKit Motor Shield

chipKit Motor Shield

Key features:

  • Usable with the ChipKIT Uno32, uC32, and – I’d assume – WF32 boards.
  • 2 DC motor driver channels, accessible with either a JST 6-pin connector or a terminal block
  • 2 DC motor encoder input signals for each DC motor channel
  • 4 servo motor channels
  • I2C General purpose I/O expander with 4 LEDs 2 push buttons and 2 user settable jumpers
  • 1 4-wire unipolar stepper motor channel
  • Standard chipKIT Shield connectors

The schematics (PDF), EAGLE v6.5 files for manufacturing, and a library containing the functions to access the buttons and LEDs connected to the I2C I/O expander can be downloaded on the shield page. chipKIT Motor Shield is also available now for $29.99.

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