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Posts Tagged ‘mips’

PowerVR SDK v3.4 Supports WebGL, 64-Bit Android 5.0 Lollipop, and MIPS Linux

October 21st, 2014 2 comments

Imagination Technolgies has just released PowerVR SDK v3.4  including the latest compilers for PowerVR Series6 and Series6XT GPUs to PVRShaderEditor, several performance optimization, a new WebGL SDK, 64-bit support for Android 5.0 Lollipop, and Linux support for MIPS based processors.

PowerVR_SDKThe company has revamped the user interfaces of their tools, and made the following key changes:

  • PVRTrace, a tool to capture and analyze OpenGL ES and EGL API calls, now supports OpenGL ES 3.1, compressed trace files, and they’ve reduce the software memory usage
  • PVRTune, a performance analysis tool, now features new counters, and  “significant” performance optimizations.
  • PVRShaderEditor, a light-weight shader editing too, adds the latest compilers for PowerVR Series6 (FP32 and FP16) and Series6XT GPUs, as well as GLSL disassembler output.
  • PVRTexTool, a utility for compressing textures, adds plugin support for Autodesk 3DSMax and Maya (2015 versions), and improves ETC decompression by up to 20% faster per surface.

Imagination also claims to have improved documentation with a new SDK Browser, part of the SDK,  with installation instructions, examples, source code, documents, etc… More details are available on the release notes page.

PowerVR SDK is available for Windows, Mac OS X & Linux (32-/64-bit).

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Linux 3.17 Released

October 9th, 2014 5 comments

Linus Torvalds announced the release of Linux Kernel 3.17 on Sunday:

So the past week was fairly calm, and so I have no qualms about releasing 3.17 on the normal schedule (as opposed to the optimistic “maybe I can release it one week early” schedule that was not to be).

However, I now have travel coming up – something I hoped to avoid when I was hoping for releasing early. Which means that while 3.17 is out, I’m not going to be merging stuff very actively next week, and the week after that is LinuxCon EU…

What that means is that depending on how you want to see it, the 3.18 merge window will either be three weeks, or alternatively just have a rather slow start. I don’t mind getting pull requests starting now (in fact, I have a couple already pending in my inbox), but I likely won’t start processing them for a week.

Anyway, back to 3.17. Nothing major happened during the last week, as you can see from the appended shortlog. Mostly drivers (i915, nouveau, ethernet, scsi, sound) and some networking fixes. With some misc noise all over.

Go out and test,

Linus

Kernel 3.16 added Nouveau drivers for GK20A GPU (Tegra K1), ARM64/EFI boot, improved support for Xen, KVM, EFI, NFS, as well as various changed to networking, and more…  Some noticeable changes for Linux 3.17:

  • Gamepads – Added Microsoft Xbox One controller support, improvements to Sony SIXAXIS support
  • Toshiba “Active Protection Sensor” support which stops your harddrive from spinning when the accelerator detects your laptop is in free fall…
  • “Cross-thread filter setting” for secure computing facility:
        int seccomp(unsigned int operation, unsigned int flag, const char *args);
    

    See manpage for details.

  • Enhanced AMD Radeon R9 290 support
  • Miscellaneous Nouveau driver improvements, including Kepler GPU fixes

New features and improvements specific to the ARM architecture include:

  • AllWinner
    • A10/A20 – IR driver
    • A31 – PIO/R_PIO external interrupts, DMAengine, GMAC
    • A23: Timers, UARTs, initial bringup, Basic clocks,  PIO/R_PIO drivers
    • New boards: ba10-tvbox; Merrii A31 Hummingbird; pcDuino V3
  • Rockchip
    • Enabled RK3288 SoC support
    • Added RK3xxx I2S controller, RK3288 clock controller, RK3066 and RK3188 clock driver.
    • Added RK3288 evaluation boards
  • Added basic support for Mediatek MT6589 SoCs
  • NEON implementation of crypto algorithms (SHA1; SHA512).
  • Marvell Kirkwood now fully “device tree-ified”, mach-kirkwood directory deleted
  • Added APM X-Gene SoC ethernet driver support.
  • Various changes for Broadcom BCM7xxx STB SoCs, Fresscale i.MX, Samsung Exynos & S5PV210, Nvidia Tegra, Renesas SH and TI AM43xx SoCs.
  • ARM64 / ARMv8 – Added 48-bit adress space, CONFIG_CC_STACKPROTECTOR (GCC’s -fstack-protector), audit support, and context tracking

I’ve also been asked about MIPS changes last time, so here it is:

  • Add Loongson-3B support
  • Add NUMA support for Loongson-3
  • BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)
  • BCM47XX: add Microsoft MN-700 and Asus WL500G
  • Support CPU topology files in sysfs
  • kernel: cpu-probe: Add support for the HardWare Table Walker
  • perf: Add hardware events for P5600

Further details on Linux 3.17 changes will soon be available on Kernelnewbies.org. For more details about ARM changes, remember to also check ARM architecture and drivers sections.

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Imagination Technologies Unveils MIPS I6400 64-Bit Warrior Core

September 3rd, 2014 1 comment

Imagination technologies has just announced their MIPS I6400 64-bit core for applications including embedded, mobile, digital consumer, advanced communications, networking and storage. MIPS I-class I6400 CPU family features a 64-bit architecture, hardware virtualization, multi-threading, multi-core and multi-cluster coherent processing, and MIPS32 code will run on MIPS64.

MIPS I6400 Block Diagram (Click to Enlarge)

MIPS I6400 Block Diagram (Click to Enlarge)

The key features of these MIPS64 cores are listed as follows:

  • Efficient, scalable 64-bit performance – The company claims MIPS I6400 achieves over 50% higher CoreMark performance and 30% higher DMIPS compared to “leading competitors in its class”.
  • Hardware multi-threading – Supports up to four hardware threads per core, and  simultaneous multi-threading (SMT) technology leads to higher utilization and CPU efficiency. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% on benchmarks such as SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase.
  • Hardware virtualization – Includes support for up to 15 secure/non-secure guests.
  • Next-generation security – The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
  • Power management – With PowerGearing for MIPS, the I6400 has the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
  • FPU with single and double precision capabilities.
  • 128-bit SIMD – The I6400 features 128-bit SIMD support, built on MIPS SIMD architecture which adheres to true RISC philosophy, with instructions defined to be easily supported within high-level languages such as C or OpenCL. The SIMD in the I6400 supports a wide variety of integer (8, 16, 32 and 64-bit) and floating point (32, 64-bit) data types suitable for various computationally-intensive use cases.
  • Next-generation multicore coherency – Supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets, and operate at different clock frequencies and voltages. The Coherency Manager fabric implements hardware pre-fetching, wider buses and lower latencies compared to previous generations.
  • Scalable, multi-cluster coherency – I6400 cores are designed to be delivered in diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters.
MIPS_I6400_vs_ARMv8

Expected Performance of MIPS I6400 vs the Competition (ARMv8 or Intel Atom?)

The chart above shows better performance of MIPS I6400 with two threads compared to “competing 64-bit CPU”, which could either be ARM Cortex-53 / Cortex A57, or Intel Atom “Bay Trail” processors, so it’s difficult to get an idea of the actual performance compared to the competition. What’s clear is that multiple threads should improve performance in some benchmarks, and application such as web browsers.

MIPS Release 6 architecture also introduces new instructions that are said to accelerate performance for several workloads commonly found in Android, including JIT compilation, Javascript, web browsing, PIC (Position-Independent Code) for Android.

MIPS I6400 will be optimized for 32-bit and 64-bit operating systems including Android L which will support MIPS64. The company will provides software, tools and applications for the new cores, which will be supported by prpl open source foundation. MIPS64 r6 architecture is already supported in QEMU, and source code available on Prpl foundation’s github account.

MIPS I6400 license is already being used by “leading partners”, with general availability scheduled for December 2014, which probably means MIPS I6400 based SoCs should become available sometimes in H2 2015, or early 2016. You can also read Imagination’s blog post for a few more details.

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MIPS Creator CI20 Development Board Formally Announced, Free to Selected Developers

August 28th, 2014 9 comments

Earlier this month, I discovered MIPS Creator CI20 development board based on Ingenic JZ4780 dual core MIPS processor thanks to one of my reader.  Imagination Technologies has now launched the board, which will run Debian 7 first, soon support Android 4.4 and others Linux distributions, and the company places their MIPS board as a competitor to the popular ARM based boards such as the Raspberry Pi and BeagleBone Black. This is the first board part of Prpl initiative for open source Linux and Android software for the MIPS architecture.

MIPS_CI20_Development_BoardAs a reminder, I’ll list the hardware specifications again:

  • SoC – Ingenic JZ4780 dual core MIPS32 processor @ 1.2 GHz with Imagination PowerVR SGX540 GPU. 32kI + 32kD per core, 512K shared L2.
  • System Memory – 1GB DDR3
  • Storage – 8GB NOR flash, 1x SD card slot, 1x SD card slot via expansion
  • Video Output – HDMI up to 1080p
  • Audio I/O – HDMI, Audio In and Out via 3.5mm jack
  • Video Playback – Up to 1080p60
  • Connectivity – 10/100M Ethernet, Wi-Fi + Bt 4.0 module (IW8103)
  • USB – 1x USB OTG, 1x USB 2.0 Host.
  • Expansions Headers – Access to 23x GPIOs, 2x SPI, 1x I2S, 7x ADC on header, including 5-wire touch and battery monitoring function, 1x UART, Transport Stream I/F.
  • Debugging – UART, and 14-pin MIPS EJTAG header
  • Misc – IR receiver, power LED, and button
  • Power Supply – 5V via 4mm/1.7mm barrel connector
  • Dimensions – 90x95mm

One thing I did not mention the last time are the multimedia capabilities of the Ingenic SoC, as it can handle codec such as MPEG-4, H.264, VP8, MPEG-2, and RV9 thanks to the video hardware, “making it ideal for HTPC enthusiasts” according to Imagination. The Linux source code  (3.0.8 and 3.16 kernel) is currently available on github and Imagination plans to up-streamed support to mainline. Graphics support includes Xorg-compliant OpenGL 2.1 and OpenGL ES 1.1/2.0 drivers, which means Linux distributions available for the board should have 3D GPU acceleration. The complete documentation is available on eLinux.

MIPS_Creator_CI20_vs_Raspberry_Pi_vs_BeagleBone_BlackBased on the comparison table above, MIPS Creator CI20 are significantly higher than Raspberry Pi, and even BeagleBone Black, and the board size is about double, so it’s unlikely it will compete on price with either, unless it’s sponsored. Its specs are more akin to the Cubietruck (except for 2GB RAM, SATA support, GbE…) which sells for $89, so something between $70 to $80 could be expected.

With regards to availability there are good and bad news. The bad news is that you can’t buy it right now, and they haven’t announced the price yet. The good news is that if you are involved in an open source project, you may be able to get it for free by requesting one. Eventually MIPS Creator CI20 should sell via Imagination Technologies e-Store.

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$25 GL.iNet 6416A is an Hackable OpenWRT Router with Easy UART and GPIO Access

August 25th, 2014 6 comments

There are plenty of low cost routers supporting OpenWRT, but GL.iNet 6416A has several advantages compared to devices like TP-Link WR703N. Both are based on Atheros AR9931, but GL.iNet router has more memory and storage (64MB RAM + 16MB Flash vs 32MB RAM + 4MB Flash), two Ethernet ports instead of just one, and 6 GPIOs, the serial pins, and power signals (5V, 3.3V and GND) are all easily accessible via though holes or headers. Gl.iNet 6416A can be purchased for about $25 on DealExtreme or Amazon US, and it used to be listed on eBay, but is now out of stock.

GL.inet_6416AGl/iNET 6416A specifications:

  • Wi-Fi SoC – Atheros AR9331 MIPS processor @ 400 MHz
  • System Memory – 64MB RAM
  • Storage – 16MB Flash
  • Connectivity – 2x 10/100 Mbit Ethernet ports, 802.11 b/g/n Wi-FI up to 150Mbps
  • USB – 1x USB 2.0 port, 1x micro USB port for power
  • Debugging – Serial console via UART header (GND, Tx, Rx)
  • Expansion – 6 GPIOs, 5V, 3.3V, and GND.
  • Misc – Reset button, LED indicator
  • Power – 5V (micro USB)
  • Dimension – 5.8 x 5.8 x 2.2 cm
  • Weight 42 grams.

The device is also said to support USB webcams (MJPG or YUV), and USB mass storage with FAT32, EXFAT, EXT-2/3/4, and NTFS file systems using the stock firmware. There are also Android and iOS apps to manage the router.

GL.iNet_6416A_Board

GL.iNet 6416A Board Description – Source: Stian Eikeland

6416A router, and its little brother, 6408A, with 8 MB flash, are now part of mainline OpenWRT. You can also follow news and access short tutorials for the board on GL.iNet website, and check out the product page.

Thanks to Nanik for the tip.

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Ineda Systems Dhanush WPU is a MIPS based SoC Specifically Designed for Wearables

June 5th, 2014 No comments

What’s a WPU? It stands for Wearable Processor Unit, and as you may guess it’s a processor specifically designed to be used in wearables such as smartwatches or fitness trackers.  Currently many wearables are based on application processors that are used in smartphones (e.g. Galaxy Gear), and lower-end versions are based on standard low power MCUs (e.g. Pebble), but none of them are actually based on SoC specifically designed for wearables, and analysts are asserting that new types of SoC are definitely needed if companies are to provide wearables with the battery life and features consumers want. Ineda Systems Dhanush WPU is not the first Wearable SoC announced, as for instance AllWinner mentioned their WX quad core SoC for Wearables should become available in Q4 2014 in their roadmap, and Mediatek vaguely unveiled their Aster SoC at CES 2014, but it’s the first that I know of where we’ve got most of the details announced.

Dhanush WPU Block Diagram

Dhanush “Advanced” WPU Block Diagram

Now that block diagram looks interesting… In order to achieve maximum battery life, Ineda has adopted a sort of “big.LITTLE processing” concept to wearables which they call Hierarchical Computing Architecture (HCA) with up to 3 cores offering three levels of performance and power consumption: MIPS microAptiv (always on for sensors, ultra-low power), MIPS microAptive (low power), and MIPS interAptive application processor.

Dhanush SoCs actually comes in four flavor with only one core, 2-level HCA or 3-level HCA:

HCA Power / Features, and Speech Processing Example

HCA Power / Features, and Speech Processing Example

  • Dhanush Nano
    • microAptiv MCU
    • Memory – On-chip SRAM
    • For werable devices that require MCU class of compute and memory footprint such as smartbands
  • Dhanush Micro (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM
    • Typical application would be a Linux based or RTOS based smartwatch.
  • Dhanush Optima (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM + LPDDR2
    • For Linux based smartwatches requiring more features
  • Dhanush Advanced (3-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Dual-core, multi-threaded interAptiv CPU
    • Multimedia – PowerVR GPU and VPU for video encode/decode
    • Memory – On-chip SRAM + LPDDR2
    • For more advanced, high-end wearables that require high resolution rendering, handle complex image/video processing via GPU compute and also support low power video recording and playback. Typical applications would be a Android smartwatches or smart glasses.

Ineda Systems can provide two SHASTRA development kit:

  • SHASTRA-A for Dhanush Advanced (INCDHAD1) which can also be used to evaluate Dhanush Optima
  • SHASTRA-M for Dhanush Micro (INCDHMC1) which can also be used to evaluate Dhanush Nano
SHASTRA-A_Development_Kit

SHASTRA-A Development Board

The boards come with a software development kit (SDK) including a unified development environment (OS, Drivers, Services, APIs, Sample Applications), integrated resource & power management, a GUI framework, user guides, tools & build utilities and power profiling tools. There are two variants of SHASTRA SDK, one for evaluation, and one for product development.

Dhanush Advanced (INCDHAD1) and Micro (INCDHMC1) are now sampling for early customers. Production status of Nano and Optima versions are not been disclosed. I’d guess that means actual products may retail by the end of the year at the earliest. You can find more information on Ineda Systems’ Dhanush WPU page, as well as Imagination Technologies Blog.

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Prpl Non-Profit Organization to Work on Linux, Android, and OpenWRT for MIPS based Processors

May 28th, 2014 5 comments

prplIn what looks like an answer, albeit fairly late, to Linaro, the non-profit organization working on open source software for ARM based SoCs, a consortium of companies composed of Imagination Technologies, Broadcom, Cavium, Lantiq, Qualcomm, Ingenic, and a few others, has funded Prpl (pronounced Purple), “an open-source, community-driven, collaborative, non-profit foundation targeting and supporting the MIPS architecture—and open to others—with a focus on enabling next-generation datacenter-to-device portable software and virtualized architectures”.

The Prpl foundation will focus on three key objectives:

  • Portability – To create ISA agnostic software for rapid deployment across multiple architecture
  • Virtualization & security – To enable multi-tenant, secure, software, environments in datacenter, networking & storage, home, mobile and embedded
  • Heterogeneous Computing – To leverage compute resources enabling next generation big data analytics and mining

Initially there will PEG (Prpl Engineering Group) to take of the following projects for 4 market segments (datacenter, network & storage, connected consumers, and Embedded & IoT):

  • Linux –  Optimizations for enterprise, home and embedded Linux.
  • Android – Getting started with Android, and Android source code
  • Developer Tools – Used in conjunction with Android and Linux OS
  • Virtualization & Secure Supervisor – Secure multi-container frameworks
  • OpenWRT – Enabling carrier-grade features to complement OpenWRT
Arduino Yun

Arduino Yun

It also appears some low cost MIPS32 & MIPS64 development board and reference designs will be supported such as Newton wearable platform, Microchip chipKit WF32 board, and Arduino Yun.

Companies can join Prpl as Board Members or Contributors Members, and individuals can join the foundation for free to engage with the community and access source code and tools.

Since the the Prpl foundation has just been launched, there aren’t any tools or software available right now, but if you are interested in MIPS development, and possibly other architecture which may be part of Prpl later on, you can get more information and/or join the foundation on Prpl Foundation Website.

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