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Posts Tagged ‘soc’

LG NUCLUN Octa-core ARM SoC Powers G3 Screen Smartphone

October 25th, 2014 5 comments

LG has been making mobile devices since 1997, has entered the smartphone market in 2010, and they’ve now decided to foray into mobile SoC, with their very first SoC being an octa-core Cortex A15/A7 processor called NUCLUN, and found in their latest G3 Screen smartphone running Android 4.4.4.

LG_G3_Screen_NUCLUN_Processor

Details about NUCLUN processor are sparse, but the company did provide some specifications for LG G3 Screen smartphone:

  • SoC – LG NUCLUN (LG7111) Octa-Core big.LITTLE processor with four ARM Cortex A15 cores @ 1.5GHz, four ARM Cortex A7 cores @ 1.2GHz.
  • System Memory – 2GB RAM
  • Storage – 32GB  eMMC + MicroSD slot
  • Display – 5.9″ Full HD IPS touchscreen
  • Camera – 13MP OIS+ rear camera, 2.1MP front-facing camera
  • Network – LTE-A Cat.6 for up to 225Mbps download speed.
  • Battery – 3,000mAh
  • Dimensions – 157.8x 81.8x 9.5mm
  • Weight – 182g

The phone,  also codenamed as LG Liger F490L, F490K or F490S (depending on carrier) , runs Android 4.4.4 KitKat on top of Linux 3.10.40+. The GPU was not listed, but based on some CPU-Z screenshots a PowerVR GPU (Series 6?) is used in NUCLUN. The firmware may not be optimized for performance just yet, as Antutu 5.1.5 score is just 25,460 points.

LG_G3_Screen_CPU-Z_Antutu

LG G3 Screen will only be available later this week in Korea, but price has not been disclosed yet.

Via Liliputing, GSMArea, and kenhcongnghe

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ICube MVP SoCs Combine CPU and GPU into a Single Unified Processing Unit (UPU)

October 15th, 2014 2 comments

ICube is a fabless semiconductor company developing SoCs featuring a Unified Processing Unit (UPU) that takes care of the tasks usually handle by separate CPU and GPU on typical SoCs. The UPUs are based on MVP (Multi-thread Virtual Pipeline) instruction set architecture, and are themselves called MVP cores. The company has now two SoCs based on UPU MVP cores: IC3128 and IC3228.

IC3228 Block Diagram

IC3228 Block Diagram

IC3128 is a single core / 4 thread SoC, and IC3228 is a dual MVP core / 8 threads SoC. Let’s have a look at IC3228 technical specifications:

  • CPU function
    • 4-way simultaneous multi-threading (SMT) in each core
    • Symmetric-multi-processing (SMP), dual MVP cores
    • 64KB I-cache, 64KB D-cache and 64KB local memory in each core, 256KB shared L2 cache
    • Homogeneous parallel programs
    • Support Pthread, OpenMP
  • GPU function
    • Data parallel, Task parallel, and/or Function parallel computing
    • Multi-standard media processor
    • Programmable unified shader
    • Support OpenGL ES 2.0
    • 70 million triangles / sec, 300 million pixel / sec
  • System Clock – 600MHz (TSMC 65nm)
  • Multi-thread Processing
  • Simultaneous 8 threads (4 threads x dual core) and 8 hybrid threads
  • Processing Power – 5160 DMIPS (equivalent to 4.3 DMIPS/MHz per core)
  • Display System
    • LCD maximum pixel clock: [email protected] (24-bit) true color,
    • HDMI/DVI output capable
  • Camera – 8/10 bit camera data interface
  • Video – Support HD 720p H.264 decoding via pure software
  • Audio – Max. 5.1 channel audio
  • Memory – Support SD, SDHC, MMC card, USB mass storage device, Nand flash, NOR flash, DDR3 SDRAM
  • Power Control – 10 independent power domain, 3 low power modes
  • Connectivity and I/Os
    • USB host/slave
    • WiFi (external), 3G modem (external), GPS (external)
    • 12 keypad I/O for Qwerty keyboard
    • 4x UART; 2x I2C; 3x I2S; 4x SPI slave; 9x GPIO x 9; 3x PWM
  • Timers – Watchdog, RTC

IC3128 has only one MVP core (4 thread) @ up to 400 MHz, supports 800×400 displays, and can decode 480p videos (H.264, MPEG4, RMVB, and ) @ 25 fps, so it’s very much a low end processor, and you could easily argue that even IC3288 is pretty much low end by today’s standards, especially when it comes to media capabilities. 5,000 DMIPS correspond to what you could get with a single core ARM Cortex A9 processor clocked at 2 GHz.

The advantage for this new architecture is that the company does not need to purchase license for processor cores, GPU cores, etc.. potentially providing  a most cost effective solution, and development should not be hindered by binary blobs, and the obvious downside is that lots of work needs to be done to port software to this new architecture, but the company claims that Android 4.2 / Linux 3.4 have already been ported to the platform.

ICube Evaluation Board

ICube Evaluation Board

ICube also offers a reference platform based on IC3228 with a 4.3″ or 7″ display, HDMI, USB, etc..  for development and evaluation of their solution. Documentation, and Android SDK and NDK are provided with the kit.

I can’t find any product based on ICube MVP processors yet, as it’s still very new, but Rhombus Tech / Qimod has recently made a Micro Desktop prototype based on IC3128 processor, using an EOMA-68 module and a baseboard with Ethernet & USB ports (using SMIC 9514 controller), UART, a micro SD card, etc… and IC3128 price is indeed competitive as it’s supposed to sell for just $2.

There’s no publicly available documentation or source code just yet, but you may want to visit ICube website for a few more details.

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Imagination Technologies Unveils Low Power Low Footprint PowerVR GX5300 GPU for Wearables

July 22nd, 2014 No comments

Up to now most wearables are based on MCU solutions or derived from mobile platforms, which may either not provide the advanced features required by users, or consume too much power and take more space than needed. With Ineda Dhanush and Mediatek Aster, we’ve already seen silicon vendors design wearables SoCs, and now Imagination Technologies has just announced PowerVR GX5300 GPU targeting wearables with support for OpenGL ES 2.0, 480p to 720p resolution, and using 0.55mm2 silicon area based on 28nm process.

PowerVR GX5300 Block Diagram

PowerVR GX5300 Block Diagram

PowerVR GX5300 GPU will be support Android, Android Wear, and Linux based operation systems, and according to the company has the following key features:

  • Unified shaders – The TBDR graphics architecture offers unified shaders where vertex, pixel and GPU compute resources are scaled simultaneously.
  • Low power and high precision graphics – All PowerVR GPUs offer a mix of low (FP16) and high precision (FP32) rendering and implement the full OpenGL ES 2.0 specification.
  • Reduced memory footprint - PowerVR GX5300 supports PVRTC, a texture compression format which reduces memory bandwidth and decreases power consumption. It can help silicon vendors reduce memory costs.

Typical applications will be embedded Linux or Android-based connected home systems that require graphics rendering such as smart washing machines, and wearables running Android Wear such as smartwatches.

PowerVR GX5300 is available for licensing now, but it has not been announced in any wearable SoCs just yet, so it’s probably something we’ll see in products in 2015.

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AllWinner V10 and V15 SoCs Target Video Recording Applications

July 9th, 2014 1 comment

AllWinner A-series that can be found in tablets and media players are pretty well known, but AllWinner also has V-Series processors with V10 and V15. A first glance, AllWinner V10 is quite similar to AllWinner A31 with a quad core Cortex A7 CPU coupled with a PowerVR SGX544MP2 GPU, and AllWinner V15 has the same CPU/GPU combo as AllWinner A10 (CortexA8/Mali-400). But AllWinner V-Series are actually video encoders targeting applications such as IP cameras, car DVRs, and sports digital video cameras thanks to features such as motion detection, video scaling, and digital watermarking.

AllWinner V10 Block Diagram

AllWinner V10 Block Diagram

Let’s go through AllWinner V10 specifications, and I’ll mark differences with AllWinner A31, or features not mentioned in A31 specs, in bold:

  • CPU – Quad-core ARM Cortex-A7 with· 256KB L1 cache, 1MB L2 cache
  • GPU – PowerVR SGX544MP2 compliant with OpenCL 1.1 EP and delivering up to 20GFLOPS.
  • Memory – 32-bit DDR3/LPDDR2 SDRAM controller, supporting up to 2GB; NAND I/F
  • Video
    • Supports H.264 High Profile 1080p@60fps video encoding
    • Digital watermarking
    • Motion detection
    • CBR/VBR bit rate control mode
    • Supports UHD@24fps video decoding
    • Supports multi-format video decoding including MPEG 1/2/4, H.264, VP8, AVS,VC-1, etc.
    • Supports independent encoding and decoding
    • 1/16 ~ 16x scaling
  • Video Input/Output
    • Supports 12-bit parallel CSI and 4-lane MIPI CSI
    • Supports up to 12M CMOS sensor
    • Supports RGB LCD/LVDS/MIPI DSI/HDMI
    • Supports one video layer and two graphic layers
    • Supports scaling up to 4K x 4K
  • HawkView ISP
    • Auto exposure/focus/white balance (AE/AF/AWB)
    • Dynamic range control (DRC)
    • Color enhancement
    • Noise reduction
  • Audio Codec
    • Integrated Hi-Fi 100dB audio codec
    • Three integrated differential analog mic amplifiers for headset and phone
    • One digital mic interface with software noise cancellation
  • Peripherals
    • 3 x USB ports
    • 4 x SD card 3.0
    • RTP/CTP
    • GMAC/EMAC
  • Package – BGA609, 18mm x 18mm, 0.65 pitch

AllWinner V10 also appears to be lacking 3840×1080 3D decoding ability found in A31, and may not have a dual band RAM interface, and no support for LPDDR3 memory. I’m not sure if A31 also supports independent encoding and decoding, or that would means Skype or Google Hangout calls are partially handled by software. AllWinner provides support for Android and Linux operating systems for the V10 and V15 processor, specifically Android 4.4 for V10. AllWinner V15 has similar features as V10 but only comes with a single Cortex A8 core, a Mali-400 GPU, supports 1080p decoding, 720p encoding, and features less peripherals. It’s also smaller with a BGA336 (14mm x 14mm) package.

I could not find any development boards, nor products based on AllWinner V10 and V15. There may be some, but the processors are seldom advertised in devices like digital cameras, and digital video recorders. I’ve asked some details to AllWinner, and I’ll update this post if I get an answer.

You can may find more information in AllWinner V10 and V15 on their respective product pages.

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Ineda Systems Dhanush WPU is a MIPS based SoC Specifically Designed for Wearables

June 5th, 2014 No comments

What’s a WPU? It stands for Wearable Processor Unit, and as you may guess it’s a processor specifically designed to be used in wearables such as smartwatches or fitness trackers.  Currently many wearables are based on application processors that are used in smartphones (e.g. Galaxy Gear), and lower-end versions are based on standard low power MCUs (e.g. Pebble), but none of them are actually based on SoC specifically designed for wearables, and analysts are asserting that new types of SoC are definitely needed if companies are to provide wearables with the battery life and features consumers want. Ineda Systems Dhanush WPU is not the first Wearable SoC announced, as for instance AllWinner mentioned their WX quad core SoC for Wearables should become available in Q4 2014 in their roadmap, and Mediatek vaguely unveiled their Aster SoC at CES 2014, but it’s the first that I know of where we’ve got most of the details announced.

Dhanush WPU Block Diagram

Dhanush “Advanced” WPU Block Diagram

Now that block diagram looks interesting… In order to achieve maximum battery life, Ineda has adopted a sort of “big.LITTLE processing” concept to wearables which they call Hierarchical Computing Architecture (HCA) with up to 3 cores offering three levels of performance and power consumption: MIPS microAptiv (always on for sensors, ultra-low power), MIPS microAptive (low power), and MIPS interAptive application processor.

Dhanush SoCs actually comes in four flavor with only one core, 2-level HCA or 3-level HCA:

HCA Power / Features, and Speech Processing Example

HCA Power / Features, and Speech Processing Example

  • Dhanush Nano
    • microAptiv MCU
    • Memory – On-chip SRAM
    • For werable devices that require MCU class of compute and memory footprint such as smartbands
  • Dhanush Micro (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM
    • Typical application would be a Linux based or RTOS based smartwatch.
  • Dhanush Optima (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM + LPDDR2
    • For Linux based smartwatches requiring more features
  • Dhanush Advanced (3-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Dual-core, multi-threaded interAptiv CPU
    • Multimedia – PowerVR GPU and VPU for video encode/decode
    • Memory – On-chip SRAM + LPDDR2
    • For more advanced, high-end wearables that require high resolution rendering, handle complex image/video processing via GPU compute and also support low power video recording and playback. Typical applications would be a Android smartwatches or smart glasses.

Ineda Systems can provide two SHASTRA development kit:

  • SHASTRA-A for Dhanush Advanced (INCDHAD1) which can also be used to evaluate Dhanush Optima
  • SHASTRA-M for Dhanush Micro (INCDHMC1) which can also be used to evaluate Dhanush Nano
SHASTRA-A_Development_Kit

SHASTRA-A Development Board

The boards come with a software development kit (SDK) including a unified development environment (OS, Drivers, Services, APIs, Sample Applications), integrated resource & power management, a GUI framework, user guides, tools & build utilities and power profiling tools. There are two variants of SHASTRA SDK, one for evaluation, and one for product development.

Dhanush Advanced (INCDHAD1) and Micro (INCDHMC1) are now sampling for early customers. Production status of Nano and Optima versions are not been disclosed. I’d guess that means actual products may retail by the end of the year at the earliest. You can find more information on Ineda Systems’ Dhanush WPU page, as well as Imagination Technologies Blog.

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Cavium ThunderX Server SoC Features up to 48 ARM 64-bit Cores

June 4th, 2014 5 comments

ARM SBSA specification for server supports up to 268,435,456 CPU cores for the second level of standardization on one or a combination of SoCs. We’re not quite up there just yet, but Cavium ThunderX is an ARM server SoC with up to 48 cores on a single chip, which is the highest number of cores I’ve ever heard of in an ARM SoC.

Cavium Thunder X Block Diagram

Simplified Cavium ThunderX Block Diagram

The company created their own custom processor cores using an ARMv8 architecture license, designing an SoC complies with ARM’s Server Base System Architecture (SBSA) standard with the following key features:

  • ARM based SoC that scales up from 8 to 48 cores with up to 2.5 GHz core frequency with 78K I-Cache, 32K D-Cache, and 16MB L2 cache.
  • Fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI)
  • Integrated I/O capacity with 100s of Gigabits of I/O bandwidth
  • 4x DDR3/4 72-bit memory controllers supporting up to 1TB RAM @ 2400 MHz in a dual socket configuration
  • Hundreds of integrated hardware accelerators for security, storage, networking and virtualization applications.
  • Cavium virtSOC technology allowing full system virtualization for low latency from virtual machine to I/O.
  • Best in class performance per watt and performance per dollar for the target applications

ThunderX processor family is comprised of several models depending on target applications: Compute, Storage, Secure Compute, and Networking as well as server chips (CN88XX_X)with 24 to 48 cores, and low-end server chips (CN87XX_X) with 8 to 16 cores.

The server chips are available in 4 SKU families:

  • ThunderX_CP (Compute)
    • Up to 48 cores along with integrated virtSOC, dual socket coherency, multiple 10/40 GbE and high memory bandwidth.
    • Optimized for private and public cloud web servers, content delivery, web caching, search and social media workloads.
  • ThunderX_ST (Storage)

    • Up to 48 cores along with integrated virtSOC, multiple SATAv3 controllers, 10/40 GbE & PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes hardware accelerators for data protection/ integrity/security, user to user efficient data movement (RoCE) and compressed storage.
    • Optimized for Hadoop, block & object storage, distributed file storage and hot/warm/cold storage type workloads.
  • Thunder_SC (Secure Compute)

    • Up to 48 cores along with integrated virtSOC, 10/40 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes Cavium’s 4th generation NITROX and TurboDPI technology with acceleration for IPSec, SSL, Anti-virus, Anti-malware, firewall and DPI.
    • Optimized for Secure Web front-end, security appliances and Cloud RAN type workloads.
  • Thunder_NT (Networking)

    • Up to 48 cores along with integrated virtSOC, 10/40/100 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric with feature rich capabilities for bandwidth provisioning , QoS, traffic Shaping and tunnel termination.
    • Hardware accelerators include high packet throughput processing, network virtualization and data monitoring.
    • Optimized for media servers, scale-out embedded applications and NFV (Network Functions Virtualization) type workloads.

The cost and power optimized ThunderX CN87xx family with 8 to 16 cores will be available in single socket configuration with two DDR3/4 controllers, multiple 10GbE, SATAv3 and PCIe Gen3 interfaces. It will be used for cold storage, distributed content delivery, dedicated hosting, distributed memory caching and embedded and control plane.

Cavium has partnered with several companies, including ODM and OEM partners such as GIGABYTE and Hewlett Packard, is part of Linaro, the Linux Foundation, OpenStack, UEFI, Xen, etc.. industry groups.  Supported operating systems include Canonical’s Ubuntu, RedHat’s Fedora,  MontaVista Linux and openSUSE.  Oracale Java, OpenJDK and GNU toolchain have been ported to the platform, as well as KVM and Xen virtualization platforms.

The company expects ThunderX processors and hardware reference platforms to be available in Q4 2014. Further details may be available on Cavium’s ThunderX page.

Via EETimes

[Update: Here's the pic of the dual socket board (96 cores: 48 + 48) via armdevices.net. There's also a single socket version. They all require an heatsink as shown in the bottom left corner of the pi (red/orange heatsink]

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)

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Your New ARM SoC Linux Support Check-List – ELCE 2012

January 16th, 2013 No comments

Thomas Petazzoni, embedded Linux engineer and trainer at Free Electrons, describes the steps he followed to add a new Marvell SoC to the mainline kernel at ELCE 2012.

Abstract:

Since Linus Torvalds raised warnings about the state of the ARM architecture support in the Linux kernel, a huge amount of effort and reorganization has happened in the way Linux supports ARM SoCs. From the addition of the device tree to the pinctrl subsystem, from the new clock framework to the new rules in code organization and design, the changes have been significant over the last one and half year in the Arm Linux kernel world.

Based on the speaker’s experience on getting the support for the new Marvell Armada 370 and Armada XP SoC support in the mainline Linux kernel, we will give an overview of those changes and summarize the new rules for ARM Linux support. We aim at helping developers willing to add support for new ARM SoCs in the Linux kernel by providing a check-list of things to do.

6 Steps to follow to get a minimal Linux image boot on a new ARM SoC

6 Steps to follow to get a minimal Linux image boot on a new ARM SoC

Here’s a summary of the main steps to go through to port a new SoC to ARM Linux:

  1. Minimal image – Write your device tree (arch/arm/boot/dts),  implement basic initialization C and header files (arch/arm/mach-foo), the timer driver (drivers/clocksource), the IRQ controller driver (drivers/irqchip),  earlyprintk support (arch/am/include/debug), and the serial port driver (drivers/tty/serial)
  2. More core infrastructure – Add pin muxing control (drivers/pinctrl), clocks (drivers/clk), and GPIO (drivers/gpio)
  3. More drivers, advanced features – Add the network driver (drivers/net), SPI controller driver (drivers/spi), SMP support, SATA controller driver (drivers/ata), Power management, and other drivers.

In all the steps above, each driver must have its own device tree binding. and they cannot include <mach/something.h> anymore as they must be supported by different platforms without having to rebuild them. Device tree is now compulsory for all new SoC, and it you have old code for an existing SoC, it’s very likely you’ll have to start from scratch due to device tree and the many changes that occurred in the kernel in the last two years.

Many ARM SoCs still do not comply with the current best practices, and Thomas recommends to have a look at the following implementations to get started:

  • arch/arm/mach-highbank
  • arch/arm/mach-socfpga
  • arch/arm/mach-bcm2835 (So having a Raspberry Pi might be a good idea to learn and experiment about device tree)
  • arch/arm/mach-mxs
  • arch/arm/mach-mvebu

You can also download the slides for this presentation.

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