Posts Tagged ‘soc’

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

July 12th, 2016 5 comments

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself.

Freedom U500 Block Diagram

Freedom U500 Block Diagram

But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller.

Freedom U500 (Unleashed family) platform key specifications:

  • U5 Coreplex with 1 to 8 U54 cores @ 1.6GHz+
  • RV64GC Architecture (64- bit RISC-V)
  • Multicore, Cache Coherency Support
  • High Speed Peripherals: PCIe 3.0, USB3.0, GbE, DDR3/4
  • TSMC 28nm

The SoC supports Linux, and targets applications such as machine learning, storage, and networking.

Freedom E300 Block Diagram

Freedom E300 Block Diagram

Freedom E300 (Everywhere family) platform key specifications:

  • E3 Coreplex
  • RV32IMC/RV32EMC Architecture
  • On chip Flash, OTP, SRAM
  • TSMC 180nm

Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.

Open source SoCs are made to be customizable to match your applications exact needs, instead of picking on existing SoC matching your requirements but with some uneeded features. SiFive also explains that “storage customers talks about custom instructions for bit manipulation so they can use one not 10 instructions for 10x speed up”. But before you get to Silicon, you’d normally ruin and customize the core on FPGA boards and three boards are currently available for development and evaluation:

  • Freedom U500:
  • Freedom E300 – Digilent Arty FPGA development kit powered by Xilinx XC7A35T-L1CSG324I FPGA, with 256 MB RAM, 16 MB flash, and vairous expension ports. Price: $99
Click to Enlarge

Xilinx Virtex-7 FPGA VC707 devkit – Click to Enlarge

You also have detailed documentation about the SoCs, U5 nd U3 coreplex, the development kits, software and tools, as well as developer forums, on SiFive developers website. You can also directly checkout the code and SDK on github.

RISC-V instructions set is royalty-free, so compared to the entry level $40,000 ARM license for startups using Cortex M0 MCU, it should provide some savings. It does not help with manufacturing costs which should remain the same. but SiFive expects that open source SoC could be manufactured through a “moderate” crowdfunding campaign.  I have not been able to figure out SiFive business model yet, unless they plan on selling their own chips too, and/or provide customization services to customers.

Lots more information can be found on Sifive website.

Via EETimes

FOSDEM 2015 Schedule – January 31 – February 1 2015

January 29th, 2015 8 comments

FOSDEM (Free and Open Source Software Developers’ European Meeting) takes place every year during the first week-end of February. This year the developer-oriented event expects to bring over 5000 geeks to share ideas and collaborate on open source projects. Contrary to most other events, it’s free to attend, and you don’t even need to register, just show up. FOSDEM 2015 will take place on January 31- February 1 in Brussels.

Fosdem_2015There will be 551 sessions divided into 5 keynotes, 40 lightning talks, 6 certification exams, and with the bulk being developer rooms and main tracks,  divided into 7 main tracks this year: Languages, Performance, Time, Typesetting, Hardware, Security and Miscellaneous.

I’m not going to attend, but it’s still interested to see what will be talked about, and I’ve concocted my own little virtual program out of the main tracks and developers’ rooms. There’s a few minutes overlap between some talks on Sunday.. Oh well.

If you won’t be able to attend, you should be able to watch the video and access the slides in a few weeks, as most sessions will be recorded.

What is the current status of Allwinner support in upstream u-boot and the kernel, which SoCs are supported, and which features (sound, video, etc.) are supported ?

The linux-sunxi community has been slowly but steadily working on getting Allwinner SoCs like the A10 supported in upstream u-boot and the kernel.

This talk will present the current status of Allwinner support upstream. Which SoCs are supported and which ones are not (yet) supported ? Which blocks if the supported SoCs are supported, and which are not ? Why are some SoCs / blocks not supported, and what are the plans to get them supported ? This are some of the questions this talk tries to answer.

Not all free operating systems are feature-full POSIX systems. FreeRTOS is a minimal operating system which is designed to run on micro-controllers, and provide real-time scheduling. It is used in industrial automation and automotive.

A brief introduction to FreeRTOS, depending on audience preference, will be followed by either a hands-on workshop using PCs, or a demonstration on a board. The workshop includes how to get started, what can be done with it, and what type of features and pitfalls to expect from FreeRTOS.

As ADAS and infotainment require more electronics, using an hypervisor is a solution to gather multiple boards into one. Xvisor is an open source lightweight hypervisor for embedded systems that perfectly fits the needs of the automative industry. It is a complete monolithic type-1 hypervisor with full virtualization and paravirtualisation support, showing better performances than KVM. We, OpenWide and the Institute for Technological Research SystemX, are working on its port on i.MX6 boards.

F*watch is an infinitely hackable GPS watch with many sensors based on a 100% Free design. Everything is Free, from the PCB and watch housing design to the software stack. Moreover, only Free software tools have been used during the development.

F*watch. Why should your watch be different?

The talk describes the development process and shows a first prototype, along with performance measurements and future plans.

The lowRISC project was established in the summer of 2014 with the aim of producing a complete open-source System-on-Chip in volume, with low-cost development boards. Alex Bradbury, one of the co-founders of the project will discuss the progress to date and the path to the first test chip. lowRISC implements the open RISC-V instruction set architecture and is exploring ideas on improving security via tagged memory and increasing flexibility through the addition of RISC-V ‘Minion’ cores to implement soft peripherals. This talk will discuss the potential benefits of a fully open-source hardware ecosystem, the challenges of getting to first silicon, and how the open source community at large can help.

Digital cameras provide almost every feature you could want. But if they don’t, you are forced to upgrade or go without. CHDK is a project which allows you to program new functionality to the majority of Canon cameras, in either C, Lua, or Basic. The talk features background on the project, code, tools, and the methods of compiling and introducing a new firmware into the camera.

Over the course of 1 hour, Steven Goodwin will guide the audience through the entire process of taking a normal (proprietary) camera and converting it into an open source version by installing custom firmware on it. He will then cover some of the features available (such as the on-device scripting language) and continue by explaining how to build and debug your own functionality. Starting with simple grids, continuing with games, and time-lapse code. And ending with a fully recompiled firmware running on the device.

The video4linux kernel subsystem reports which colorspace the captured video uses. But what does that really mean, and what do you have to do to correctly reproduce those colors? This talk will dive into the crazy world of colorspaces and give you a practical guide to colorspace handling. I will also demonstrate colorspace handling, both right and wrong.

Kernel profiling tools status on ARM and ARM64: – perf status, – ARM and ARM64 support, – callchain unwinding mechanisms and support, – patches status: merged, pending, in development, – links to discussions (LKML) and patches.

The profiling tools in the kernel are changing at a fast pace. This talk is about the support for ARM and ARM64 architecture and the development of features for these architectures, namely the callchain unwinding. The presentation goes over: – the detailed description of the feature, – the methods used to do the callchain unwinding (fp, exidx, dwarf etc.), – the status of the on-going patches, – the remaining work to be done, – the links to patches, discussions on the mailing lists, – -if needed and if time allows- a demo of the feature.

Building a medical device requires to follow certain rules specially when health care depend on it. The presentation will explain how Yocto help us in Kaptalia to solve this issue. In particular we will focus on fast boot, update with unskilled user base, Bluetooth Low Energy, security and data privacy.

During this event we will show how our team succeeded to build our first OS, start from a company with medical expert only and no prior expertise on embedded systems. At the end, a live demonstration for using the the monitor and sensor will be held.

LAVA is a python service created by Linaro for testing software on hardware which accepts test jobs to perform on selected hardware to provide a black box to continuous integration tests. Bisecting is a technique for finding commit in version control system that broke the software. Git provides the powerful “git bisect” subcommand for this purposes. In this talk we give and introduction to LAVA and explain howto combine LAVA and git bisect to automatically find offending commits in the Linux kernel.

Prospero Technologies has made a Linux based Digital Video Recorder which constantly records all UK broadcast TV so that the consumer no longer needs to schedule recordings. This will be a talk on the technologies used to achieve this, the open source software on the consumer device and how you can build your own 30 channel DVR.

The final version of the DVR uses a Freescale i.MX6 CPU with a video processing unit running a Linux built with Yocto. The talk will cover how well this is supported by gstreamer and how we built a QT application to display our HTML5 interface.

More and more embedded projects require support for advance connectivity. With it, comes the requirement to enforce a better security as well as private data protection. Using the layer model of Yocto, we show how we can extract from a complex project such as Tizen, advance connectivity and security and apply it to any embedded project.

The Internet of Things (IoT) is growing fast and opens large opportunities to embedded Linux. Unfortunately traditional embedded Linux has been weak when it comes to security and complex connectivity enabling. Tizen which has been developed as a Linux base OS for connected object (phone, TV, car) is on the other side very well equipped in that area. We will start by explaining what is Tizen architecture and how it provides Security and Connectivity facilities on top of a base Linux. We will then show how Yocto and Tizen-meta can be used to create embedded devices which benefit from several years of work done by the Tizen community. In particular we will review : – the mandatory access control enabling in an embedded device – the enforcement of good behavior by applications – resource access control – connectivity layers – HTML5 App enabling. – multi user mode enabling.

The ARM LLVM backend has been around for many years and generates high quality code, yet there are still standard benchmarks where GCC is generating more efficient code than LLVM. The goal of this talk is to get a better understanding of why the GCC-generated code for those benchmarks is executing more efficiently and also about finding out what we need to do on the LLVM side to address those code generation deficiencies. This talk presents current performance numbers for the SPEC CPU benchmark suites on ARM, comparing the performance of LLVM and GCC, with the main focus on the SPEC CPU integer benchmarks. To dive a little bit deeper, we will also have a closer look at the generated assembly code of selected benchmarks where LLVM is performing worse than GCC and use the results of this performance analysis to point out potential code generation opportunities for LLVM.

Connectivity is crucial for Internet of Things concept. For moving devices like position data loggers is typical solution GSM network. I will show you how you can use different types of GSM network for your IoT projects.

GSM network is easy way how to connect almost any device to internet. There are lot of GSM modules on market from different vendors but all devices has one thing in common – AT commands. There is standardized AT commands set for GSM networks. Using AT command you can send text messages, read phone number from list on SIM card, connect to internet and much more. I will show you basic command set for HTTP communication using basic GSM module SIM900 and Arduino.

This talk will give an overview over the Linux backports project and how to use it. The Linux backports project makes it possible to use a driver from a recent Linux mainline kernel with an older kernel version.

When you have a vendor board support package which does not use a bleeding edge mainline kernel, like it is the case most times, but you want to use some driver from a bleeding edge Linux kernel you can use backports. Backports “automatically” generates a tar with many drivers from a specific Linux mainline kernel which can be used with older kernel versions.

In this talk I will describe how the backports project, with its compatibility layer, the spatches and the normal patches. For practical usage I will show how to use backports with your own kernel in addition I will give a brief overview on how to add a new driver to backports.

Patchwork is a toolkit for connecting various devices into a network of things or, in a more broad case – Internet of Things (IoT). The main goal of creating this toolkit is to have a lightweight set of components that can help to quickly integrate different devices (i.e. Arduino, Raspberry Pi, Plugwise, etc) into a smart environment and expose specific devices’ capabilities as RESTful/SOAP/CoAP/MQTT/etc services and data streams.

The key features of patchwork include:

  • Lightweight (no RAM-consuming sliced pie of Java and OSGi, only bare necessities)
  • Cross-platform (can be deployed on OSX/Linux/Windows, tested on Raspberry Pi and BeagleBone Black boards)
  • Language-agnostic (device agents can be written in any programming language, APIs can be consumed by app written in any programming language)
  • Easily deployable (no JARs, no Eggs or Wheels for the core components, just a single native binary with statically linked dependencies)
  • Easily extendable (integrate new devices without modification of the core components, drop in solution)
  • Interchangeable (not happy with current existing Device Gateway or Catalog? replace it with another implementation without breaking the infrastructure)
  • Not re-inventing the wheel (we re-use as many existing technologies and components as possible)

libcurl is the world’s most used and most popular Internet transfer library, already used in every imaginable sort of embedded device out there. How did this happen and how do you use libcurl to transfer data to or from your device?

Embedded devices are very often network connected these days. Network connected embedded devices often need to transfer data to and from them as clients, using one or more of the popular internet protocols.

Daniel once founded the project and is still lead developer and maintainer of the curl project, making curl and libcurl. He is also active within IETF and maintain several other open source projects. Daniel is employed by Mozilla.

This presentation will reveal the process of porting Tizen:Common to open source hardware developer boards with SoC manufactured by Allwinner, Rockchip or Intel such as OLinuXino, Radxa Rock, Minnowboard. The following topics will be covered:

  • Building Tizen ARMv7 and x86 images from scratch
  • Adapting the Linux kernel, bootloader and Tizen:Common to popular single board computers
  • Do it yourself (DIY) open-source hardware Tizen tablet or laptop
  • Sharing knowledge and experience of the community.
The presentation will also provide information about U-Boot, Yocto project, the Linux-Sunxi and Linux-Rockchip, Minnowboard communities.

Although Tegra K1 uses the same Kepler architecture as NVIDIA desktop cards that Nouveau already supports, there are other challenges that need to be addressed before Nouveau can drive K1’s graphic acceleration: the fact that the GPU does not reside on the PCI bus requires architectural changes in the Nouveau core. The absence of dedicated GPU memory directly interferes with the way Nouveau is used to do memory management and leads to potentially sub-optimal behavior. Also, in a system where all devices share the same system memory, PRIME support is mandatory to perform any useful work and the relevance of a driver-agnostic memory allocator becomes perceptible.

This talk will discuss these challenges, and in particular the consequences of using a unified memory architecture, in the hope of triggering discussions that will help improving the general support of GPU architectures for new mobile platforms.

A brief look at the past, present, and future of the KiCad project. The discussion will be primarily on what near and long term future development is planned for the project as well as discussing the potential for collaboration with other EDA projects.

Yocto has an alleged steep learning curve. It can be a challenge for modules and evaluation board manufacturers to add support for their devices in Yocto as they don’t necessarily have a software background. This talk will highlight the steps required, techniques and good practices to create a well integrated machine configuration allowing to build images using the Yocto Linux build system. The Crystalfontz support from meta-fsl-arm-extra will be used to illustrate the talk.

The bitbox console is a small open hardware & open source game console. I will present the rationale behind it and the current status of the project, detail the hardware conception and particularly video signal generation from a cortex-m4 chip with no video subsystem. I will then proceed to show the different elements of the software stack : kernel, video engines, the boot loader and, finally, current programs and games, including a Gameboy emulator and a full motion video player.

If you want to build your own schedule before going, you can check the full list of events by subjects, but an easier way to organize your day is to check the sessions in chronological order, by checking out Saturday and Sunday schedules.

LG NUCLUN Octa-core ARM SoC Powers G3 Screen Smartphone

October 25th, 2014 5 comments

LG has been making mobile devices since 1997, has entered the smartphone market in 2010, and they’ve now decided to foray into mobile SoC, with their very first SoC being an octa-core Cortex A15/A7 processor called NUCLUN, and found in their latest G3 Screen smartphone running Android 4.4.4.


Details about NUCLUN processor are sparse, but the company did provide some specifications for LG G3 Screen smartphone:

  • SoC – LG NUCLUN (LG7111) Octa-Core big.LITTLE processor with four ARM Cortex A15 cores @ 1.5GHz, four ARM Cortex A7 cores @ 1.2GHz.
  • System Memory – 2GB RAM
  • Storage – 32GB  eMMC + MicroSD slot
  • Display – 5.9″ Full HD IPS touchscreen
  • Camera – 13MP OIS+ rear camera, 2.1MP front-facing camera
  • Network – LTE-A Cat.6 for up to 225Mbps download speed.
  • Battery – 3,000mAh
  • Dimensions – 157.8x 81.8x 9.5mm
  • Weight – 182g

The phone,  also codenamed as LG Liger F490L, F490K or F490S (depending on carrier) , runs Android 4.4.4 KitKat on top of Linux 3.10.40+. The GPU was not listed, but based on some CPU-Z screenshots a PowerVR GPU (Series 6?) is used in NUCLUN. The firmware may not be optimized for performance just yet, as Antutu 5.1.5 score is just 25,460 points.


LG G3 Screen will only be available later this week in Korea, but price has not been disclosed yet.

Via Liliputing, GSMArea, and kenhcongnghe

ICube MVP SoCs Combine CPU and GPU into a Single Unified Processing Unit (UPU)

October 15th, 2014 2 comments

ICube is a fabless semiconductor company developing SoCs featuring a Unified Processing Unit (UPU) that takes care of the tasks usually handle by separate CPU and GPU on typical SoCs. The UPUs are based on MVP (Multi-thread Virtual Pipeline) instruction set architecture, and are themselves called MVP cores. The company has now two SoCs based on UPU MVP cores: IC3128 and IC3228.

IC3228 Block Diagram

IC3228 Block Diagram

IC3128 is a single core / 4 thread SoC, and IC3228 is a dual MVP core / 8 threads SoC. Let’s have a look at IC3228 technical specifications:

  • CPU function
    • 4-way simultaneous multi-threading (SMT) in each core
    • Symmetric-multi-processing (SMP), dual MVP cores
    • 64KB I-cache, 64KB D-cache and 64KB local memory in each core, 256KB shared L2 cache
    • Homogeneous parallel programs
    • Support Pthread, OpenMP
  • GPU function
    • Data parallel, Task parallel, and/or Function parallel computing
    • Multi-standard media processor
    • Programmable unified shader
    • Support OpenGL ES 2.0
    • 70 million triangles / sec, 300 million pixel / sec
  • System Clock – 600MHz (TSMC 65nm)
  • Multi-thread Processing
  • Simultaneous 8 threads (4 threads x dual core) and 8 hybrid threads
  • Processing Power – 5160 DMIPS (equivalent to 4.3 DMIPS/MHz per core)
  • Display System
    • LCD maximum pixel clock: [email protected] (24-bit) true color,
    • HDMI/DVI output capable
  • Camera – 8/10 bit camera data interface
  • Video – Support HD 720p H.264 decoding via pure software
  • Audio – Max. 5.1 channel audio
  • Memory – Support SD, SDHC, MMC card, USB mass storage device, Nand flash, NOR flash, DDR3 SDRAM
  • Power Control – 10 independent power domain, 3 low power modes
  • Connectivity and I/Os
    • USB host/slave
    • WiFi (external), 3G modem (external), GPS (external)
    • 12 keypad I/O for Qwerty keyboard
    • 4x UART; 2x I2C; 3x I2S; 4x SPI slave; 9x GPIO x 9; 3x PWM
  • Timers – Watchdog, RTC

IC3128 has only one MVP core (4 thread) @ up to 400 MHz, supports 800×400 displays, and can decode 480p videos (H.264, MPEG4, RMVB, and ) @ 25 fps, so it’s very much a low end processor, and you could easily argue that even IC3288 is pretty much low end by today’s standards, especially when it comes to media capabilities. 5,000 DMIPS correspond to what you could get with a single core ARM Cortex A9 processor clocked at 2 GHz.

The advantage for this new architecture is that the company does not need to purchase license for processor cores, GPU cores, etc.. potentially providing  a most cost effective solution, and development should not be hindered by binary blobs, and the obvious downside is that lots of work needs to be done to port software to this new architecture, but the company claims that Android 4.2 / Linux 3.4 have already been ported to the platform.

ICube Evaluation Board

ICube Evaluation Board

ICube also offers a reference platform based on IC3228 with a 4.3″ or 7″ display, HDMI, USB, etc..  for development and evaluation of their solution. Documentation, and Android SDK and NDK are provided with the kit.

I can’t find any product based on ICube MVP processors yet, as it’s still very new, but Rhombus Tech / Qimod has recently made a Micro Desktop prototype based on IC3128 processor, using an EOMA-68 module and a baseboard with Ethernet & USB ports (using SMIC 9514 controller), UART, a micro SD card, etc… and IC3128 price is indeed competitive as it’s supposed to sell for just $2.

There’s no publicly available documentation or source code just yet, but you may want to visit ICube website for a few more details.

Imagination Technologies Unveils Low Power Low Footprint PowerVR GX5300 GPU for Wearables

July 22nd, 2014 No comments

Up to now most wearables are based on MCU solutions or derived from mobile platforms, which may either not provide the advanced features required by users, or consume too much power and take more space than needed. With Ineda Dhanush and Mediatek Aster, we’ve already seen silicon vendors design wearables SoCs, and now Imagination Technologies has just announced PowerVR GX5300 GPU targeting wearables with support for OpenGL ES 2.0, 480p to 720p resolution, and using 0.55mm2 silicon area based on 28nm process.

PowerVR GX5300 Block Diagram

PowerVR GX5300 Block Diagram

PowerVR GX5300 GPU will be support Android, Android Wear, and Linux based operation systems, and according to the company has the following key features:

  • Unified shaders – The TBDR graphics architecture offers unified shaders where vertex, pixel and GPU compute resources are scaled simultaneously.
  • Low power and high precision graphics – All PowerVR GPUs offer a mix of low (FP16) and high precision (FP32) rendering and implement the full OpenGL ES 2.0 specification.
  • Reduced memory footprint – PowerVR GX5300 supports PVRTC, a texture compression format which reduces memory bandwidth and decreases power consumption. It can help silicon vendors reduce memory costs.

Typical applications will be embedded Linux or Android-based connected home systems that require graphics rendering such as smart washing machines, and wearables running Android Wear such as smartwatches.

PowerVR GX5300 is available for licensing now, but it has not been announced in any wearable SoCs just yet, so it’s probably something we’ll see in products in 2015.

AllWinner V10 and V15 SoCs Target Video Recording Applications

July 9th, 2014 1 comment

AllWinner A-series that can be found in tablets and media players are pretty well known, but AllWinner also has V-Series processors with V10 and V15. A first glance, AllWinner V10 is quite similar to AllWinner A31 with a quad core Cortex A7 CPU coupled with a PowerVR SGX544MP2 GPU, and AllWinner V15 has the same CPU/GPU combo as AllWinner A10 (CortexA8/Mali-400). But AllWinner V-Series are actually video encoders targeting applications such as IP cameras, car DVRs, and sports digital video cameras thanks to features such as motion detection, video scaling, and digital watermarking.

AllWinner V10 Block Diagram

AllWinner V10 Block Diagram

Let’s go through AllWinner V10 specifications, and I’ll mark differences with AllWinner A31, or features not mentioned in A31 specs, in bold:

  • CPU – Quad-core ARM Cortex-A7 with· 256KB L1 cache, 1MB L2 cache
  • GPU – PowerVR SGX544MP2 compliant with OpenCL 1.1 EP and delivering up to 20GFLOPS.
  • Memory – 32-bit DDR3/LPDDR2 SDRAM controller, supporting up to 2GB; NAND I/F
  • Video
    • Supports H.264 High Profile [email protected] video encoding
    • Digital watermarking
    • Motion detection
    • CBR/VBR bit rate control mode
    • Supports [email protected] video decoding
    • Supports multi-format video decoding including MPEG 1/2/4, H.264, VP8, AVS,VC-1, etc.
    • Supports independent encoding and decoding
    • 1/16 ~ 16x scaling
  • Video Input/Output
    • Supports 12-bit parallel CSI and 4-lane MIPI CSI
    • Supports up to 12M CMOS sensor
    • Supports one video layer and two graphic layers
    • Supports scaling up to 4K x 4K
  • HawkView ISP
    • Auto exposure/focus/white balance (AE/AF/AWB)
    • Dynamic range control (DRC)
    • Color enhancement
    • Noise reduction
  • Audio Codec
    • Integrated Hi-Fi 100dB audio codec
    • Three integrated differential analog mic amplifiers for headset and phone
    • One digital mic interface with software noise cancellation
  • Peripherals
    • 3 x USB ports
    • 4 x SD card 3.0
    • RTP/CTP
  • Package – BGA609, 18mm x 18mm, 0.65 pitch

AllWinner V10 also appears to be lacking 3840×1080 3D decoding ability found in A31, and may not have a dual band RAM interface, and no support for LPDDR3 memory. I’m not sure if A31 also supports independent encoding and decoding, or that would means Skype or Google Hangout calls are partially handled by software. AllWinner provides support for Android and Linux operating systems for the V10 and V15 processor, specifically Android 4.4 for V10. AllWinner V15 has similar features as V10 but only comes with a single Cortex A8 core, a Mali-400 GPU, supports 1080p decoding, 720p encoding, and features less peripherals. It’s also smaller with a BGA336 (14mm x 14mm) package.

I could not find any development boards, nor products based on AllWinner V10 and V15. There may be some, but the processors are seldom advertised in devices like digital cameras, and digital video recorders. I’ve asked some details to AllWinner, and I’ll update this post if I get an answer.

You can may find more information in AllWinner V10 and V15 on their respective product pages.

Ineda Systems Dhanush WPU is a MIPS based SoC Specifically Designed for Wearables

June 5th, 2014 No comments

What’s a WPU? It stands for Wearable Processor Unit, and as you may guess it’s a processor specifically designed to be used in wearables such as smartwatches or fitness trackers.  Currently many wearables are based on application processors that are used in smartphones (e.g. Galaxy Gear), and lower-end versions are based on standard low power MCUs (e.g. Pebble), but none of them are actually based on SoC specifically designed for wearables, and analysts are asserting that new types of SoC are definitely needed if companies are to provide wearables with the battery life and features consumers want. Ineda Systems Dhanush WPU is not the first Wearable SoC announced, as for instance AllWinner mentioned their WX quad core SoC for Wearables should become available in Q4 2014 in their roadmap, and Mediatek vaguely unveiled their Aster SoC at CES 2014, but it’s the first that I know of where we’ve got most of the details announced.

Dhanush WPU Block Diagram

Dhanush “Advanced” WPU Block Diagram

Now that block diagram looks interesting… In order to achieve maximum battery life, Ineda has adopted a sort of “big.LITTLE processing” concept to wearables which they call Hierarchical Computing Architecture (HCA) with up to 3 cores offering three levels of performance and power consumption: MIPS microAptiv (always on for sensors, ultra-low power), MIPS microAptive (low power), and MIPS interAptive application processor.

Dhanush SoCs actually comes in four flavor with only one core, 2-level HCA or 3-level HCA:

HCA Power / Features, and Speech Processing Example

HCA Power / Features, and Speech Processing Example

  • Dhanush Nano
    • microAptiv MCU
    • Memory – On-chip SRAM
    • For werable devices that require MCU class of compute and memory footprint such as smartbands
  • Dhanush Micro (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM
    • Typical application would be a Linux based or RTOS based smartwatch.
  • Dhanush Optima (2-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Memory – On-chip SRAM + LPDDR2
    • For Linux based smartwatches requiring more features
  • Dhanush Advanced (3-level HCA)
    • Ultra low power, always-on microAptiv MCU for sensors
    • “high performance” low power microAptiv MCU
    • Dual-core, multi-threaded interAptiv CPU
    • Multimedia – PowerVR GPU and VPU for video encode/decode
    • Memory – On-chip SRAM + LPDDR2
    • For more advanced, high-end wearables that require high resolution rendering, handle complex image/video processing via GPU compute and also support low power video recording and playback. Typical applications would be a Android smartwatches or smart glasses.

Ineda Systems can provide two SHASTRA development kit:

  • SHASTRA-A for Dhanush Advanced (INCDHAD1) which can also be used to evaluate Dhanush Optima
  • SHASTRA-M for Dhanush Micro (INCDHMC1) which can also be used to evaluate Dhanush Nano

SHASTRA-A Development Board

The boards come with a software development kit (SDK) including a unified development environment (OS, Drivers, Services, APIs, Sample Applications), integrated resource & power management, a GUI framework, user guides, tools & build utilities and power profiling tools. There are two variants of SHASTRA SDK, one for evaluation, and one for product development.

Dhanush Advanced (INCDHAD1) and Micro (INCDHMC1) are now sampling for early customers. Production status of Nano and Optima versions are not been disclosed. I’d guess that means actual products may retail by the end of the year at the earliest. You can find more information on Ineda Systems’ Dhanush WPU page, as well as Imagination Technologies Blog.

Cavium ThunderX Server SoC Features up to 48 ARM 64-bit Cores

June 4th, 2014 5 comments

ARM SBSA specification for server supports up to 268,435,456 CPU cores for the second level of standardization on one or a combination of SoCs. We’re not quite up there just yet, but Cavium ThunderX is an ARM server SoC with up to 48 cores on a single chip, which is the highest number of cores I’ve ever heard of in an ARM SoC.

Cavium Thunder X Block Diagram

Simplified Cavium ThunderX Block Diagram

The company created their own custom processor cores using an ARMv8 architecture license, designing an SoC complies with ARM’s Server Base System Architecture (SBSA) standard with the following key features:

  • ARM based SoC that scales up from 8 to 48 cores with up to 2.5 GHz core frequency with 78K I-Cache, 32K D-Cache, and 16MB L2 cache.
  • Fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI)
  • Integrated I/O capacity with 100s of Gigabits of I/O bandwidth
  • 4x DDR3/4 72-bit memory controllers supporting up to 1TB RAM @ 2400 MHz in a dual socket configuration
  • Hundreds of integrated hardware accelerators for security, storage, networking and virtualization applications.
  • Cavium virtSOC technology allowing full system virtualization for low latency from virtual machine to I/O.
  • Best in class performance per watt and performance per dollar for the target applications

ThunderX processor family is comprised of several models depending on target applications: Compute, Storage, Secure Compute, and Networking as well as server chips (CN88XX_X)with 24 to 48 cores, and low-end server chips (CN87XX_X) with 8 to 16 cores.

The server chips are available in 4 SKU families:

  • ThunderX_CP (Compute)
    • Up to 48 cores along with integrated virtSOC, dual socket coherency, multiple 10/40 GbE and high memory bandwidth.
    • Optimized for private and public cloud web servers, content delivery, web caching, search and social media workloads.
  • ThunderX_ST (Storage)

    • Up to 48 cores along with integrated virtSOC, multiple SATAv3 controllers, 10/40 GbE & PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes hardware accelerators for data protection/ integrity/security, user to user efficient data movement (RoCE) and compressed storage.
    • Optimized for Hadoop, block & object storage, distributed file storage and hot/warm/cold storage type workloads.
  • Thunder_SC (Secure Compute)

    • Up to 48 cores along with integrated virtSOC, 10/40 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric for east-west as well as north-south traffic connectivity.
    • Includes Cavium’s 4th generation NITROX and TurboDPI technology with acceleration for IPSec, SSL, Anti-virus, Anti-malware, firewall and DPI.
    • Optimized for Secure Web front-end, security appliances and Cloud RAN type workloads.
  • Thunder_NT (Networking)

    • Up to 48 cores along with integrated virtSOC, 10/40/100 GbE connectivity, multiple PCIe Gen3 ports, high memory bandwidth, dual socket coherency, and scalable fabric with feature rich capabilities for bandwidth provisioning , QoS, traffic Shaping and tunnel termination.
    • Hardware accelerators include high packet throughput processing, network virtualization and data monitoring.
    • Optimized for media servers, scale-out embedded applications and NFV (Network Functions Virtualization) type workloads.

The cost and power optimized ThunderX CN87xx family with 8 to 16 cores will be available in single socket configuration with two DDR3/4 controllers, multiple 10GbE, SATAv3 and PCIe Gen3 interfaces. It will be used for cold storage, distributed content delivery, dedicated hosting, distributed memory caching and embedded and control plane.

Cavium has partnered with several companies, including ODM and OEM partners such as GIGABYTE and Hewlett Packard, is part of Linaro, the Linux Foundation, OpenStack, UEFI, Xen, etc.. industry groups.  Supported operating systems include Canonical’s Ubuntu, RedHat’s Fedora,  MontaVista Linux and openSUSE.  Oracale Java, OpenJDK and GNU toolchain have been ported to the platform, as well as KVM and Xen virtualization platforms.

The company expects ThunderX processors and hardware reference platforms to be available in Q4 2014. Further details may be available on Cavium’s ThunderX page.

Via EETimes

[Update: Here’s the pic of the dual socket board (96 cores: 48 + 48) via There’s also a single socket version. They all require an heatsink as shown in the bottom left corner of the pi (red/orange heatsink]

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)

Cavium ThunderX Dual Socket Motherboard (Click to Enlarge)