Archive

Posts Tagged ‘xilinx’

EU funded AXIOM Board is Powered by Xilinx Zynq UltraScale+ FPGA + ARM SoC

February 17th, 2017 3 comments

Back in 2015, Xilinx unveiled Zynq Ultrascale+ MPSoC combining ARM Cortex A53 & Cortex R5 cores, a Mali-400MP2 GPU, and UltraScale FPGA, and the company recently launched ZCU102 Evaluation Kit based on the SoC, which sells for just under $3,000. But if you are based in the European Union, you’ll be glad to learn about 4 millions Euros of your taxes have been spent to design a board based on the same MPSoC family as part of the AXIOM project, which was developed in collaboration with European universities and companies with the “aim of researching new software/hardware architectures for Cyber-Physical Systems (CPS) to meet the expectations” in terms of computational power, energy efficiency, scalability through modularity, easy programmability, and leverage of the best existing standards at minimal costs.

AXIOM (Agile, eXtensible, fast I/O Module) board’s key specifications:

  • SoC – Xilinx Zynq Ultrascale+ ZU9EG MPSoC with four ARM Cortex A53 cores @ 1.2GHz, two Cortex R5 “real-time” cores @ 500MHz, a Mali-400MP GPU @ 600 GHz, 600K System Logic Cells;
  • System Memory – 32 GB of swappable SO-DIMM RAM  (up to 32GB) for the Processing System, plus a soldered 1 GB Programmable Logic.
  • Storage – 8 GB eMMC flash (PCN layout supports up to 32GB), and a micro SD card reader.
  • Display – miniDP connector, single channel 24-bit LVDS interface, touch panel connector
  • Connectivity – Gigabit Ethernet port (RJ45)
  • USB – 4x USB Type C ports, 2x USB Type A ports
  • Expansion
    • Arduino UNO headers
    • 12x GTH transceivers @ 12.5 Gbps  (8 on USB Type C connectors + 4 on HS connector)

There’s also mention of an Axiom Link interface that would allow to interconnect multiple AXIOM boards in order to arrange small clusters.

Since it’s a public project I would have expected it to be open source. While there are some deliverables available for download, they appear to be outdated with “the technical specification of AXIOM board” PDF mentioning only AXIOM-15 and AXIOM-35 boards based on the previous Xilinx Zynq-7000 series SoCs. We can also find links to a Wiki, as well as git and svn repository, but all those are in a private area that requires a login, and as far as I could tell, it’s not possible to register. So maybe the EU commission wants to protect its investment, or we just need to be a little more patient. [Update: This Download page  seems to have more public info available]

Click to Enlarge

The AXIOM Board is said to combine features required for High-Performance Computing, Embedded Computing and Cyber-Physical Systems, with typical applications including real-time data analysis of a huge amount of data, machine learning, neural networks, server farms, bitcoin miners, and so on.

It’s unclear when/if the board will be available for sale, and at what price.

Via Board DB and Single Board Computers G+ community.

NovaVGA Shield Adds VGA Output to Arduino Boards

January 30th, 2017 2 comments

Arduino boards are convenient to control I/Os, link LEDs, and display info on small LCD displays, but if you want to output data to a larger monitor, it’s a bit more complex. NovaVGA shield for Arduino simplify the task of outputting data to a VGA monitor over SPI.

NovaVGA shield hardware specifications:

  • CPLD – Xilinx XC9572XL CPLD, user programmable via JTAG interface.
  • SRAM Framebuffer – 160×120 pixels @ 6-bit color (2^6 = 64 possible colors)
  • VGA Output – 640×480 @ 60Hz physical resolution (25.175MHz pixel clock)
  • Interface with MCU – SPI mode 1 interface (consumes only three Arduino pins)
  • Header pins not included

MicroNova provides an Arduino library with various examples such as color palette, Mandelbrot, Tetris and text console, as well as a user’s guide and PDF schematics that can all be downloaded directly on the product page.

NovaVGA shield sells for $29 on Tindie or directly on MicroNova store. Note that it’s not the first board of this kind, as Olimex MOD-VGA, based on GameDuino design, has been available for several years.

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

July 12th, 2016 5 comments

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself.

Freedom U500 Block Diagram

Freedom U500 Block Diagram

But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller.

Freedom U500 (Unleashed family) platform key specifications:

  • U5 Coreplex with 1 to 8 U54 cores @ 1.6GHz+
  • RV64GC Architecture (64- bit RISC-V)
  • Multicore, Cache Coherency Support
  • High Speed Peripherals: PCIe 3.0, USB3.0, GbE, DDR3/4
  • TSMC 28nm

The SoC supports Linux, and targets applications such as machine learning, storage, and networking.

Freedom E300 Block Diagram

Freedom E300 Block Diagram

Freedom E300 (Everywhere family) platform key specifications:

  • E3 Coreplex
  • RV32IMC/RV32EMC Architecture
  • On chip Flash, OTP, SRAM
  • TSMC 180nm

Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.

Open source SoCs are made to be customizable to match your applications exact needs, instead of picking on existing SoC matching your requirements but with some uneeded features. SiFive also explains that “storage customers talks about custom instructions for bit manipulation so they can use one not 10 instructions for 10x speed up”. But before you get to Silicon, you’d normally ruin and customize the core on FPGA boards and three boards are currently available for development and evaluation:

  • Freedom U500:
  • Freedom E300 – Digilent Arty FPGA development kit powered by Xilinx XC7A35T-L1CSG324I FPGA, with 256 MB RAM, 16 MB flash, and vairous expension ports. Price: $99
Click to Enlarge

Xilinx Virtex-7 FPGA VC707 devkit – Click to Enlarge

You also have detailed documentation about the SoCs, U5 nd U3 coreplex, the development kits, software and tools, as well as developer forums, on SiFive developers website. You can also directly checkout the code and SDK on github.

RISC-V instructions set is royalty-free, so compared to the entry level $40,000 ARM license for startups using Cortex M0 MCU, it should provide some savings. It does not help with manufacturing costs which should remain the same. but SiFive expects that open source SoC could be manufactured through a “moderate” crowdfunding campaign.  I have not been able to figure out SiFive business model yet, unless they plan on selling their own chips too, and/or provide customization services to customers.

Lots more information can be found on Sifive website.

Via EETimes

OpenAMP Open Source Framework Provides the Glue between Linux, RTOS, and Bare Metal Apps in Heterogeneous SoCs

January 27th, 2016 No comments

SoCs becoming more complex, and go beyond homogeneous multicore systems by mixing different type of cores such as high performance cores, low power real-time cores, or even FPGA fabric. Examples include NXP i.MX6 SoloX with an ARM Cortex A9 core for Linux apps, and an ARM Cortex M4 core for real-time tasks, or Xilinx Zynq UltraScale+ MPSoC with Cortex A53 core for higher level apps, Cortex R5 cores for real-time processing, and Ultrascale FPGA logic. All these different cores are running their own Linux based OS, real-time operating system or bare metal application, and all this makes software development an even greater difficult tasks. In order to reduce the complexity, and address some of the issues, the Multicore Association has launched a new working group targeting the management, expansion, and standardization of  OpenAMP (Open Asymmetric Multi Processing), an open source framework that allows operating systems to interact within a broad range of complex homogeneous and heterogeneous architectures and allows asymmetric multiprocessing applications to leverage parallelism offered by the multicore configuration”.

OpenAMP_ArchitectureKey features and benefits of OpenAMP listed by the association:

  • Configure, deploy, and manage multiple OS’s across homogeneous and heterogeneous cores
  • Availability of open source Linux implementations and proprietary RTOS and bare metal implementations
  • Android OS compatibility
  • Inter-OS & inter-processor communication
  • Shared memory protocol – Virtio/rpmsg
  • Lifecycle APIs – remoteproc
  • Proxy technologies emulate Linux processes
  • Compatibility with MCAPI to support high-performance use cases and zero-copy
  • Standardizes OS interaction between Linux and RTOS/bare-metal

Some RTOS support has already been implemented by FreeRTOS, Mentor, Micrium, NXP, Xilinx, and an open source implementation, as well as corresponding documentation, can be found on OpenAMP github repository.You can find out more on OpenAMP page, the mailing list, and the first 2-hour developer meeting that will take place later today (January 27, 2016) at 9:00 pm Pacific Standard Time, and go through OpenAMP governance, the working group goals, current OpenAMP capabilities, and issues, as well as time for an open discussion on architectural proposals.

Digilent ARTY is a $99 Xilinx Artix-7 FPGA Board with Arduino Headers

October 2nd, 2015 1 comment

Low cost FPGA boards with Arduino headers are nothing new, as we’ve seen before with Arduissimo and Papilio DUO, but both of these boards are based on Spartan 6 FPGA, while the recent Digilent ARTY board is powered by an Artix-7 FPGA. Beside the hardware differences, Spartan 6 FPGAs only support Xilinx ISE Design Suite, while Artix-7 parts are also supported by Vivado Design Suite, which according to Xilinx has a much better workflow and user interface.

Digilent_ARTYDigilent ARTY specifications:

  • FPGA – Xilinx XC7A35T-L1CSG324I with 33,280 logic cells, 1,800 Kb block RAM, 90 DSP slices, and 250 I/O pins
  • System memory – 256 MB DDR3L SDRAM
  • Storage – 16 MB of QSPI Flash
  • Connectivity – 10/100M Ethernet
  • Expansion interfaces
    • 4 Digilent compatible Pmod interfaces enabling 32 user I/O pins: 2 Pmods routed as differential pairs, paired to fit dual-wide Pmods
    • Arduino UNO R3 shield / chipKit interface
  • Debugging – USB-UART Interface, JTAG Programming/Configuration Port
  • Misc – 4x user RGB LEDs, 4x user LEDs, 4x user slide switches, 4x user push button switches
  • Power Supply – 7-15V input via DC jack or headers, 5V via micro USB port
  • Dimensions – N/A
ARTY Block Diagram

ARTY Block Diagram

Vivado Design Suite comes with various editions, starting from the free WebPACK Edition with limited features to the System Edition with the complete integration and verification feature set selling for close to $5,000. According to the product brief, ARTY evaluation kit includes the Design Edition, locked to XC7A35T device, and valued at $2,995.

However, ARTY development board / evaluation kit sells for just $99 on Digilent or Avnet. Technical documentation and design resources can be found on Arty Resource Center.

Xilinx Introduces Zynq UltraScale+ MPSoC with Cortex A53 & R5 Cores, Ultrascale FPGA

March 5th, 2015 2 comments

Xilinx Zynq-7000 dual core Cortex A9 + FPGA SoC family was announced in 2012, and provides a wide range of SoC with features and price range, and led to low cost ARM + FPGA such as ZedBoard, and more recently Parallela and MYiR Z-Turn boards. The company unveiled its successor with Zynq UltraScale+ MPSoC providing five times more performance per watt, with four ARM Cortex A53 cores, two ARM Cortex R5 real-time MCU cores, a Mali-400MP GPU, an UltraScale FPGA fabric manufactured with 16nm FinFET+ process.

Zynq_Ultrascale+_MPSoCThere are two main sub-families in Zynq Ultrascale+ MPSoC for “smarter control & vision”, and “smarter network”. Both share the same processing systems (CPU, GPU, MCU, Peripherals, Security), but the networking family has beefier FPGAs,  and lacks the H.264/H.265 video processing unit found in the control & vision version:

  • Processing Systems
    • Processor – Quad ARM Cortex A53 MPCore up to 1.3GHz
    • Real-time Processor – Dual ARM Cortex-R5 MPCore up to 600MHz
    • GPU – Mali-400MP2 up to 466MHz
    • External Memory I/F – DDR4, LPDDR4, DDR3, DDR3L, LPDDR3, 2x Quad-SPI, NAND
    • High-Speed Connectivity – 2x USB3.0, SATA 3.0, DisplayPort, 4x Tri-mode Gigabit Ethernet, PCIe Gen2x4
    • General Connectivity – 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
    • Security – AES, RSA, and SHA
    • AMS System Monitor – 10-bit, 1 MSPS– Temperature, Voltage, and Current Monitor
  • Programmable Logic
    • FPGA
      • Control & Vision (C&V) – Up to 485K Effective LEs, 405K Logic Cells, 1,728 DSP Slices, 6.2 Mb distributed RAM,  11.2 Mb BlockRAM, 27 Mb UltraRAM
      • Networking (N) – Up to 1,095K Effective LEs, 920K Logic Cells, 3,528 DSP Slices, 11 Mb distributed RAM,  34.6 Mb BlockRAM, 36 Mb UltraRAM
    • PCI Express Interface – Gen4 x8;  Gen3 x16
    • 1x Video Codec Unit (C&V only) – H.264/H.265 up to 4Kx2Kp60 or 8Kx4Kp15
    • Serial Transceiver – C&V: 28 up to 16 Gb/s; N: 76 up to 33 Gb/s
    • Analog Mixed Signal (AMS) – System Monitor—10-bit, 1 MSPS ADCs with 17 Differential Inputs, Power supply line voltage monitoring & JTAG, PMBUS, I2C support

The processing systems and programmable logic are interfaced via 128-bit AMBA AXI4 interfaces.

Zqnq_Ultrascale_Plus_BLock_Diagram

Zynq UltraScale+ MPSoC Block Diagram (Click to Enlarge)

There are 5 parts for Control and Vision (XCZU2, XCZU3, XCZU4, XCZU5, and XCZU7), and 6 parts (XCZU6, XCZU9, XCZU11, XCZU15, XCZU1 and XCZU19) for Network, and even more if you include different packaging options. SKU details and nomenclature can be found in the product selection guide.

The Cortex A53 cores will run Linux, Cortex R5 cores FreeRTOS, and design tools include Vivado Design Suite, Xilinx SDK, and PetaLinux SDK. Zynq UltraScale+ MPSoCs can be used for connected control/machine-to-machine applications for manufacturing, 2D/3D vision application (video-processing, object detection…), wired and wireless networking, and data centers.

I could not find any availability information from Xilinx, but LinuxGizmos reports that “early access to the UltraScale+ processors starts in the second quarter, with samples coming later this year, and volume production due in 2016”.

Visit Xilinx Zynq UltraScale+ MPSoC page for more information.

PicoZed System-on-Modules are Powered by Xilinx Zynq-7000 ARM + FPGA SoC

September 10th, 2014 1 comment

After the Zedboard, and the Microzed, here comes PicoZed, a family of system-on-modules (SoM) based on Xilinx Zynq-7000 SoCs featuring a dual core Cortex A9 processor and FPGA fabric. The module also comes with 1GB RAM, 4GB eMMC, Gigabit Ethernet PHY, various user I/O, and more. Target applications include embedded vision, test & measurement, motor control, software-defined radio, and industrial automation.

PicoZed 7303 SoM (Click to Enlarge)

PicoZed 7030 SoM (Click to Enlarge)

Four modules are available with support for commercial or industrial temperature ranges, all sharing the following specifications:

  • SoC (depending on module)
    • Xilinx Zynq-7010 with two Cortex-A9 cores @  866MHz, FPGA with 28K Logic Cells
    • Xilinx Zynq-7015 with two Cortex-A9 cores @  866MHz, FPGA with 74K Logic Cells, 4 transceivers @ 6.25 Gb/s
    • Xilinx Zynq-7020 with two Cortex-A9 cores @  866MHz, FPGA with 85K Logic Cells
    • Xilinx Zynq-7030 with two Cortex-A9 cores @  1GHz, FPGA with 125K Logic Cells, up to 4 transceivers @ 12.5 Gb/s
  • System Memory – 1GB DDR3 SDRAM
  • Storage – 4GB eMMC flash, 128Mb QSPI flash
  • Connectivity – Gigabit Ethernet PHY
  • PicoZed Block Diagram (Click to Enlarge)

    PicoZed Block Diagram (Click to Enlarge)

  • USB – USB 2.0 PHY
  • User I/O via three board-to-board connectors (JX3):
    • 7Z010 Version:
      • 113 User I/O (100 PL, 13 PS MIO)
      • PL I/O configurable as up to 48 LVDS pairs or 100 single-ended I/O
    • 7Z015 Version:
      • 148 User I/O (135 PL, 13 PS MIO)
      • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O
      • 4 GTP transceivers
    • 7Z020 Version:
      • 138 User I/O (125 PL, 13 PS MIO)
      • PL I/O configurable as up to 60 LVDS pairs or 125 single-ended I/O
    • 7Z030 Version:
      • 148 User I/O (135 PL, 13 PS MIO)
      • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O
      • 4 GTX transceivers
  • Debugging – JTAG configuration port accessible via I/O connectors, PS JTAG pins accessible via I/O connectors
  • Misc – Oscillator @ 33.33 MHz
PicoZed 7030 Back (Click to Enlarge)

PicoZed 7030 Back (Click to Enlarge)

The module comes with a getting started card, and the company provides a Linux BSP, as well as reference design files.

To ease development, PicoZed Carrier Board is also available with the following specifications:

  • SoC/Memory/Storage – Via PicoZed modules listed above
  • External Storage — MicroSD slot
  • Connectivity – 2x Gigabit Ethernet ports, SFP+ cage
  • Video Output – HDMI
  • USB – USB 2.0 port, USB UART
  • Other I/O
    • SMA port for GTX/GTP
    • JTAG port
    • Programmable clock mux
    • SMA reference clock input
    • User I/O:
      • FMC (Low Pin Count)
      • PS Pmod (Shared with eMMC)
      • PL Pmod (7015/20/30 only)
      • PL Pmod (7015/30 only)
  • Expansion – 1x PCIe Gen 2
  • Misc – User push buttons and LEDs
  • Power – 12V
PicoZed Carrier Board (Click to Enlarge)

PicoZed Carrier Board (Click to Enlarge)

This baseboard comes with a 12V AC/DC power support, and a quick start card.

PicoZed SoMs and Carrier Board are available now on Avnet with lead times between 8 to 10 weeks. The SoM prices vary between $179 and $399 depending on chosen Zynq SoC and temperature range, and PicoZed Carrier Board can be purchased for $425. You can find more details on PicoZed SoM and PicoZed Carrier Board pages. The board will be demonstrated at X-Fest seminars in Europe, Asia, and North America.

Via LinuxGizmos

Adapteva Announces Three Parallella Fanless Boards for Microserver, Desktop, and Embedded Applications

July 15th, 2014 6 comments

Adapteva’s Parallella low cost open source hardware “supercomputer” is a board powered by Xilinx Zynq-7010/7020 dual core Cortex A9 + FPGA SoC and the company’s Ephipany epiphany coprocessor, that’s had a successful Kickstarter campaign in 2012 as the 16-core version sold for just $99, and is capable of handling applications such as image and video processing, and ray-tracing, and also comes with an OpenCL SDK. The board was fairly difficult to source after the crowdfunding campaign, and one the common complain of backers was the board had to be actively cooled by a fan. The company has fixed both issues by increasing slightly the price, and redesigning the board so that it can be passively cooled by a larger heatsink.

Parallela Desktop Board

Parallella Desktop Board with Heatsink

There are now three versions of the parallela board:

  • Parallella Microserver ($119) – Used as an Ethernet connected headless server
  • Parallella Desktop ($149) – Used as a  personal computer
  • Parallella Embedded ($249) – Used for “leading edge” embedded system

Here are the simplified specs of the boards:

  • SoC
    • Microserver and Desktop – Xilinx Zynq Z7010 dual-Core ARM Cortex A9 with 512KB L2 Shared Cache + Artix-7 FPGA with 28K logic cells
    • Embedded – Xilinx Zynq Z7020 dual-Core ARM Cortex A9 with 512KB L2 Shared Cache + Artix-7 FPGA with 85K logic cells
  • Coprocessor – 16-core Epiphany-III processor
  • System Memory – 1GB DDR3
  • Storage – micro SD slot + 128Mb quad SPI flash
  • Connectivity – 10/100/100M Ethernet
  • Video Output – 1x micro HDMI (Desktop and Embedded only)
  • USB – 1x micro USB host port  (Desktop and Embedded only)
  • Expansion I/O
    • Microserver – N/A
    • Desktop – 2 eLinks (Ephiphany Links) + 24 GPIO pins
    • Embedded – 2 eLinks + 48 GPIO pins
  • Dimensions – 86.36mm x 53.34mm
Parallela Embedded

Parallela Embedded

The board will sell with the heatsink and a power adapter. If you have one of the boards from the Kickstarter campaign,  or boards purchased before the 10th of July, you can’t go fanless by just replacing the fan by the new heatsink, as it won’t fit.

Parallella-16 Desktop computer is available now for $149 on Adapteva shop, and in a couple of days, it will be on Amazon US. The Microserver and Embedded versions will be available in a few weeks. You can read the announcement on the company website, where you’ll also find some interesting projects (videos) that have been done so far by the community of developers.