$5 Tang Nano FPGA Board Features GOWIN GW1N “LittleBee” FPGA

Last year, we wrote about Lichee Tang FPGA board powered by Anlogic EG4S20 FPGA and targeting RISC-V development for just under $15.

The company, now called Sipeed, has made an even cheaper FPGA board with Tang Nano equipped with GOWIN Semi GW1N FPGA part of the company’s LittleBee family.

Sipeed Tang Nano

Sipeed Tang Nano FPGA Board
Click to Enlarge

Sipeed Tang Nano specifications:

  • FPGA – Gowin GW1N-1-LV FPGA with 1,152 LUT4, 864 Flip-Flops(FF), 72Kbit Block SRAM, 4x B-SRAM, 96Kbit user flash, 1x PLL, 4x I/O banks
  • System Memory – 64Mbit (8MB) 3.3V PSRAM
  • Display – Standard 40-pin RGB LCD interface with on-board screen backlight driver circuit (default normally open, EN pin can be connected to FPGA)
  • USB – USB Type-C port for download and power supply
  • Expansion – 34 I/O ports and power pins on headers (unpopulated), breadboard-compatible
  • Misc – RGB LED, 2x user buttons, 24MHz crystal oscillator
  • Power Supply – 5V via USB-C port (at least 400 mA)
  • Dimensions –  58.4 x 21.3 x 4.8 mm
Sipeed Tang Nano RGB Display
Tan Nano Connected to RGB LCD Display – Click to Enlarge

Everything is done through a USB-C cable with which the board is powered, and you can power download the bitstream. Programming can be done with GOWIN IDE available for Windows and Linux. There’s a Wiki with more information, but note that for now the English section is empty, and all info is on the Chinese version. Browsing that directory will bring you to more hardware documentation and the schematics, as well as (soon) more details about the software.

If you’d like to purchase the board, you can do so via Taobao, or a third-party Taobao forwarder if you are outside of china, where it is sold for 34.90 RMB ($4.9 US), or up to 132 RMB (~$18) with a 5″ color display.

GOWIN GW1N FPGA

GOWIN GW1N FPGA
Click to Enlarge

The directory also contains the datasheet of GOWIN GW1N FPGA in both English and Chinese, where we can find the main features of the tiny, low-cost FPGA:

  • User Flash
    • GW1N-1, GW1N-1S – 100,000 write cycles,  > 10-year data retention at +85 °C, selectable 8/16/32 bits data-in and data-out, 256 bytes page size: 256 bytes, 3 μA standby current, page write time: 8.2 ms
    • GW1N-2/2B/4/4B/6/9) – Up to 608Kbits, 10,000 write cycles
  • Low power consumption
    • 55 nm embedded flash technology
    • LV: supports 1.2 V core voltage
    • UV: supports same power supply for VCC / VCCO / VCCx – Note: GW1N-1 and GW1N-1S devices do not support UV version, the other devices
      support both.
    • Clock dynamically turns on and off
  • Multiple I/O Standards
    • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I,
      SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI,
      LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew rate option
    • Output drive strength option
    • Individual bus keeper, weak pull-up, weak pull-down, and open
      drain option
    • Hot socket
    • I/Os in the top layer of GW1N-1S and GW1N-6/9 devices support MIPI input
    • I/Os in the bottom layer of GW1N-6/9 devices support MIPI output
    • I/Os in the Top layer and Bottom layer of GW1N-6/9 devices support I3C OpenDrain/PushPull conversion
  • High-performance DSP
    • High-performance digital signal processing ability
    • Supports 9 x 9,18 x 18,36 x 36 bits multiplier and 54 bits
      accumulator;
    • Multipliers cascading
    • Registers’ pipeline and bypass
    • Adaptive filtering through signal feedback
    • Supports barrel shifter
  • Abundant slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shift register and distributed register
  • Block SRAM with multiple modes
    • Supports dual port, single port, and semi-dual port
    • Supports bytes write enable
  • Flexible PLLs+DLLs – Frequency adjustment (multiply and division) and phase
    adjustment;  Supports global clock
  • Built-in flash programming – Instant-on; supports security bit operation; supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • GW1N-2B and GW1N-4B devices support JTAG transparent
      transmission
    • Offers up to six GowinCONFIG configuration modes: AUTOBOOT,
      SSPI, MSPI, CPU, SERIAL, DUAL BOOT

As you can see in the table below, GW1N-1 used in Tang Nano board only supports some of the features and is one of the entry-level members of the family.

GOWIN GW1N FPGA FamilyYou’ll find more by checking out the datasheet.

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dgpJean-Luc Aufranc (CNXSoft)Icenowy ZhengBoriszoobab Recent comment authors
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DurandA
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I saw some discussion on twitter about adding GOWIN FPGAs support to SymbiFlow (open source FPGA toolchain). I don’t know if there is some recent progress, but having dirt-cheap FPGAs would certainly help for education and hobbyists.

zoobab
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Downloading their SDK is super damn slow. Is it hosted behind the great firewall of China?

zoobab
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dgp
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dgp

An open toolchain for these off brand FPGAs would be killer. I’d like to see some small (QFN) packaged parts with enough gates for one of the small RISC-V cores, a bit more block ram and some analogue blocks.

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dgp
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dgp

The anlogic parts are interesting but they only go down to 88 QFN AFAIK and they seem to be hard to get now and they are all discontinued at lcsc.

The gowin GW1NS with built in Cortex M3 seems to be pretty close to what I want. 🙂

zoobab
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Boris
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“System Memory – 64Mbit (8MB) 3.3V PSRAM”

According to the Gowin data only GW1NR Family has Embedded 64 Mb pSRAM !

It is not available on GW1N-1 used on Sipeed Tang Nano.

Icenowy Zheng
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Icenowy Zheng

The SOIC-8 chip is the PSRAM. The flash is embedded instead.