Sony Spresense 6-core MCU Development Board Now Supports Java

Sony Spresense board was introduced in spring 2018 with a 6-core Cortex-M4 microcontroller from the company, GPS & GLONASS, as well as audio support.

The breadboard-compatible board could also be inserted into an Arduino UNO R3 compatible base board, and Sony offered support for both the Arduino IDE and a C-based NuttX-based SDK. You’ll find some more details and photos in our “review”.

Sony Spresense Java (MicroEJ VEE)
Click to Enlarge

Sony has now partnered with MicroEJ to provide developers with Java support on Spresense board through MicroEJ Virtual Execution Environment (VEE). A Java simulator (VEE Virtual Device) allows you to develop software for Spresense independently of the hardware.

Beside plenty of libraries, MicroEJ VEE features MEJ32 32-bit virtual core is compatible with various architectures including ARM Cortex-M, ARM Cortex-Ax, RX, V85, MIPS32, TriCore, and Tensilica. Java enables application portability which means that any GUI/IoT/Security or application code can run on various embedded systems supported by MicroEJ VEE.

There are three main tools for developers:

  • MicroEJ SDK to enable manufacturers to build MicroEJ-ready devices.
  • MicroEJ Studio to develop applications for MicroEJ-ready devices.
  • MicroEJ Store to publish applications and share them with the MicroEJ community.

MicroEJ Studio

If you’d like to try it out you could follow one of the guides on the developer website, and/or check out the Weather station demo based on the Spresense hardware.

If you don’t own a Sony Spresense, MicroEJ VEE has reference implementations on other popular development boards including Espressif ESP32-WROVER-KIT V3, NXP FRDM-KL46Z freedom platform, or STMicro STM32F746-DISCO board.

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David Willmore
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David Willmore

18 months later and they’re still trying to lure people to their devices? 6x Cortex-M4? Did someone from the Cell processor division get lost?

dgp
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dgp

>18 months later and they’re still trying to lure people to their devices?

TBH I think this was designed for in-house projects and they’re trying to see if there is a market for it.
They need to half the price of the boards to make it attractive to makers though.

>6x Cortex-M4?

If there was some memory mapping/protection logic between the cores and the SRAM that couldn’t be disabled after hitting the secure switch you would have some really well isolated “trust zones” which are interesting for our “put everything on the internet” world. Alas I think this is actually more about having enough CPU resources to do stuff like audio decoding, video capture etc without just going for a Cortex A. I wonder if something like the Renesas RZ with a Cortex A9 (IIRC) and megabytes of SRAM would actually be better at what this is meant to do.

David Willmore
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David Willmore

> TBH I think this was designed for in-house projects and they’re trying to see if there is a market for it.

Oh, they’re Motorola’ing it. Gotcha. I always wondered why all the microcontrollers that Moto made had the most bizarre collection of peripherials. I mentioned it to someone over at Semiconductor Products Sector and their answer was “Oh, we only make custom parts either for internal or external customers. Once we’ve made the parts, though, we may offer them to the general market.” So, the reason the chips were so strange is that they were all custom designed for a very specific job. If they had leftovers or fab capacity, they’d make more and sell them to anyone else.

To someone used to nice orthogonal feature sets, this logic was bizarre and confusing. But it does make a crazy kind of sense.

Any idea if a 6x M4 has to pay the royalty for every core or just once? I can’t believe 6x the royalty of the M4 is less than the royalty for 1 A9/A5/A7 or whatever. Maybe a process/power limitation? I guess if you have a problem that breaks down well into 6 even parts…. Like the voice transcoder boards in Mot’s GSM cell systems. Just full of 31 separate DSPs–each one transcoding one PCM stream. Why not? Each one could *just* do that much work at sane clocks/power levels, so it wasn’t like they could do two channels/DSP. And then Enhanced Full Rate and Half Rate came in they they took more processing so all that went out the window. Good time.

dgp
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dgp

>I always wondered why all the microcontrollers that Moto made had the most bizarre collection of peripherials.

I’m not hugely knowledgeable about the motorola 8 bit stuff but it seemed like once the 68k wasn’t going to be a mainstream general purpose CPU anymore they took the 68000 and dropped it into some stuff like the telecom specific chips or the complete palm pilot on a chip dragonballs. There was never just a 68000 with the basic stuff to use it like a high power MCU (UART, Timers, DRAM logic) AFAIK even though Toshiba were shipping 68000s like that. So I guess those were designed for a big contract (like some telco or palm) and then offered to the general public? The standalone 68sec000 then seems to be an offshoot of having reimplemented the 68000 for the dragonballs and then thinking what the heck and selling it as a standalone chip. I did find some info about Motorola offering that 68000 core as an IP block but not much actual detail.

>Maybe a process/power limitation? I guess if you have a problem that breaks down well into 6 even parts….

I seem to remember there being some weird offshoot of the 68K where you had a single 68000 core but multiple banks of the registers so you could have multiple *threads* without ever having to do a context switch.

David Willmore
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David Willmore

Yes, the 68K was treated the same way, although the family did keep going with compute only processors all the way up to the 060, IIRC. I was thinking of the 6809 microcontrollers primarily, but the same is true of the 68K.

I’m not recalling a 68K with those threading abilities. I do remember the Tera processor arch which did a similar thing to hide memory latency.