The PCIe 7.0 specification has been released, offering a data rate of up to 128GT/s, or a bi-directional transfer rate of 512GB/s in x16 configuration. This doubles the speed of PCIe 6.0 specification released in 2022, reaching up to 64GT/s data rate, or 256GB/s bi-directional transfer rates.
PCI-SIG says the PCIe 7.0 specification targets data-intensive applications such as AI/ML, 800 Gbps Ethernet, cloud, and Quantum computing. Work on PCIe 8.0 has started, likely aiming for 256GT/s and a 2028 release date.
Like PCIe 6.0, PCIe 7.0 utilizes PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding. It also provides improved power efficiency and maintains backwards compatibility with previous generations of PCIe technology.
New specifications are released regularly, and since the introduction of PCI in 1992 with a 013GB/s data rate, the PCI/PCIe bandwidth has roughly doubled every three years, as illustrated in the chart below.
Although it typically takes around 18 months for a new PCIe specification to be adopted in high-end hardware, broad adoption takes much longer. For instance, PCIe 5.0 was announced in 2019, started to show up in Alder Lake-S IoT processors in 2022, and has only become more common very recently, although most x86 computers still rely on PCIe 4.0 introduced in 2017.
It takes even more time in SBCs. The Raspberry Pi CM4 got PCie 2.0 x1 in October 2020, but that’s a system-on-module launched in October, and the first PCIe-capable SBCs were likely those based on Rockchip RK3566/68 SoC introduced in 2020 with PCIe 2.0, such as the Firefly ROC-RK3566-PC or Geniatech RK3568 development board. Rockchip RK3588 SBCs released in 2022 and beyond, and the Raspberry Pi 5 introduced in 2023, further democratized PCIe Gen 2.x/3.0 in single board computers. That would be about 14 years after PCIe 2.0 and 12 years after PCIe 3.0. So a Raspberry Pi 10 with PCIe 7.0 might become available in 2038, if single board computers are still a thing by that time :).
You’ll find the latest PCIe specification available to members ($5,000 annual membership fee) and additional details on the PCI-SIG website.
Via Liliputing
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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I’m wondering how long they’ll continue to use unidirectional lanes. By using them in bidirectional mode or even just returning them for a transfer, since most traffic is mostly unidirectional, would permit to double the bandwidth again. Maybe the prevalence of SSDs that can use short burst of extreme bandwidths when loading LLMs can play a role for a change in that direction. We could even imagine that such changes could be backported to older versions (e.g. 6.1, 7.1 etc) and be compatible with boards running at a lower speed provided that the chip and device support it, since the traces already exist on the board.
True bidirectional links have several downsides:
Looking at current busses, the only high speed bus using bidirectional lanes for some part is USB 4, where one lane can be used in both directions. But this is then fixed at connection time (not changeable at runtime), and optional for most devices on the bus (there is still 1 RX and 1 TX pair always available).
But then you would need to dedicate a minimum of 2 lanes to any link between devices, rather than the current 1 lane. The design of PCI is based around just throwing lanes at the issue (1x, 2x, 4x, 8x and 16x) and switching the allocated lanes’ direction as the data flow requires, rather than dedicating lanes for each direction.
Inagine something at home requiring this speed in the next 50 years? lol
I would guess that many graphics cards will be using such speed far sooner than 50 years from now. Don’t forget it means that a PCIe 7 based system will be able to just use 2 lanes to match the performance of a current PCIe 4 based system that has allocated 16 lanes to a problem.
A lot of consumer grade graphics cards don’t even need the full PCIe 5 x16 connection. The performance difference compared to a PCIe 3 x16 connection is minimal, so most current desktop GPUs could run on PCIe 5 x4 and still perform very near their maximum performance.