SiFive has just launched its 2nd Generation Intelligence family, featuring five new RISC-V-based products: the new X160 Gen 2 and X180 Gen 2, and upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 processors, all featuring scalar, vector, and matrix processing (XM only) capabilities designed for AI workloads.
The original Intelligence X280 64-bit RISC-V CPU was introduced in 2021, following the Intelligence X390 NPU in 2023, and the Intelligence XM Series in September 2024. The X160 Gen 2 (32-bit) and X180 Gen 2 (64-bit) are entry-level AIoT CU cores targeting edge compute and IoT applications for automotive, autonomous robotics, industrial automation, and smart IoT applications. The upgrade models get support for the RVA23 profile and a few other changes.
SiFive X160/X180 Gen 2 CPUs
Key features and specifications:
- Scalar processing
- Intelligence X160 Gen 2 – 32-bit RISC-V ISA (RV32I)
- Intelligence X180 Gen 2 – 64-bit RISC-V ISA (RV64I)
- Dual issue, in-order 8-stage superscalar pipeline
- Vector Processing
- 128-bit wide vector registers (vlen)
- 64-bit datapath (dlen)
- Int8 and BFloat16 support
- Integer: 2x 32-bit/4x 16-bit/8x 8-bit per cycle
- Floating point: 2x Single precision, 4x Half precision per cycle
- RISC-V Vector Extension v1.0 (RVV1.0)
- In-order sequencing of vector operations (decoupled from scalar execution)
- Other specs
- Single and multi-core configurations, up to quad-cores
- SiFive Custom Instruction Extension (SCIE)
- SiFive Scalar Coprocessor Interface (SSCI) – Drives accelerator via RISC-V custom instructions with direct access to CPU registers. Flexible range of instruction opcode formats.
- Vector Coprocessor Interface eXtension (VCIX) – A vector instruction-mapped interface, enabling a direct connection between the X-series vector ALU to a custom accelerator, allowing custom vector instructions to be executed on the accelerator from the vector pipeline.
- Memory port with full duplex load/store bandwidth (8B read + 8B write)
- Up to 16 Physical Memory Protection (PMP) regions
- Optional SiFive WorldGuard security, up to 4 worlds supported
The Intelligence X160 32-bit IP core is designed to be optimized for power efficiency and severely area-constrained applications, while the Intelligence X180 64-bit IP core can deliver higher performance and better integration with larger memory systems.
Upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 cores
The X-Series, 200 Class, 300 Class, and XM Series are all upgrades. SiFive did not provide the full details, at least undr embargo, but the table below gives from clue. One of the main change is support for the RVA23 profile. Others changes include support for extra vector datatypes (FP4, FP8), a wider ange of cache options, and a few changes in the ports available. SiFive has not been extra clear about that…
All five Intelligence Gen 2 products are available for licensing now, and the first silicon is expected in Q2 2026. The cores will also be showcased at the AI Infra Summit in Santa Clara, US on September 9-11. You should be able to get more information about the 2nd Gen Intelligence RISC-V IP and access the product brief for the X160 Gen 2, X180 Gen 2, X280 Gen 2, and X390 Gen 2, and the Intelligence Family Brief on the SiFive Intelligence page.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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