NXP has recently introduced the i.MX 952 applications processor, a new member of the i.MX 95 series, designed for AI-powered automotive and industrial applications, including driver monitoring, child presence detection, and in-cabin HMIs.
The i.MX 952 features up to four Arm Cortex-A55 cores with Cortex-M7 and M33 microcontroller cores, and is compliant with ISO 26262 ASIL B and SIL2/SIL3 standards. It integrates an eIQ Neutron NPU for AI-based sensor fusion, a 500 Mpixel/s ISP with RGB-IR support, and is the first processor with built-in local dimming for better display efficiency. Security features include EdgeLock Secure Enclave with post-quantum cryptography, meeting ISO 21434 and IEC 62443 standards. It can be interfaced with NXP’s PF09 PMIC, PF53 regulator, Trimension UWB, and IW693/AW693 Wi-Fi 6/6E SoCs, and is pin-to-pin compatible with other members of the i.MX 95 family.
NXP i.MX 952 specifications:
- CPU
- Up to 4 Arm Cortex-A55 cores with 32KB + 32KB L1-cache, 64KB L2 cache, 512KB L3 cache with ECC
- 1x Arm Corex-M7 real-time core with 32 KB + 32 KB cache, 512KB TCM with ECC
- 1x Arm Cortex-M33 low-power Safety/system microcontroller with 16 KB + 16 KB cache, 256KB OCRAM with ECC
- GPU – Unnamed Arm Mali 3D GPU with OpenGL ES 3.2, Vulkan 1.2, OpenCL 3.0, 2D GPU
- AI accelerator – NXP eIQ Neutron NPU
- Memory I/F
- Up to x32 LPDDR5 (6000 MT/s) / LPDDR4X (4266 MT/s) with inline ECC and encryption
- Up to 768 KB on-chip OCRAM (ECC)
- Storage I/F
- 3x uSDHC interfaces (SD 3.0 / SDIO 3.0 / eMMC 5.1)
- Octal/Quad SPI Flash (inline crypto, IPED, SPI NOR/NAND)
- Display I/F
- 1x 4-lane MIPI-DSI interface
- 2x 4-lane or 1x 8-lane LVDS
- Camera I/F – 4-lane or 2x 2-lane MIPI-CSI
- Audio – 15-lane I²S TDM Tx/Rx, SPDIF Tx/Rx, PDM mic input
- Networking
- 1x 2.5 Gbps Ethernet (TSN)
- 2x 1 Gbps Ethernet (TSN, AVB, IEEE 1588, EEE)
- USB – 2x USB 2.0 with integrated PHY
- PCIe – 1x PCIe Gen 3.0 (1 lane, 2.5 Gbps mux)
- Serial
- 3x CAN-FD
- 8x UART/USART
- Other peripherals
- 8x LPI2C, 8x LPSPI, 2x I3C
- 2x 32-pin FlexIO interfaces (camera, bus, or serial I/O)
- Security (EdgeLock Secure Enclave )
- Secure boot, secure clock, crypto engine, and tamper detection
- eFuse key storage and hardware random number generator
- EdgeLock Prime accelerator
- Post Quantum Cryptography (PQC) support
- Complies with IEC 61508 (SIL 2) and ISO 26262 (ASIL B) functional safety standards
- Packaging
- 19 × 19 mm FCBGA (0.7 mm pitch)
- 15 × 15 mm FCBGA (0.5 mm pitch)
- Temperature Ranges
- Consumer – 0 ºC to 95 ºC
- Standard Industrial – -40 ºC to 105 ºC
- Automotive / Extended industrial – -40 ºC to 125 ºC
From the specifications block diagram and overall description, the i.MX 952 It features the same heterogeneous architecture with Cortex-A55, M7, and M33 cores, an eIQ Neutron NPU, and a high-performance ISP as the i.MX 95, but adds new features like local dimming for displays and post-quantum cryptography (PQC) within the EdgeLock Secure Enclave. Compared to the i.MX 95, it reduces CPU cores (6→4), on-chip memory, and some high-speed I/O options (no USB 3.0 or 10GbE), for a more efficient balance between performance and safety (up to SIL 3) features.
The NXP i.MX 952 supports Linux and Android BSPs for the Arm Cortex-A55 application cores, while the Cortex-M7 and Cortex-M33 real-time and safety cores are supported by FreeRTOS. The integrated eIQ Neutron NPU is compatible with NXP’s eIQ machine learning software development environment for model optimization, quantization, and deployment of AI and vision workloads at the edge. Developers can also use NXP’s Yocto-based Linux SDK, EdgeLock security framework, and MCUXpresso suite for toolchain integration, secure boot configuration, and safety-critical development across automotive, industrial, and IoT platforms.
After the initial release of the i.MX 95 series, we have seen various development boards and systems-on-modules (SoMs) built around the i.MX 95 SoC, including the ADLINK OSM-IMX95, Compulab MCM-iMX95 SoM, Forlinx FET-MX95xx-C (FET-MX9596-C), and the Toradex Titan Evaluation Kit, among others.
The i.MX 952 processor is in preproduction, with specifications subject to change. More details may be found on the product page and the press release.
Debashis Das is a technical content writer and embedded engineer with over five years of experience in the industry. With expertise in Embedded C, PCB Design, and SEO optimization, he effectively blends difficult technical topics with clear communication
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