ESP32JTAG – An open-source wireless JTAG and logic analyzer (Crowdfunding)

EZ32 ESP32JTAG is an open-source, wireless JTAG and logic analyzer tool that can debug both MCUs and FPGAs. It features a 16-channel 250 MHz logic analyzer and integrated UART interface, designed to replace tools such as ST-Link or Saleae analyzers in a single compact, wireless solution.

The device is built around an ESP32-S3 dual-core SoC and a small FPGA with 5k logic gates and 1 Mbit of internal RAM to handle high-speed signal processing.  Connectivity options include Wi-Fi 4, Bluetooth 5.0, and USB Type-C, and a small 1.83-inch LCD displays system information such as IP address and status. The ESP32JTAG is also equipped with four configurable 4-wire ports for JTAG, SWD, UART, and logic analyzer mode, and supports target voltage monitoring.

ESP32JTAG Deveice

EZ32 ESP32JTAG specifications:

  • Wireless MCU – Espressif Systems ESP32-S3
    • CPU – dual-core Tensilica LX7 @ up to 240 MHz with vector instructions for AI acceleration
    • Memory – 512KB RAM, 8MB PSRAM
    • Built-in wireless connectivity (See below)
  • Storage – 16MB flash
  • FPGA – Gowin Semiconductors GW1N FPGA (Not confirmed)
  • Display – 1.83-inch LCD for IP address, Wi-Fi status, and system information
  • Connectivity via ESP32-S3
    • 2.4 GHz 802.11 b/g/n Wi-Fi 4 with 40 MHz bandwidth support
    • Bluetooth Low Energy (BLE) 5.0 connectivity with the long-range backing, 2 Mbps data rate
    • Onboard PCB antenna module
  • USB – USB Type-C port for power and programming
  • Supported Modes
    • MCU JTAG/SWD debugging (OpenOCD, Blackmagic Probe, CMSIS-DAP)
    • FPGA JTAG programming (openFPGALoader, XVC for Vivado)
    • UART terminal with WebTerminal support
    • 16-channel logic analyzer, up to 250 MHz sampling rate
  • Misc
    • Boot, Reset buttons
    • Voltage monitoring and reset control
  • Power – 5V via USB-C port
  • Dimensions – 40 x 33 x 5 mm (bare board); 120 x 80 × 20 mm (package)
  • Weight – 200 grams (with packaging)
  • Compliance – CE, UKCA (underway), FCC (ESP32-S3 pre-certified module)
ESP32JTAG module
ESP32JTAG backside

In terms of software support, the ESP32JTAG works with open-source tools such as OpenOCD, Blackmagic Probe, CMSIS-DAP, GDB Server, and openFPGALoader. It also supports IDEs like VSCode, Arduino IDE, STM32CubeIDE, Vivado, and PlatformIO. The built-in web interface provides configuration, firmware updates, and access to a browser-based logic analyzer and WebUART terminal without needing drivers. The firmware is based on ESP-IDF and FreeRTOS, and the company mentions that all hardware and files will be open-source and available on GitHub. EZ32 plans to release all open hardware files, firmware, and documentation before production is complete. The latest hardware revision (v1.4) focuses on Wi-Fi performance and enclosure.

Previously, we have written about other debugging tools like the WiSer, which allows users to establish a P2P wireless connection between a host computer and the USB-Cereal designed to simplify the testing, development, debugging, and manufacturing of devices with USB Type-C ports. While writing, one interesting thing I noticed is that the hardware configuration is very similar to the LILYGO T-FPGA devkit, with the same ESP32-S3 and GW1N FPGA configuration.

ESP32JTAG OpenOCD and Logic Analizer Example
ESP32JTAG OpenOCD and Logic Analyzer Example

The ESP32JTAG is available for pre-order on Crowd Supply for $139 with free US shipping and $12 to the rest of the world. The campaign has already met its $10,000 funding goal and will remain open until December 4, 2025. Deliveries are expected to start on February 14, 2026. Units will be manufactured and tested by a professional PCB assembly house and fulfilled globally via Mouser’s logistics network.

Share this:
FacebookTwitterHacker NewsSlashdotRedditLinkedInPinterestFlipboardMeWeLineEmailShare

Support CNX Software! Donate via cryptocurrencies, become a Patron on Patreon, or purchase goods on Amazon or Aliexpress. We also use affiliate links in articles to earn commissions if you make a purchase after clicking on those links.

Radxa Orion O6 Armv9 mini-ITX motherboard

2 Replies to “ESP32JTAG – An open-source wireless JTAG and logic analyzer (Crowdfunding)”

  1. I wonder if the ESP32JTAG can be made to work to download/debug an elf onto a RiscV inside a Lattice FPGA. Using an FTDI F2232H I programmed the ECP5 bitstream (ecpdap/ecpprog) but could never get OpenOCD to talk to the VexRiscV.

    Regarding the Logic Analyzer, I know the Saleae products stream the data real-time to the PC via usb3, so that the memory depth is virtually unlimited. Other LAs (LogicPort) capture locally, and therefore the depth is determined by how many channels (1-34) you are capturing and the sample rate (1khz-500mhz). How does the ESP32JTAG  work? BTW, is the use of Sigrok for the GUI possible?

    Speaking of streaming, I think one of the features that makes Segger tools and clones (Orbtrace Mini) so expensive is that they can stream trace data via SWD..

Leave a Reply

Your email address will not be published. Required fields are marked *

Boardcon MINI1126B-P AI vision system-on-module wit Rockchip RV1126B-P SoC
Boardcon MINI1126B-P AI vision system-on-module wit Rockchip RV1126B-P SoC