After the release of the high-performance EPYC Embedded 9005, AMD has now introduced the EPYC Embedded 2005 Series, a mid-range processor family also based on the “Zen 5” architecture and designed for space-constrained networking, storage, and industrial edge applications.
The new SoCs feature up to 16 cores (32 threads) with 64 MB L3 cache, support dual-channel DDR5-5600 memory with ECC, and offer 28 lanes of PCIe Gen5 connectivity. It also supports advanced RAS capabilities, BMC, PCIe Hot Plug, multi-SPI ROM, and AMD Infinity Guard security. The processors come in a compact 40 x 40mm BGA package, which, according to AMD, is up to 2.4x smaller than competing enterprise solutions (Intel Xeon 6500P-B). Yet, they are designed for 24/7 operation, with up to 10 years of availability with full open-source software support. These features make it suitable for networking switches/routers, cold storage systems, aerospace, robotics, and other high-reliability embedded infrastructure.
EPYC Embedded 2005 specifications:
| Feature | EPYC Embedded 2435 | EPYC Embedded 2655 | EPYC Embedded 2875 |
|---|---|---|---|
| Architecture | Zen 5 |
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| Die Configuration | 1 CCD + 1 IO | 1 CCD + 1 IOD | 2 CCD + 1 IOD |
| Cores / Threads | 8C / 16T | 12C / 24T | 16C / 32T |
| Base / Boost Clock | 2.8 / 4.5 GHz | 2.7 / 4.5 GHz | 3.0 / 4.5 GHz |
| L2 Cache | 8 MB | 12 MB | 16 MB |
| L3 Cache | 32 MB | 64 MB | 64 MB |
| Memory | 2-Channel DDR5-5600 (1 DIMM/ch) or DDR5-3600 (2 DIMMs/ch) w/ sideband ECC |
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| USB | 4× USB 3.2 Gen 2 (10 Gb/s) + 1× USB 2.0 (480 Mb/s) |
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| Expansion | 28 Lanes, 11 Root Ports, SR-IOV, Enhanced Hot Plug. GPIO, I²C, I³C, SMBus, SPI, eSPI. |
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| Security Processor | Yes |
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| TDP | 45 W | 55 W | 75 W |
| cTDP Range | 45–55 W | 45–75 W | 45–75 W |
| Package | FL1 Lidless BGA: 40×40×2.133 mm, 0.81 mm pitch, 1,763 balls |
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| Socket | 1P SoC |
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| Junction Temp | 0 to 105°C |
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At the time of writing, the series includes only three SKUs with 45–75W configurable TDP, namely the EPYC Embedded 2435, EPYC Embedded 2655, and EPYC Embedded 2875. The company also mentions that it is manufactured using 4nm process technology for the Core Complex Die (CCD) and 6nm for the I/O Die (IOD). These chiplets are integrated into a 40x40mm BGA package, which reduces the processor’s vertical profile to just 2.13mm and allows for direct-die cooling to support fanless and ruggedized industrial deployments.
In terms of software support, the EPYC Embedded 2005 Series supports a standard embedded software stack, including EDK II firmware, Yocto-based Linux distributions, and upstream Linux kernel drivers. Other than that, there is not much additional information available at the time of writing, and AMD’s Technical Information Portal does not provide any documentation or software resources for the new series.
The EPYC Embedded 2005 can be considered one of a kind because it brings a full EPYC-class BGA platform for the first time in a while, now using the FL1 BGA footprint. The silicon itself is not new, as it uses the 6nm I/O die and 4nm Zen 5 chiplets from the EPYC Embedded 4005 chips. What’s truly new is that AMD is making all of its enterprise features available on an embedded chip for the first time.
At the time of writing, AMD has not disclosed pricing for the EPYC Embedded 2005 Series. The processors are currently sampling with partners, with mass production scheduled for Q1 2026. More information can be found on the company’s product page and press release.
Debashis Das is a technical content writer and embedded engineer with over five years of experience in the industry. With expertise in Embedded C, PCB Design, and SEO optimization, he effectively blends difficult technical topics with clear communication
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At last, a chip that is not marketed as “AI-blablabla” in 2025! It’s a bit late in the year but better late than never 🙂
Agreed! This looks like a solid small server-class CPU family, specially considering ECC RAM support. It would be great to see a Enterprise-class notebooks (or at least SFFPCs) using them, but given that must people don’t seem to care about reliability anymore, I’m not holding my breath.
An i was going to say 28lanes PCIe – perfect for ai!
😉
That’s 1 Tbps of total bandwidth in each direction, it’s perfect for lots of things (storage, network, etc). You could for example easily imagine setting up a 400 Gbps file server with this.
Wouldn’t you need a network offload FPGA for those kinds of network speeds?
> Wouldn’t you need a network offload FPGA for those kinds of network speeds?
No, with todays CPUs and NICs, it’s just easy. The CPU basically just presents pages with up to 64kB of data to the NIC which will segment it using TSO when sending. I’m not going to say it’s super cheap of course but it’s totally within range of what modern servers are handling. The main difficulty with the chip here is that it has two CPU dies, hence poor connectivity between its L3 caches. But that might still be manageable (e.g. by using two storage adapters instead of one and having only 8 cores on each).
Would love to see this on a new board by pcengines, but it seems they left the market behind, just selling off the remaining mechanical parts as long stocks last…