AMD Kintex UltraScale+ Gen 2 is a mid-range FPGA family designed for the broadcast, test, industrial, and medical markets, which provides an update to the Spartan UltraScale+ FPGA family introduced in 2024, and promises availability until at least 2045.
Key features include high-speed transceivers and PCIe Gen4 for support of 4K AV-over-IP, multi-stream capture, and frame-accurate transport, increased memory bandwidth for semiconductor test and inspection systems, and advanced imaging and real-time control for machine vision, industrial automation, medical imaging, and robotic systems.
AMD Kintec UltraScale+ Gen2 key features
| Device Name | 2KU030P | 2KU040P | 2KU050P |
|---|---|---|---|
| System Logic Cells (K) | 328 | 410 | 491 |
| CLB LUTs (K) | 150 | 187 | 225 |
| Total RAM (Mb) | 33.9 | 42.4 | 50.9 |
| Memory Controller LPDDR4X/5/5X | 4 | 6 | 6 |
| DSP Slices | 1248 | 1560 | 1872 |
| PCI Express | 2x Gen4x8 | 2x Gen4x8 | 2x Gen4x8 + 1x Gen4x4 |
| Max. I/O (HDIO/XP5IO) | 78/264 | 78/396 | 120/396 |
| GTY Transceivers | 16 | 16 | 24 |
| 100G CMAC | 2 | 2 | 2 |
AMD says the Kintex UltraScale+ Gen 2 devices deliver up to 5x increase in memory bandwidth when comparing the AMD Kintex UltraScale+ Gen 2 XC2KU040P and XC2KU050P FPGAs to the previous generation Kintex UltraScale+ FPGA, and up to 2x higher channel density per PCIe interface compared to the Altera Agilex A5EC065A FPGA.
The company further states that compared to “competing platforms”, the family delivers up to 80% higher embedded RAM, 2x DSP density, and substantially higher LPDDR memory bandwidth. Looking at the footnotes, those numbers are based on AMD engineering projections for AMD Kintex UltraScale+ Gen 2 XC2KU050P FPGAs compared to the published specifications for Altera Agilex A5EC052A FPGAs.
If we look at the AMD Kintex portfolio, the UltraScale+ Gen2 actually offers fewer LUTs than the Kintex UltraScale+ family, but much higher memory bandwidth, and slightly faster I/Os, as well as faster PCIe Gen4 interfaces.
You’ll also need to wait at least until the end of the year before getting Kintex UltraScale+ Gen2 silicon. Vivado and Vitis tools will support simulation in Q3 2026 for early design work. However, pre-production XC2KU050P FPGA silicon is scheduled for sampling in Q4 2026, and mass production is only slated for H1 of 2027. A Kintex UltraScale+ Gen 2 evaluation kit based on the XC2KU050P FPGA will start sampling in Q4 2026.
In the meantime, the existing Spartan UltraScale+ SCU200 Evaluation Kit based on the migration-capable XCSU200P device is said to be available today. However, I’m unable to find any photos or information about this development kit, and it appears it should become available in the next few weeks based on the slide above. It features the SCU200P FPGA with 218K logic cells, HSIO, Pmod, and 40-pin expansion connectors, as well as a PCIe Gen4 x4 interface.
More details can be found on the product page and the announcement. AMD will also be discussing the Kintex UltraScale+ Gen 2 FPGAs at Integrated Systems Europe (ISE) 2026 on February 3-7.
Thanks to TLS for the tip.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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