AMD launches Versal Prime Gen 2 2VM3454, 2VM3254, and 2VM3104 adaptive SoCs in compact 23x23mm packages

AMD has added three new chips to its Versal Prime Series Gen 2 lineup: the Versal 2VM3454, 2VM3254, and 2VM3104. Designed for space-constrained applications like Pro AV, broadcast, and industrial IoT, these new devices deliver up to 100K DMIPS of scalar compute in packages as small as 23 x 23 mm.

AMD started shipping the first production units of the Versal Prime Gen2 Series with the 2VM3858 device late last year. The 2VM3558 has since entered full production, while the 2VM3358 is currently sampling. These new devices are designed to provide an optimized footprint and processing subsystem compared to the earlier models. Despite the reduction in core count, AMD claims these devices can deliver up to 5x the scalar compute performance compared to existing AMD adaptive SoCs.

MD Versal Prime Gen 2 Adaptive SoC 2VM3454, 2VM3254, and 2VM3104

AMD Versal Prime Series Gen 2 (2VM3104, 2VM3254, and 2VM3454) specifications:

  • Processor Subsystem (PS)
    • APU – Quad-core Arm Cortex-A78AE with 64 KB L1 Cache (with parity & ECC), 512 KB L2 Cache, and 2 MB L3 Cache per cluster
    • Real-time Processor – Hexa-core (6x) Arm Cortex-R52 with 32 KB L1 Cache (with ECC) and 128 KB TCM (with ECC)
    • GPU – Integrated single-core Arm Mali-G78AE GPU
    • Video Codec Unit (VCU) – 1x hardened tile on the 2VM3254 and 2VM3454 supporting HEVC & AVC encode and decode up to 4K60, 4:4:4, 12-bit (not available on 2VM3104)
    • Memory – 1 MB On-Chip Memory with ECC
  • Programmable Logic (PL) and DSP
    • System Logic Cells – Up to 564,760 (2VM3454)
    • LUTs – Up to 258,176 (2VM3454)
    • DSP Engines – Up to 1,140 (2VM3454)
  • Memory
    • DDR5 memory controllers up to 6400 Mb/s and LPDDR5X up to 8533 Mb/s; up to 102 GB/s maximum bandwidth
    • Total PL Memory – Up to 45.4 Mbit
  • Storage – UFS 3.1 support
  • Display – DisplayPort 1.4
  • Networking
    • Up to 2x 100Gbps Multirate Ethernet MAC on the 2VM3454 (1x on 2VM3104 and 2VM3254)
    • 10Gbps Ethernet and 1Gbps Ethernet
  • USB – USB 3.2 and USB 2.0 support
  • Other I/O – Up to 16x GTYP transceivers (PL-Only) up to 32 Gbps (4x on 2VM3104; 8x on 2VM3254)
  • Expansion – PL-based PCIe Gen5x4 controller on the 2VM3254 and 2VM3454 (not available on 2VM3104), plus PS-based PCIe Gen5 x4 support
  • Security
    • Application Security Unit and general security enhancements
    • High-speed crypto engine (HSC) available on the 2VM3454
  • Packages
    • 23×23 mm – 2VM3104, 2VM3254
    • 29×29 mm – 2VM3454

Versal Prime Series Gen 2 Block Diagram

The combination of Cortex-A78AE and Cortex-R52 cores helps these SoCs handle complex tasks and real-time control more easily. The programmable logic also enables developers to process sensor data quickly and in real time. AMD has also added various safety features (ASIL D/SIL 3), eliminating the need for a separate safety controller and reducing system size. Developers can still update algorithms or video processing later without changing hardware.

The 2VM3654 SKU was released earlier, but it also shares the same footprint, so the new chips can be installed in older PCBs very easily. AMD also notes that the new small devices offer more programmable logic per square millimeter than comparably sized 8-core devices.

MD Versal Prime Gen 2 Specifications

On the software side, AMD provides Vivado for RTL design (Verilog/VHDL) and Vitis for building software on the Arm Cortex-A78/R52 processor cores. AMD also maintains the Embedded Development Framework (EDF) based on Yocto, and including ready Linux images, drivers for video, GPU, and fast memory. You can also run simple bare-metal programs on the real-time cores.

Early Access design tools are already available for the Versal 2VM3654, with the 2VM3454 expected to begin sampling later in 2026. The more compact 2VM3254 and 2VM3104 are expected to become available in 2027. Full production tool support will follow accordingly. Additional information can be found on the Versal Prime Series Gen 2 product page and in the press release.

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