OpenC6 BIOS project brings PC-like firmware to ESP32-C6 MCU with network boot and OTA update support

OpenC6 BIOS is an open-source project by Rompass that takes a different approach to MCU development. It adds a BIOS-like system to the ESP32-C6, so the system part and application code can run separately rather than being combined into a single firmware image.

In traditional development, hardware setup, networking, and application code are combined into a single firmware image. But the OpenC6 BIOS operates differently: it runs as the base system on the ESP32-C6 and handles hardware initialization and system functions. Instead of flashing a full application each time, it can load small payload programs separately. These payloads can run from RAM or flash (XIP) and use system functions through a simple Application Binary Interface (ABI), without needing the full firmware. In some ways, it operates like AkiraOS, but with a BIOS-like interface.

OpenC6 BIOS for ESP32 C6

Key features of the OpenC6 BIOS architecture:

  • Dynamic CPU scaling – Adjusts CPU frequency based on load using FreeRTOS idle time (80, 120, and 160 MHz)
  • Modular firmware architecture – Hardware setup is handled by the BIOS, while applications are compiled as small independent payloads (2–10 KB)
  • System Call Interface (ABI) – Payloads can access Wi-Fi, math, and crypto functions provided by the BIOS without linking to the full ESP-IDF
  • LP-Core management engine – Uses the ESP32-C6 low-power RISC-V core to monitor system health, watchdog timers, and power events independently of the main application
  • Network boot (PXE-like) – Payloads can be downloaded over Wi-Fi and executed without flashing via USB
  • A/B OTA updates – Firmware updates include rollback support to avoid bricking the device
  • Web-based setup interface – A local Wi-Fi access point (BIOS_SETUP_C6) hosts a browser-based configuration page (192.168.4.1) similar to a PC BIOS setup utility with a 1280×1024 blue-screen look
  • Aura Sync RGB – Supports Aura Sync RGB Flow and POST diagnostic codes
  • Misc
    • Power Button – GPIO 4  (Short click: Boot; Hold 3s: Setup; Hold 5s: Hard Reset)
    • BOOT Button – GPIO 9 (Standard BOOT pin. Hold during startup for Boot Menu)
    • POST LED – GPIO 8 (Addressable RGB for diagnostics and Aura Sync)
    • Clear CMOS – GPIO 2 (Short during boot to reset NVRAM to factory defaults)
    • Payload RX / TX – GPIO 18 / GPIO 19 (Dedicated UART for the Serial Bootloader)

Retro Web Setup Utility (1280x1024 5:4 Native Look)
Retro Web Setup Utility (1280×1024 5:4 Native Look)

The BIOS runs first after boot and performs hardware initialization. It then exposes services through a defined ABI, so compiled payloads can be uploaded to a UART serial loader, network-booted over an HTTP server, or executed directly from flash (XIP), without using the full ESP-IDF.

This is similar to old PC BIOS, which gave basic functions before starting the OS, but here it is used to run small embedded programs instead of a full operating system.

ESP32-C6 Zero development board
ESP32-C6 Zero development board

The project is designed for generic ESP32-C6 boards with at least 8MB of Flash. The ESP32-C6 Zero board was used for development and testing, but the OpenC6 BIOS project should also work with boards such as the Olimex ESP32-C6-DevKit-Lipo, WeAct ESP32-C6 (8MB), Arduino Nesso N1, and others. Modifications for each board may be required, since the firmware assigns GPIOs for power and reset control, an RGB LED for status indication, a UART for loading payloads, and configuration pins similar to CMOS reset pins.

To get started, you need to install ESP-IDF (development version) and build the BIOS firmware. Payloads are compiled separately using the provided tools available in the tools directory.  Network booting is supported by running a simple local HTTP server and pointing the device to the payload URL through the web setup interface.

OpenC6 BIOS is open source under the MIT license. The code, documentation, and payload build instructions are available on GitHub. The developer is also looking for contributors to work on a custom zRAM and a lightweight file system for RISC-V.

Via Hackaday

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