AMD has announced the Versal Premium Gen 2 Memory-on-Package (MoP) adaptive SoCs, adding an integrated memory option to the Premium Gen 2 family, a topic we covered back in November 2024.
While the core silicon (dual-core Cortex-A72 + dual-core Cortex-R5F + high-end FPGA fabric) remains the same, the new devices (2VP3422, 2VP3522, and 2VP3622) integrate up to 32 GB of LPDDR5X memory directly inside the package. This removes the need for external high-speed memory on the board and reduces PCB area by up to 60%. This also eliminates high-speed memory routing on the carrier board, increasing the maximum memory bandwidth to 288 GB/s.
AMD Versal Premium Gen2 MoP specifications:
- CPU cores
- Dual-core Arm Cortex-A72 application core, 48 KB/32 KB L1 Cache w/ parity & ECC; 1 MB L2 Cache w/ ECC
- Dual-core Arm Cortex R5F, 32 KB/32 KB L1 Cache, and 256 KB TCM w/ECC
- Memory on Package
- 32 GB of LPDDR5X DRAM operating at up to 9000 Mb/s
- 256 KB on-chip memory w/ECC
- Eight 32-bit hard memory controllers with hard inline ECC and encryption for data integrity
- FPGA fabric
- System Logic Cells – Up to 3,273K
- CLB LUTs – Up to 1,496K
- DSP Engines – Up to 7,616 supporting fixed- and floating-point data types for DSP and ML applications
- Interfaces connected to CPU cores
- 2x Ethernet
- 2x UART, 2x SPI, 2x I2C
- 2x CAN-FD
- 1x USB 2.0
- FPGA memory, interfaces, I/Os, and transceivers
- Total PL Memory
- 2VP3422 – 256 Mb (36 Mb Distributed RAM, 78 Mb Block RAM, 142 Mb UltraRAM)
- 2VP3522 – 327 Mb (46 Mb Distributed RAM, 99 Mb Block RAM, 182 Mb UltraRAM)
- 2VP3622 – 327 Mb (46 Mb Distributed RAM, 99 Mb Block RAM, 182 Mb UltraRAM)
- Up to 288.0 GB/s LPDDR5X on-package memory bandwidth (across eight x32-bit hard memory controllers)
- 100G multirate Ethernet MAC
- 600G Ethernet MAC
- 2VP3422 – 3 cores
- 2VP3522 – 5 cores
- 2VP3622 – 5 cores
- 2x PCIe Gen6 x8 with DMA & CXL 3.1 (via CPM6 hardened subsystem)
- 194x high-performance I/Os (XP5IO) and 78x MIO
- Total GTM2 Transceivers (supporting PAM4 and NRZ up to 128 Gb/s):
- 2VP3422: 56x transceivers
- 2VP3522: 72x transceivers
- 2VP3622: 72x transceivers
- 16x GTM2 transceivers connected to CPM6 (Note: Can bypass CPM6 using GT Direct mode to support non-PCIe protocols up to 32G NRZ or 25G NRZ depending on speedgrade)
- Total PL Memory
- High-speed crypto engines
- Hard 400G High-Speed Crypto Engines (up to 800 Gb/s line-rate encryption)
- PCIe Integrity and Data Encryption (IDE)
- DDR memory encryption in integrated controllers
- Package – VMVA3575 lidded package with stiffener ring (55 × 57.5 mm, 0.92 mm ball pitch)
- Temperatures – Extended (0°C to 110°C) and Industrial (-40°C to 110°C)
There are three SKUs: 2VP3422, 2VP3522, and 2VP3622. All three feature 32GB of integrated LPDDR5X, dual-core Arm Cortex-A72 and Cortex-R5F processors, and the same adaptive SoC architecture, while differing in FPGA resources, including system logic cells, DSP engines (2,512 to 7,616), and GTM2 transceiver counts.
The devices use the same AMD Vivado and AMD Vitis development tools as the standard Versal Premium Gen 2 family, enabling existing designs to migrate without major changes to software or the FPGA development flow.
Applications for the SoCs include cloud and data center acceleration, networking, test and measurement equipment, broadcast video, and aerospace and defense systems such as secure communications, LEO satellites, and radar. The devices are designed to operate over a wide temperature range and are covered by AMD’s 15-year product lifecycle program.
The Versal Premium Gen 2 Memory-on-Package devices are expected to begin sampling at the end of 2026, with production scheduled for the second half of 2027. More information can be found on the product page and announcement.
Debashis Das is a technical content writer and embedded engineer with over five years of experience in the industry. With expertise in Embedded C, PCB Design, and SEO optimization, he effectively blends difficult technical topics with clear communication
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