Efinix has introduced the Titanium Edge FPGA family designed for low-power edge AI and machine vision applications. Based on the company’s Titanium FPGA architecture, the new family introduces lower static power consumption, configurable 2.5 Gbps MIPI I/O, built-in single-event upset (SEU) correction, and System-in-Package (SiP) variants that integrate SPI flash and HyperRAM for compact systems.
The initial Titanium Edge FPGA family includes the Ti125, Ti40, Ti70, and Ti95 devices, with approximately 39K to 123K logic elements for embedded AI, machine vision, robotics, medical systems, and various other applications. Compared to the high-end Titanium Ti375 and the cost-efficient Topaz FPGA family, the new devices are designed to have about 50% lower static power consumption while retaining the company’s Quantum architecture.
Efinix Titanium Edge Ti125 and Ti125 SiP specifications:
- FPGA Fabric
- Efinix Quantum architecture
- Up to 122,792 logic elements (109,440 XLR cells)
- 288 DSP blocks
- Embedded Memory – 5.9 Mbit SRAM
- Memory – Integrated SPI flash and 512 Mbit HyperRAM (Ti125 SiP only)
- I/O – Up to 36 HVIO, 62 HSIO, and 84 HSIO2 pins; MIPI CSI/DSI up to 2.5 Gbps; DDR3L support up to 1,333 Mbps
- Clocking – Up to 7 PLLs and 32 global clock/control networks
- Reliability – Hardware SEU detection and correction
- Security (Optional)
- Post-quantum cryptography ML-DSA-65 (CRYSTALS-Dilithium) signature authentication
- AES-256-GCM, RSA-4096, EC-DSA-384, PUF, and TRNG
- Packages
- Ti125 – 225-ball FBGA (10 × 10 mm, F225 package)
- Ti125 SiP – 225-ball FBGA (8 × 8 mm, M225S4F4 package)
- Compliance – Upcoming CNSA 2.0
- Manufacturing process – 16 nm TSMC
At the time of writing, detailed documentation is only available for the Ti125 and Ti125 SiP models. The Ti125 SiP integrates the FPGA, 512 Mbit HyperRAM, and SPI boot flash into a single package, reducing the required PCB footprint by up to 60% compared to a discrete implementation.
Other FPGAs in the family include the Ti95, Ti70, and Ti40 devices, offering between 38,925 and 93,200 logic elements for different performance requirements. The Ti95 is sampling now, while the Ti70 and Ti40 are scheduled for Q4 2026. Efinix also plans a Ti70 SiP variant with integrated 256 Mbit HyperRAM and SPI boot flash to reduce PCB footprint.
Software support for the Titanium Edge family is provided through the Efinity IDE. The latest version (v2026.1) added dedicated support for Ti125 and Ti95 devices and delivers a complete RTL-to-bitstream design flow. It includes improvements in MIPI performance (up to 2.5 Gbps), lower power HSIO2 interfaces, and faster compile times. For hardware designers developing custom boards, Efinix provides device pinout spreadsheets (such as the Ti125 pinout) along with the updated Titanium interfaces user guide and Quantum Titanium primitives user guide.
The family also includes a hardware Single-Event Upset (SEU) detection and correction engine that helps protect the FPGA configuration from radiation-induced bit errors, making it suitable for harsh-environment applications.
The Ti125 and Ti95 are currently being sampled (specific information about Ti95 is limited), while sampling of the Ti125 SiP is scheduled for August 2026. Security variants of both devices are planned for Q4 2026. Pricing has not been announced; more information is available on the product page and press release.
Debashis Das is a technical content writer and embedded engineer with over five years of experience in the industry. With expertise in Embedded C, PCB Design, and SEO optimization, he effectively blends difficult technical topics with clear communication
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