A first look at Microchip PolarFire SoC FPGA Icicle RISC-V development board

Formally launched on Crowd Supply a little over a year ago, Microchip PolarFire SoC FPGA Icicle (codenamed MPFS-ICICLE-KIT-ES) was one of the first Linux & FreeBSD capable RISC-V development boards. The system is equipped with PolarFire SoC FPGA comprised a RISC-V CPU subsystem with four 64-bit RISC-V (RV64GC) application cores, one 64-bit RISC-V real-time core (RV64IMAC), as well as FPGA fabric. Backers of the board have been able to play with it for several months ago, but Microchip is now sending the board to more people for evaluation/review, and I got one of my own to experiment with. That’s good to have a higher-end development board instead of the usual hobbyist-grade board. Today, I’ll just have a look at the kit content and main components on the board before playing with Linux and FPGA development tools in an upcoming or two posts. Microchip PolarFire SoC FPGA Icicle Unboxing The board […]

Getting started with Bluetrum AB32VG1 RISC-V Bluetooth audio board using RT-Thread

Bluetrum AB32VG1 is a development board based on AB5301A RISC-V microcontroller designed for Bluetooth audio applications as well as general-purpose projects that works with RT-Thread real-time operating system. RT-Thread sent me a board for review, and I’ll write about my experience in a getting started guide for Bluetutm AB32VG1 trying out the RT-Thread Studio IDE with the LED blink and audio samples, as there’s no Bluetooth sample at this time… Bluetrum AV32VG1 Unboxing The board ships with a USB-C cable for power and programming. It offers Arduino UNO headers for expansion, a MicroSD card slot, a USB host port, a 3.5mm audio jack, an IR receiver, and a few buttons. There’s nothing to do on the bottom of the board apart from a QR Core for the WeChat app. There are also several configuration jumpers, but I could not find any documentation about these and did not mess with the […]

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Mikron MIK32 – Made in Russia 32-bit RISC-V MCU offers features similar to STM32L0 MCU

The Mikron MIK32 is a 32-bit RISC-V microcontroller made in Russia with features similar to an STMicro STM32L0 Cortex-M0+ MCU that shows how RISC-V open-source architecture can help lower the barrier to entry, and let more companies design their own chips. The MIK32 microcontroller features CPU IP from Syntacore based in Saint Petersburg following the RV32IMC profile. Clocked at 32 MHz, the MCU comes with I2C, UART, SPI, ADC, DAC interfaces, as well as various timers, an interrupt controller, and more. Mikron MIK32 specifications: CPU Core – 32-bit RISC-V up to 32 MHz with 32 registers,  embedded multiplier, debugger (TAP controller and JTAG interface), and interrupt controller Memory & Storage – 256 bytes OTP ROM, 16KB RAM, 8KB EEPROM Interfaces Storage I/F – SPI, Dual-SPI, Quad-SPI interfaces for NOR and NAND flash  devices 4-channel DMA controller supporting low-power modes 2x I2C, 2x UART with synchronous mode support, 2x SPI 12-bit […]

Linux 5.14 Release – Main changes, Arm, MIPS, and RISC-V architectures

Linus Torvalds has just announced Linux 5.14 release which happens to almost coincide with the anniversary of the initial announcement of the “small” project on August 25, 1991, about 30 years ago. Here’s Linux 5.14’s announcement: So I realize you must all still be busy with all the galas and fancy balls and all the other 30th anniversary events, but at some point you must be getting tired of the constant glitz, the fireworks, and the champagne. That ball gown or tailcoat isn’t the most comfortable thing, either. The celebrations will go on for a few more weeks yet, but you all may just need a breather from them. And when that happens, I have just the thing for you – a new kernel release to test and enjoy. Because 5.14 is out there, just waiting for you to kick the tires and remind yourself what all the festivities are […]

Imagination Technologies to design RISC-V cores

Now better known for its PowerVR embedded GPUs, Imagination Technologies tried to enter the CPU market by purchasing MIPS Technologies and introducing microAptiv, interAptiv, and proAptiv cores in 2012. It did not end up well, as the company had to sell its MIPS technology a few years later, and the MIPS architecture is now barely supported. But Imagination is now working on getting back into the CPU space by designing RISC-V cores. At least that’s what the company revealed in a press release also announcing overall revenues increased by 55% to $76m in H1 2021, with $70m in cash, and no external third-party debt. This year Imagination is re-entering the CPU market with designs based around the RISC-V open ISA. Imagination’s heritage in CPU enables it to provide innovative and patent protected technologies for the discrete CPU market as well as addressing demand for heterogeneous solutions that combine GPU, CPU […]

Ultra-Low-Power RISC-V System-on-Chip features Adaptive Body Biasing Technology

CSEM and USJC together have developed an ultra-low-power RISC-V chip for electronic gadgets such as wearables. The semiconductor companies, from Switzerland and Japan respectively, have been in the market for a while, developing technologies for low-power chips. Their latest collaboration uses Adaptive Body Biasing (ABB) and Deeply Depleted Channel (DDC) to build an ultra-low-power RISC-V chip with all the required and necessary components. Originating from the labs of CSEM, the Adaptive Body Biasing dwells into the operating efficiency of all the modes of ON, Standby, and OFF. There has been the problem of power leakage in Standby and OFF operating modes, but the Adaptive Body Biasing technology helps design to minimize power leakage when the processor is not operating while keeping the best performance in ON mode. For most of the designs, the processor is in Standby mode waiting for the incoming data or the next event to be offered. […]

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The RISC-V Platform Specification aims to ensure RISC-V hardware and software compatibility

The RISC-V platform specification aims to define a set of rules to make sure operating systems like Linux or the Zephyr Project can boot properly on all RISC-V hardware compliant with the specs. If you’ve ever worked with the Arm Linux kernel over ten years ago, you may remember board files, which were replaced by device tree bindings, and eventually, Arm defined several standards culminating with Arm SystemReady certifications allowing compliant Arm platforms to boot off-the-shelf OS images like in the x86 world. While we are probably a long way from a “RISC-V SystemReady” platform certification program, the RISC-V platform specification is currently being worked on to define requirements for two types of platforms with optional extensions: OS-A Platform: This specifies a rich-OS platform for Linux/FreeBSD/Windows…​flavors that run on enterprise and embedded class application processors. Current extension: Server Extension M Platform – This specifies an RTOS platform for bare-metal applications […]

ESP32-H2 RISC-V WiSoC announced with Zigbee 3, Thread, and Bluetooth LE 5.2

Just a few days ago, we noted ESP32-H2 802.15.4 & BLE RISC-V SoC had shown up in the source code, and tried to derive specs and a block diagram from the info seeing it was similar to ESP32-C3, but swapping the WiFi radio for an 802.15.4 radio. We don’t need to guess anymore, as Espressif Systems has just announced ESP32-H2 RISC-V WiSoC with support for Zigbee 3.x, Thread 1.x through the 802.15.4 radio, as well as Bluetooth LE 5.2. So overall it’s very close to what we discussed from the information in the source code with ESP32-H2 highlights including: CPU – 32-bit RISC-V core (at up to 96 MHz) RAM – 256 KB SRAM Storage – External flash support Wireless connectivity IEEE 802.15.4 radio with Zigbee 3.x and Thread 1.x support, Matter protocol Bluetooth 5.2 (LE) radio designed in-house, with support for direct connection, Bluetooth Mesh, Bluetooth LE Audio Future […]

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