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Category: Atmel SAMV7

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 6.14 release – Main changes, Arm, RISC-V, and MIPS architecture

Linux 6.14 release – Main changes, Arm, RISC-V, and MIPS architecture

Linux 6.14 release

Linus Torvalds has just announced the release of Linux 6.14 on LKML: So it’s early Monday morning (well – early for me, I’m not really a morning person), and I’d love to have some good excuse for why I didn’t do the 6.14 release yesterday on my regular Sunday afternoon release schedule. I’d like to say that some important last-minute thing came up and delayed things. But no. It’s just pure incompetence. Because absolutely nothing last-minute happened yesterday, and I was just clearing up some unrelated things in order to be ready for the merge window. And in the process just entirely forgot to actually ever cut the release. D’oh. So yes, a little delayed for no good reason at all, and obviously that means that the merge window has opened. No rest for the wicked (or the incompetent). Below is the shortlog for the last week. It’s nice and […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on Atmel SAM S70 and SAM E70 Cortex M7 MCUs, SAM V71 Xplained Board Are Now Shipping

Atmel SAM S70 and SAM E70 Cortex M7 MCUs, SAM V71 Xplained Board Are Now Shipping

ARM Introduced Cortex M7 IP in September, and ST Micro simultaneously announced its STM32F7 Cortex M7 MCU clocked up to 200 MHz, and boards are now available, including some running Linux. But two other companies have licenses Cortex M7, Freescale with its Kinetis KV5x micro-controllers which are yet to be mass-produced, and Atmel which has recently announced their SAM S70 and E70 micro-controllers are now in mass production. SAM E70 and S70 have similar features, but E70 offers some extra interface like CAN and Fast Ethernet: ARM Cortex-M7 core running at up to 300MHz (1500 CoreMark) Up to 2MB Flash and 384kByte SRAM Floating point unit (FPU) for high-precision computing and accelerated data processing High-performance internal memory architecture with user configurable Tightly Couples Memories and System memory, and 16kB I and D-cache High Speed USB Host and Device with on-chip high-speed PHY CMOS image sensor interface AES hardware encryption engines, […]