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Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Linux 6.18 LTS release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.18 LTS release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.18

Linus Torvalds has just announced the release of Linux 6.18 on the Linux Kernel Mailing List (LKML), which will likely become the next LTS kernel [update: it’s now official]: So I’ll have to admit that I’d have been happier with slightly less bugfixing noise in this last week of the release, but while there’s a few more fixes than I would hope for, there was nothing that made me feel like this needs more time to cook. So 6.18 is tagged and pushed out. Most of the last-minute fixes are minor fixes to drivers, with some random noise elsewhere (bluetooth, ceph, afs..). Nothing strikes me as standing out, but hey, there’s a shortlog appended if you want to see the details. And this obviously means that the merge window will open tomorrow, and I already have three dozen pull requests pending. Thanks. And as I already mentioned a couple of […]

Posted on by Debashis Das - 3 Comments on Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat UP201 and UP301 Series AI MCUs No BG

Upbeat Technology, in collaboration with SiFive, has introduced UP201 and UP301 always-on AI MCUs for ultra-low-power AI and IoT applications such as wearables, drones, and sensor-based systems. The UP201 is designed for compact, battery-driven devices such as smartwatches, hearing aids, and IoT sensor nodes, whereas the UP301 targets AI and vision-based applications for more complex edge systems such as smart glasses, robotics, and industrial AI equipment. Both chips feature a dual-core RISC-V architecture. The SiFive E21 lightweight core is Always-On (AON), managing continuous low-power sensing, whereas the SiFive E34 performance core activates for higher workloads. The MCUs also integrate a 2.5D GPU and various I/O options. UP201 and UP301 MCU specifications: CPU cores (SiFive Essential RISC-V IP cores) E21 core in Always-On (AON) domain for continuous low-power sensing E34 performance core in the Non-AON domain for higher workloads Up to 400 MHz operating frequency Up to 717 DMIPS performance Near-threshold […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive Intelligence X180 Gen 2 Core Complex

SiFive has just launched its 2nd Generation Intelligence family, featuring five new RISC-V-based products: the new X160 Gen 2 and X180 Gen 2, and upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 processors, all featuring scalar, vector, and matrix processing (XM only) capabilities designed for AI workloads. The original Intelligence X280 64-bit RISC-V CPU was introduced in 2021, following the Intelligence X390 NPU in 2023, and the Intelligence XM Series in September 2024. The X160 Gen 2  (32-bit) and X180 Gen 2 (64-bit) are entry-level AIoT CU cores targeting edge compute and IoT applications for automotive, autonomous robotics, industrial automation, and smart IoT applications. The upgrade models get support for the RVA23 profile and a few other changes. SiFive X160/X180 Gen 2 CPUs Key features and specifications: Scalar processing Intelligence X160 Gen 2 – 32-bit RISC-V ISA (RV32I) Intelligence X180 Gen 2 – 64-bit RISC-V ISA (RV64I) Dual […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 release arm linux mips

Linus Torvalds has just announced the release of Linux 6.16 on LKML: It’s Sunday afternoon, and the release cycle has come to an end. Last week was nice and calm, and there were no big show-stopper surprises to keep us from the regular schedule, so I’ve tagged and pushed out 6.16 as planned. It’s worth noting that the upcoming merge window for 6.17 is going to be slightly chaotic for me: I have multiple family events this August (a wedding and a big birthday), and with said family being spread not only across the US, but in Finland too, I’m spending about half the month traveling. That means that I will try very hard to get most of the merge window done the first week before my travels start, and I already ended upgiving a heads-up on that to the people who tend to send me the most pull requests. […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 6.15 Release – Main changes, Arm, RISC-V and MIPS architectures

Linux 6.15 Release – Main changes, Arm, RISC-V and MIPS architectures

Linux 6.15 release

Linus Torvalds has just announced the release of Linux 6.15: So this was delayed by a couple of hours because of a last-minute bug report resulting in one new feature being disabled at the eleventh hour, but 6.15 is out there now. Apart from that final scramble, things looked pretty normal last week. Various random small fixes all over, with drivers as usual accounting for most of it. But we’ve got some bcachefs fixes, some core networking, and some mm fixes in there too. Nothing looks particularly scary. And this obviously means that the merge window opens tomorrow as usual, and I see the usual people being proactive and having sent me their pull requests. It’s memorial day tomorrow here in the US, but like the USPS, “neither snow nor rain nor heat nor gloom of night” – nor memorial day – stops the merge window. [ Actually, thinking back […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on DC-ROMA RISC-V Mainboard is designed for the Framework Laptop 13 modular laptop

DC-ROMA RISC-V Mainboard is designed for the Framework Laptop 13 modular laptop

DeepComputing DC ROMA RISC V mainboard

DeepComputing’s DC-ROMA RISC-V Mainboard is designed for the modular Framework Laptop 13 and powered by a StarFive JH7110 quad-core RISC-V processor running either Ubuntu 24.04 Desktop or Fedora 41 Linux distribution. The Framework Laptop 13 was initially offered with Intel Core i5-1135G7, Core i7-1165G7, or Core i7-1185G7 processor, but the advantage of a modular laptop is that you can replace components, and that’s exactly what the “DC-ROMA RISC-V Mainboard” does by allowing users/developers to do by switching to a less powerful RISC-V processor for software development. Framework Laptop 13 specifications with DC-ROMA RISC-V Mainboard: SoC – StarFive JH7110 CPU Quad-core 64-bit RISC-V SiFive U74 (RV64GC) processor @ up to 1.5 GHz with 32KB D-Cache, 32KB I-cache Single-core 64-bit RISC-V SiFive S7 (RV64IMAC) monitor core with 16KB I-cache, 8KB DTIM Single-core 32-bit RISC-V SiFive E24 (RV32IMFC) real-time control core with 16KB I-cache Up to 2MB L2 cache GPU – Imagination BXE-4-32 […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

SiFive HiFive Premier P550 RISC-V mini-DTX motherboard

SiFive HiFive Premier P550 is a mini-DTX (203 x 170mm) motherboard powered by a 1.4 GHz ESWIN EIC7700X quad-core RISC-V SiFive P550 SoC with up to 19.95 TOPS of AI performance, and equipped with up to 32GB LPDDR5 memory and a 128GB eMMC flash all soldered on a system-on-module. The motherboard itself features a SATA III connector for data storage, includes an HDMI 2.0 port for 4K video output, a PCIe Gen3 x16 slot (working at x4), two gigabit Ethernet ports, an M.2 Key-E socket to add a WiFi/Bluetooth card, up to five USB interfaces, and more. HiFive Premier P550 specifications: SoC – ESWIN EIC7700X CPU 4x SiFive Performance P550 RV64GC RISC-V cores @ 1.4GHz (up to 1.8GHz when overclocked) with Cortex-A75-class performance 32KB(I) + 32KB(D) L1 Cache 256KB L2 Cache 4MB shared L3 Cache Cache supports ECC (support SECDED) NPU (Not currently supported in software) – Up to 19.95 […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 11 Comments on Microchip PIC64GX is a quad-core 64-bit RISC-V microprocessor for real-time processing

Microchip PIC64GX is a quad-core 64-bit RISC-V microprocessor for real-time processing

Microchip PIC64GX

Microchip has introduced its first 64-bit RISC-V microprocessor family with the PIC64GX pin-to-pin compatible with the company’s PolarFire SoC FPGA devices and designed for edge designs for the industrial, automotive, communications, IoT, aerospace, and defense segments. The PIC6GX MPU supports asymmetric multiprocessing (AMP) to run Linux, real-time operating systems, and bare metal in a single processor cluster with secure boot capabilities. The company further claims the PIC64GX MPU is “the first RISC-V multi-core solution that is AMP capable for mixed-criticality systems”. The first member of the PIC64GX RISC-V family is the PIC64GX1000 microprocessor. Microchip PIC64GX1000 specifications: CPU Quad-core SiFive U54 64-bit five-stage, single-issue, in-order pipeline RISC-V (RV64GC) processor at up to 625 MHz with AMP and deterministic latencies, PMP and MMU units Single-core SiFive E51 64-bit RISC-V (RV64IMAC) monitor processor core at up to 625 MHZ with PMP unit Cache L1 memory subsystem with Single-Error Correct, Double-Error Detect (SECDED) Flexible […]