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Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 7.1 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.1 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.1 release

Linus Torvalds has just released Linux 7.1 on LKML: So it’s only Sunday morning back home, but it’s Sunday afternoon where I am right now, so I’m doing the 7.1 release at the regular time – just not in the regular timezone. This obviously means that the merge window opens tomorrow, but I’ll be in yet another timezone by then, so timing will all be a bit irregular. Normally I try to front-load the merge window and do as much as possible the first few days – this time I’m not sure that will work out with my laptop and a couple of long flights without internet, but I’ve made sure that I have fetched the early pull requests (thank you – you know who you are), so I will be able to do some of it off-line. Anyway, possible slight hiccups in the merge window aside, the news today […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on SiFive introduces RVA23-compliant Performance P570 Gen3 RISC-V core for consumer and AIoT applications

SiFive introduces RVA23-compliant Performance P570 Gen3 RISC-V core for consumer and AIoT applications

SiFive Performance P570 Gen3 Core Complex

SiFive has just launched the SiFive Performance P570 Gen 3 out-of-order RISC-V processor core, compliant with the RVA23 ISA profile, and designed for edge AI, high-end consumer, and commercial IoT applications running Android or enterprise-grade OS. Besides the CPU core, SiFive also provides system IP, such as the RISC-V standard-compliant advanced interrupt architecture (AIA), WorldGuard security, and a second-generation RISC-V standard-compliant IOMMU to build a complete SoC with up to 16x P570 Gen 3 cores. Performance P570 Gen3 specifications: Support for all mandatory RVA23 profile extensions for compatibility with modern operating systems such as Ubuntu 26.04 LTS and Red Hat Enterprise Adds extensions for enhanced security and performance, including Smepmp, Zvkng, Zvksg, Zicfilp, Zicfiss, Zfbfmin, Zvfbfmin, Zvfbfwma, and Zvdot4a8i Third-generation out-of-order core building on earlier P550 Gen1 and P470 Gen2 cores 3-wide, 13-stage fully out–of order execution superscalar pipeline Single 128-bit vector pipeline with dot product extensions Supports multicore coherence […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 6 Comments on Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.0

Linus Torvalds has just released Linux 7.0 on LKML: The last week of the release continued the same “lots of small fixes” trend, but it all really does seem pretty benign, so I’ve tagged the final 7.0 and pushed it out. I suspect it’s a lot of AI tool use that will keep finding corner cases for us for a while, so this may be the “new normal” at least for a while. Only time will tell. Anyway, this last week was a little bit of everything: networking (core and drivers), arch fixes, tooling and selftests, and various random fixes all over the place. Let’s keep testing, and obviously tomorrow the merge window for 7.1 opens. I already have four dozen pull requests pending – thank you to all the early people. Linus This follows the Linux 6.19 release about two months ago, which brought us PCIe link encryption and […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.19

Linus Torvalds has just released Linux 6.19 on the Linux Kernel Mailing List (LKML): No big surprises anywhere last week, so 6.19 is out as expected – just as the US prepares to come to a complete standstill later today watching the latest batch of televised commercials. The betting man would expect them all to be AI-generated, but maybe some enterprising company decides to buck the trend? Doubtful, but there’s always a slight chance. But for anybody outside the US, maybe taking the newest kernel out for a spin instead is an option? I have more than three dozen pull requests for when the merge window opens tomorrow – thank you to all the early maintainers. And as people have mostly figured out, I’m getting to the point where I’m being confused by large numbers (almost running out of fingers and toes again), so the next kernel is going to […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on FOSDEM 2026 schedule – Embedded, RISC-V, Robotics, Rust, Open Hardware, and more

FOSDEM 2026 schedule – Embedded, RISC-V, Robotics, Rust, Open Hardware, and more

FOSDEM 2026 schedule

FOSDEM 2026 will take place on January 31-February 1, with thousands of developers meeting in Brussels to discuss open-source software & hardware projects. The free-to-attend “Free and Open Source Software Developers’ European Meeting” gets more traction every year, and in 2026, there will be at least 1,113 speakers, 1,016 events, 70 tracks, and potentially close to 10,000 attendees. As usual, I’ll create a virtual schedule with sessions most relevant to the topics covered on CNX Software from the “Embedded, Mobile and Automotive” and “Open Hardware and CAD/CAM” devrooms, but also other devrooms, including “RISC-V”, “Robotics and simulation”, and “FOSS on Mobile”, among others. I’m aware some of the talks overlap by a couple of minutes or so… FOSDEM 2026 Day 1 – Saturday, January 31 10:40 – 11:15 – RISC-V Vector optimisations in FFmpeg by Rémi Denis-Courmont FFmpeg is the most versatile multimedia codec and format support library, and was […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 8 Comments on Linux 6.18 LTS release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.18 LTS release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.18

Linus Torvalds has just announced the release of Linux 6.18 on the Linux Kernel Mailing List (LKML), which will likely become the next LTS kernel [update: it’s now official]: So I’ll have to admit that I’d have been happier with slightly less bugfixing noise in this last week of the release, but while there’s a few more fixes than I would hope for, there was nothing that made me feel like this needs more time to cook. So 6.18 is tagged and pushed out. Most of the last-minute fixes are minor fixes to drivers, with some random noise elsewhere (bluetooth, ceph, afs..). Nothing strikes me as standing out, but hey, there’s a shortlog appended if you want to see the details. And this obviously means that the merge window will open tomorrow, and I already have three dozen pull requests pending. Thanks. And as I already mentioned a couple of […]

Posted on by Debashis Das - 3 Comments on Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat UP201 and UP301 Series AI MCUs No BG

Upbeat Technology, in collaboration with SiFive, has introduced UP201 and UP301 always-on AI MCUs for ultra-low-power AI and IoT applications such as wearables, drones, and sensor-based systems. The UP201 is designed for compact, battery-driven devices such as smartwatches, hearing aids, and IoT sensor nodes, whereas the UP301 targets AI and vision-based applications for more complex edge systems such as smart glasses, robotics, and industrial AI equipment. Both chips feature a dual-core RISC-V architecture. The SiFive E21 lightweight core is Always-On (AON), managing continuous low-power sensing, whereas the SiFive E34 performance core activates for higher workloads. The MCUs also integrate a 2.5D GPU and various I/O options. UP201 and UP301 MCU specifications: CPU cores (SiFive Essential RISC-V IP cores) E21 core in Always-On (AON) domain for continuous low-power sensing E34 performance core in the Non-AON domain for higher workloads Up to 400 MHz operating frequency Up to 717 DMIPS performance Near-threshold […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive Intelligence X180 Gen 2 Core Complex

SiFive has just launched its 2nd Generation Intelligence family, featuring five new RISC-V-based products: the new X160 Gen 2 and X180 Gen 2, and upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 processors, all featuring scalar, vector, and matrix processing (XM only) capabilities designed for AI workloads. The original Intelligence X280 64-bit RISC-V CPU was introduced in 2021, following the Intelligence X390 NPU in 2023, and the Intelligence XM Series in September 2024. The X160 Gen 2  (32-bit) and X180 Gen 2 (64-bit) are entry-level AIoT CU cores targeting edge compute and IoT applications for automotive, autonomous robotics, industrial automation, and smart IoT applications. The upgrade models get support for the RVA23 profile and a few other changes. SiFive X160/X180 Gen 2 CPUs Key features and specifications: Scalar processing Intelligence X160 Gen 2 – 32-bit RISC-V ISA (RV32I) Intelligence X180 Gen 2 – 64-bit RISC-V ISA (RV64I) Dual […]