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Renesas RA8M1 is the world’s first Arm Cortex-M85 microcontroller

Renesas RA8M1 Arm Cortex-M85 microcontroller

Renesas RA8M1 is an up to 480 MHz Arm Cortex-M85 microcontroller with Arm Helium technology to improve DSP and machine learning performance on Cortex-M microcontrollers, and delivering up to 6.39 CoreMark/MHz performance using EEMBC’s CoreMark, or over 3,000 CoreMark at 480 MHz. The Arm Cortex-M85 core was first unveiled in April 2022 as a faster Cortex-M7 alternative and new Arm Helium technology that delivers machine learning performance similar to Cortex-M55 application processor. We had some teases about the upcoming Renesas Cortex-M85 in the last year, but the world’s first Cortex-M85 microcontroller is finally here. Renesas RA8M1 key features and specifications: MCU core – Arm Cortex-M85 clocked at 240 to 480 MHz with Helium MVE (M-Profile Vector Extension) with 32KB I/D Caches and 12KB Data Flash Memory & Storage 1MB SRAM with TCM 1MB to 2MB Flash memory External memory interfaces (CS/SDRAM) Camera – 16-bit Capture Engine Unit (CEU) interface Communication […]

Arm Cortex-M85 is faster than Cortex-M7, offers higher ML performance than Cortex-M55

Arm Cortex M85

Arm has introduced a new MCU-class core with the Cortex-M85 core that offers higher integer performance than Cortex-M7, and higher machine learning performance compared to Cortex-M55 equipped with Helium instructions. The new Cortex-M85 core is designed for developers requiring increased performance for their Cortex-M powered products without going to Cortex-A cores, and instead, keeping important features such as determinism, short interrupt latencies, and advanced low-power management modes found in all Cortex-M cores. Arm Cortex-M85 key features and specifications: Architecture – Armv8.1-M Performance efficiency – 6.28 CoreMark/MHz and 3.13/4.52/8.76DMIPS/MHz (1. “ground rules” in the Dhrystone documentation, 2. inlining of functions,  3. simultaneous (”multi-file”) compilation). Bus interfaces AMBA 5 AXI 64-bit Main system bus (compatible with AXI4 IPs) AMBA 5 AHB 32-bit Peripheral bus AMBA 5 AHB 64-bit TCM Access bus (subordinate port) Pipeline – 7-stage (for main integer pipeline) Security Arm TrustZone technology PACBTI extension (Pointer Authentication, Branch Target Identification) helps […]