sifive

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

SiFive Automotive RISC V processor

RISC-V is coming to your car too, with the introduction of SiFive Automotive E6-A, X280-A, and S7-A RISC-V processors designed for automotive applications such as infotainment, cockpit, connectivity, ADAS, and electrification. Those are built on the existing SiFive Essential 6-series E6 32-bit real-time cores, SiFive Intelligence X280 64-bit RISC-V processor with AI extensions, and SiFive S7 64-bit real-time cores (equivalent to Cortex-R7/R8), but adds safety, security, and performance required by the automotive market such as ASIL compliance. Each new core targets specific applications within a vehicle: The SiFive E6-A series will be found in system control boards, hardware security modules (HSMs) and safety islands, as well as standalone in microcontrollers. The SiFive S7-A 64-bit  real-time core is said to be suited to the needs of SoCs with performant safety islands, requiring both low latency interrupt support and the same 64-bit memory space as the main application CPUs. The SiFive X280-A […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 release arm risc-v mips

Linux 5.18 is out! Linus Torvalds has just announced the release on lkml: No unexpected nasty surprises this last week, so here we go with the 5.18 release right on schedule. That obviously means that the merge window for 5.19 will open tomorrow, and I already have a few pull requests pending. Thank you everybody. I’d still like people to run boring old plain 5.18 just to check, before we start with the excitement of all the new features for the merge window. The full shortlog for the last week is below, and nothing really odd stands out. The diffstat looks a bit funny – unusually we have parsic architecture patches being a big part of it due to some last-minute cache flushing fixes, but that is probably more indicative of everything else being pretty small. So outside of the parisc fixes, there’s random driver updates (mellanox mlx5 stands out, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 16 Comments on Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel RISC-V

Intel has just announced a $1 billion fund to support companies bringing innovations and new technologies to the foundry ecosystem. The company says the fund will prioritize investments in “capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures, and advanced packaging technologies.” What’s interesting is that it does not only cover x86 architecture but also Arm and RISC-V, with a focus on the latter, as Intel has just become a Premier member of RISC-V International, and partnered with several companies offering RISC-V solutions including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. Intel’s Open Chiplet Platform Part of the investment will go to the Open Chiplet Platform offering a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. This will allow designers to select the best IP and process technologies for a particular SoC. […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linux 5.16 release

Linus Torvalds has just announced the release of Linux 5.16: Not a lot here since -rc8, which is not unexpected. We had that extra week due to the holidays, and it’s not like we had lots of last-minute things that needed to be sorted out. So this mainly contains some driver fixes (mainly networking and rdma), a cgroup credential use fix, a few core networking fixes, a couple of last-minute reverts, and some other random noise. The appended shortlog is so small that you might as well scroll through it. This obviously means that the merge window for 5.17 opens tomorrow, and I’m happy to say I already have several pending early pull requests. I wish I had even more, because this merge window is going to be somewhat painful due to unfortunate travel for family reasons. So I’ll be doing most of it on the road on a laptop […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on Sifive Essential 6-Series RISC-V processors target Linux, real-time applications

Sifive Essential 6-Series RISC-V processors target Linux, real-time applications

SiFive E6 vs S6 Block Diagram

SiFive has been busy. Just a few days after SiFive Performance P650 announcement, the company has announced the SiFive Essential 6-Series RISC-V processor family starting with four 64-bit/32-bit real-time core, and two Linux capable application cores, plus the SiFive 21G3 release with various improvements to existing families. SiFive Essential 6-Series range of RISC-V processors There Essential 6-Seris family is comprised of three sub-families with two processors each: E6 Series with 1.91 DMIPS/MHz, 3.69 CoreMark/MHz E61-MC – Quad-core 32-bit embedded processor E61 – Mid-range performance 32-bit embedded processor (one-core) S6 Series with 2.07 DMIPS/MHz, 3.73 CoreMark/MHz S61-MC – Quad-core 64-bit embedded processor S61 – Mid-range performance 64-bit embedded processor (one-core) U6 Series with 2.07 DMIPS/MHz, 3.73 CoreMark/MHz U64-MC – Quad-core 64-bit application processor U64 – Mid-range performance Linux-capable processor (one-core) E6-Series and S6 Series real-time processors have practically the same features except for the 32-bit and 64-bit cores, and a different […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 20 Comments on SiFive Performance P650 RISC-V core to outperform Arm Cortex-A77 performance per mm2

SiFive Performance P650 RISC-V core to outperform Arm Cortex-A77 performance per mm2

SiFive Performance P650

About six months have passed since the SiFive announcement of the Performance P550 “fastest 64-bit RISC-V processor” ever, and the company has now introduced an even faster RISC-V core with the Performance P650 that’s expected to match Cortex-A77 performance. Building upon the Performance P550 design, the SiFive Performance P650 is scalable to sixteen cores using a coherent multicore complex, and delivers a 40% performance increase per clock cycle based on SiFive engineering estimated performance in SPECInt2006/GHz, thanks to an expansion of the processor’s instruction-issue width. The company compares P650 to the Arm family by saying it “maintains a significant performance-per-area advantage compared to the Arm Cortex-A77”. SiFive Performance P650 key features: 64-bit RISC-V (RV64GCB) core Sv39/Sv48 Virtual Memory Support Multi-core, multi-cluster processor configurations with up to 16 cores Performance > 11 SpecINT2006/GHz Thirteen stage, four-issue, out-of-order pipeline tuned for scalable performance Private L2 Caches and Streaming Prefetcher for improved memory […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 13 Comments on Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards

Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards

Ubuntu RISC-V HiFive QEMU

Let’s a lot of excitement around RISC-V open architecture, but a lot of work still needs to be done to bring the ecosystem to level with Arm or x86 architecture from the silicon to the software. Progress is made step-by-step and one of these steps is Canonical released Ubuntu 64-bit RISC-V (RISCV64) images for some of SiFive HiFive boards, as well as QEMU open-source emulator. Specifically, Canonical released an Ubuntu 20.04.2 LTS image for HiFive Unleashed & QEMU, and an Ubuntu 21.04 image for HiFive Unleashed, HiFive Unmatched, and QEMU. Note those are only server images, and there’s no desktop image yet like for Ubuntu 21.04 on Raspberry Pi 2/3/4. It’s been possible to run RISC-V Linux in QEMU for at least three years, but when I tried it was a minimal system based on Busybox, so let’s try again with Ubuntu 21.04 following the instructions provided on Discourse. I […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 22 Comments on SiFive Performance P550 is the fastest 64-bit RISC-V processor so far

SiFive Performance P550 is the fastest 64-bit RISC-V processor so far

SiFive Performance P550 fastest RISC-V processor

SiFive has announced two RISC-V “Performance” cores with Performance P550 that should be the fastest 64-bit RISC-V processor so far with a SPECInt 2006 score of 8.65/GHz, as well as a Performance P270 Linux capable processor with full support for the RISC-V vector extension v1.0 rc. SiFive Performance P550 P550 highlights: RISC-V RV64GBC ISA 13 stage, 3-issue high-performance out-of-order pipeline Supports multicore coherence with up to 4 cores in a core complex Private 32KB+32KB L1 cache and a private 256KB L2 cache per core Up to 4MB L3 cache in a four-core cluster SPECint 2006 – 8.65/GHz 2.4 GHz in 7nm with a footprint of less than 0.25 mm SiFive compares the Performance P550 core to Arm’s Cortex-A75 with higher performance in SPECint2006 and SPECfp2006 integer/floating-point benchmark, all a much smaller area which would enable a quad-core P550 cluster on about the same footprint as a single Cortex-A75 core. There […]

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