This Micro-ATX Motherboard is Based on Phytium FT2000/4 Arm Desktop Processor @ 3.0 GHz

Arm Micro-ATX Desktop PC Motherboard

There have been attempts to bring Arm processors to desktop PC’s in recent years with projects such as 96Boards Synquacer based on SocioNext SC2A11 24-core Cortex-A53 server processor or Clearfog-ITX workstation equipped with the more powerful NXP LX2160A 16-core Arm Cortex A72 networkingprocessor @ 2.2 GHz. Those solutions were also based server and networking SoCs, but there may soon be another option specifically designed for Arm Desktop PCs as a photo of an Arm Micro-ATX motherboard just showed up on Twitter. Here are the specifications we derive from the Tweet and the photo: SoC – Phytium FT2000/4 quad core custom Armv8 (FTC663) desktop processor @ 2.6 – 3.0 GHz with 4MB L2 Cache (2MB per two cores) and 4MB L3 Cache; 16nm process; 10W power consumption; 1144-pin FCBGA package (35×35 mm) System Memory – 2x SO-DIMM slot supporting 72-bit (ECC) DDR4-3200  memory Storage – 4x SATA 3.0 connectors; MicroSD card slot Video Output – N/A – Discrete PCIe graphics card …

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Amazon Unveils EC2 A1 Arm Bare Metal Instances

AWS A1 Baremetal Arm Instances

A1 ARM Instances Amazon had first released its 64-bit ARM EC2 A1 Instances back in 2018, which are part of AWS Elastic Compute Cloud (EC2), an ever-evolving virtual platform that supports business subscribers utilizing applications in the cloud.  Arm Bare Metal Instances The most recent launch is the EC2 A1 ARM Bare Metal Instances, which Amazon is reporting is similar to the previous version of A1 ARM Instances, but with greater reach within the ARM ecosystem. The Servers The new EC2 A1 Arm instances are powered by the AWS Graviton Processors, featuring the 64-bit Arm Neoverse with custom silicon developed by AWS.  Features Include Amazon Machine Images (AMI) Elastic Block Store (EBS) Auto Scaling Applications can have  more direct access to the processor and memory resources within the underlying server.  Some of the different types of scale-out applications the new Instances support and will enhance are – Application Types Web Servers Containerized Microservices Caching Fleets Distributed Data Stores A1 Arm …

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PiPo Snapdragon 850 2-in-1 Laptop to Sell for around $400

PiPo Snapdragon 850 Laptop

Current Qualcomm based Windows 10 laptops are mostly interesting for people wanting all-day battery life and/or being always connected over 4G LTE, as they are still pretty expensive, and performance somewhat underwhelming, although Snapdragon 8cx processor should change that. Chinese-based PiPo, known for their tablets,  mini PCs and Arm Android laptops, is working on solving affordability of Arm Windows 10 laptop with their Snapdragon 850 2-in-1 laptop, heavily inspired by Huawei MateBook E 2019, and expected to sell for half the price or around $400. PiPo 2-in-1 laptop preliminary specifications: SoC – Qualcomm Snapdragon 850 octa-core Kryo 385 Arm cores clocked @ up to 2.96 GHz with Adreno 630 Visual Processing Subsystem, Hexagon 685 DSP Systmem Memory – 8GB RAM Storage – 256GB flash storage Display – 12.3″ IPS display with 3000×2000 resolution, 10-point touch Audio – 3.5mm audio jack, Connectivity – WiFi 5 802.11ac/b/g/n + 4G LTE Camera – 5.0MP front-facing camera. 13MP rear camera USB – 1x USB …

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Arm Custom Instructions Coming to Armv8-M Embedded Processors

Arm Custom Instructions

So far Arm defined all instructions for their cores with the benefit of code portability between solutions, so code compiled for an Arm Cortex-M33 based microcontroller would run on another without modifications (we’re obviously talking about code running directly on the core, not using specific peripherals here). But with RISC-V open-source architecture many have seen the benefit of custom instructions for specific tasks, at the risk of potential fragmentation. With Arm Techcon 2019 now taking place, Arm has just announced support for custom instructions for ARMv8-M embedded CPUs starting with Arm Cortex-M33 cores. The implementation of Arm Custom Instructions for specific embedded and IoT applications will start in H1 2020 at no additional cost to licensees and without risk of software fragmentation using NOCP exception if the instructions are not available. Arm futher explains: Arm Custom Instructions are enabled by modifications to the CPU that reserve encoding space for designers to easily add custom datapath extensions while maintaining the integrity …

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ctxLink Open Hardware WiFi Debug Probe is based Black Magic Probe (Crowdfunding)

ctxlink

Last month, we wrote about Blip nRF52840 dev board that also included an STM32F103 MCU running the open source Black Magic Probe (BMP) firmware for debugging and programming. Based on the original Black Magic Probe hardware product page, BMP is a JTAG and SWD adapter used for programming and debugging ARM Cortex MCUs, and does not require intermediate programs such as OpenOCD or STLink server. Instead, you can run GNU Debugger (GDB) and select the virtual COM port offered by the debug board. The reason I’m bringing BMP again today, is because a new open source hardware wireless debugging probe for Cortex-M based on Black Magic Probe has been launched in the last few days. ctxLink key features and specifications: Microcontroller – STMicro STM32F401RE Arm Cortex -M4F MCU at up to 84 MHz Connectivity – 802.11b/g/n WiFi via Microchip WINC1500 module USB – 1x micro USB port for connection to host computer and/or power Debugging Features Implements SWD and JTAG …

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Linux 5.3 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linux 5.3 Changelog

Linus Torvalds has just announced the release of Linux 5.3: So we’ve had a fairly quiet last week, but I think it was good that we ended up having that extra week and the final rc8. Even if the reason for that extra week was my travel schedule rather than any pending issues, we ended up having a few good fixes come in, including some for some bad btrfs behavior. Yeah, there’s some unnecessary noise in there too (like the speling fixes), but we also had several last-minute reverts for things that caused issues. One _particularly_ last-minute revert is the top-most commit (ignoring the version change itself) done just before the release, and while it’s very annoying, it’s perhaps also instructive. What’s instructive about it is that I reverted a commit that wasn’t actually buggy. In fact, it was doing exactly what it set out to do, and did it very well. In fact it did it _so_ well that …

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How to Sandbox an arm64 GCC on aarch64 Hardware with armv7 Userspace

Arm64 GCC Armv7 Userspace

CNXSoft: Guest post by Blu about setting up arm64 toolchain on 64-bit Arm hardware running a 32-bit Arm (Armv7) rootfs. Life is short and industry progress is never fast enough in areas we care about. That’s an observation most of us are familiar with. One would think that by now most aarch64 desktops would be running arm64 environments, with multi-arch support when needed. Alas, as of late 2019, chromeOS on aarch64 is still shipping an aarch64 kernel and an armhf userspace. And despite the fine job by the good folks at chromebrew, an aarch64 chromeOS machine in dev mode ‒ an otherwise excellent road-warrior ride, is stuck with 32-bit armhf. Is that a problem, some may ask? Yes, it is ‒ aarch64 is the objectively better arm ISA outside of MCUs, from gen-purpose code to all kinds of ISA extensions, SIMD in particular. That shows in contemporary compiler support and in the difference in quality of codegen. Particularly with the …

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AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets

Andes N22 RISC-V vs Arm Cortex M3 / M0+

We covered Gigadevice GD32V general-purpose microcontroller with a RISC-V “Bumblebee” core last week, and I was informed that Andes Technology had recently introduced AndesCore N22 RISC-V “Bumblebee” IP core capable of supporting either RV32IMAC or RV32EMAC instruction sets. A web search did not reveal any specific information about what “Bumblebee” RISC-V cores are exactly, or maybe it’s in reference that many can be coupled in parallel. But that’s just a small detail, let’s check out in some details what AndesCore N22 core has to offer. The RISC-V core is designed for entry-level MCUs found in IoT devices and wearables, and is capable of deeply embedded protocol processing for I/O control, storage, networking, AI and AR/VR. Highlights of AndesCore N22: AndeStar V5 (RV32IMAC) / V5e (RV32EMAC) Instruction Set Architecture (ISA), compliant to RISC-V technology plus Andes extensions architectured for performance and functionality enhancements 32-bit, 2-stage pipeline CPU architecture 16/32-bit mixable instruction format for compacting code density Branch prediction to speed up …

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