Cadence Neo NPU (Neural Processing Unit) IP delivers 8 GOPS to 80 TOPS in single core configuration and can be scaled to multicore configuration for hundreds of TOPS. The company says the Neo NPUs deliver high AI performance and energy efficiency for optimal PPA (Power, Performance, Area) and cost points for next-generation AI SoCs for intelligent sensors, IoT, audio/vision, hearables/wearables, mobile vision/voice AI, AR/VR and ADAS. Some highlights of the new Neo NPU IP include: Scalability – Single-core solution is scalable from 8 GOPS to 80 TOPS, with further extension to hundreds of TOPS with multicore Supports 256 to 32K MACs per cycle to allow SoC architects to meet power, performance, and area (PPA) tradeoffs Works with DSPs, general-purpose microcontrollers, and application processors Support for Int4, Int8, Int16, and FP16 data types for CNN, RNN and transformer-based networks. Up to 20x higher performance than the first-generation Cadence AI IP, with […]
Cadence Neo NPU IP scales from 8 GOPS to 80 TOPS
