fpga

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on Embedded development board features Microchip PolarFire RISC-V FPGA SoC

Embedded development board features Microchip PolarFire RISC-V FPGA SoC

PolarFire RISC-V FPGA SoC development board

Microchip/MicroSemi first introduced PolarFire RISC-V FPGA SoC at the end of 2018, with the chip being like the RISC-V equivalent of Xilinx Zynq Ultrascale+ Arm & FPGA MPSoC. The following year, ARIES Embedded unveiled the ARIES M100PF system-on-module and evaluation board, before Microchip launched PolarFire SoC Icicle 64-bit RISC-V and FPGA development board, followed by the more compact PolarBerry SBC in 2020. There’s now at least a fourth platform based on PolarFire SoC with Aldec TySOM-M-MPFS250 embedded development board.   Aldec TySOM-M-MPFS250 specifications: SoC – Microchip PolarFire MPFS250T-FCG1152 SoC  with 4x SiFive U54 RV64GC application cores (similar to Cortex-A35 performance), 1x SiFive E51 RV64IMAC monitor core, FPGA fabric with 254K logic cells, 17.6 Mb RAM System Memory 2GB (16Gbit) 32-bit DDR4 for the FPGA 2GB (16Gbit) 36-bit RAM with ECC for the RISC-V cores (aka MSS = Microprocessor Subsystem) Storage – MicroSD card socket, eMMC flash, SPI flash, 64 Kbit […]

Posted on by Saumitra Jagdale - No Comments on Xilinx announces Versal AI Edge Series with Cortex-A72 & R5 cores, FPGA fabric

Xilinx announces Versal AI Edge Series with Cortex-A72 & R5 cores, FPGA fabric

Xilinx Versal AI Edge

Edge AI solves the latency and security issues through on-device AI acceleration for optimal computations at a low power supply. Xilinx announces its Versal AI Edge Series which is 4th member of the Adaptive Compute Acceleration Platform (ACAP) family. The versal series consists of seven models ranging from VE2002 to VE2802 with the processor fabrication on 7 nm silicon technology. Talking more about ACAP, it is a platform that provides a combined essence of a processor and FPGA. The processing features efficient memory and I/Os, whereas programmable arrays allow logical control over the hardware. Also, as Xilinx specializes in FPGA products, the additional support of computational features makes the ACAP hardware even more flexible and dynamic. The Versal AI Edge series features different types of engines for specific functionalities in terms of adaptable, scalar, and intelligent engines. The seven processor models vary with respect to engine and platform specifications. However, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Mercury+ XU6 Xilinx Zynq UltraScale+ module is optimized for I/O-intensive applications

Mercury+ XU6 Xilinx Zynq UltraScale+ module is optimized for I/O-intensive applications

Mercury-XU6 Zynq Ultrascale+ SoM

Enclustra, a company headquartered in Switzerland specializing in FPGA solutions, has recently announced the launch of the Mercury+ XU6 system-on-module based on Xilinx Zynq UltraScale+ MPSoC. The module is optimized for I/O-intensive applications with up to 294 user I/Os, up to eight 6/12.5 Gbps multi-gigabit transceivers, and available with six different variants of Xilinx MPSoC. The company also offers Mercury+ ST1 and PE1 baseboards for evaluation and early software development. Mercury+ XU6 SoM Key features and specifications: SoC – Xilinx Zynq Ultrascale+ MPSoC (ZU2CG, ZU2EG, ZU3EG, ZU4CG, ZU4EV, or ZU5EV) with: CPU ARM dual-/quad-core Cortex-A53 processor  up to 1333 MHz ARM dual-core Cortex-R5 up to 533 MHz GPU – Mali-400MP2 GPU (only for EG/EV variants) Video Codecs – H.264 / H.265 Video Codec (only for EV variants) FPGA fabric – Up to 256,000 system logic cells System Memory – Up to 8 GB DDR4 ECC SDRAM (PS side) Storage – […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Xilinx Introduces Kria K26 SoM and vision AI devkit based on Zynq Ultrascale+ XCK26 FPGA MPSoC

Xilinx Introduces Kria K26 SoM and vision AI devkit based on Zynq Ultrascale+ XCK26 FPGA MPSoC

Kria V260 Vision AI Starter Kit

Silicon vendors will usually focus on chip design, and provide an expensive evaluation kit to early customers, leaving the design of cost-optimized boards and system-on-modules to embedded systems companies. But Xilinx has decided to enter the latter market with the Kria portfolio of adaptive system-on-modules (SOMs) and production-ready small form factor embedded boards starting with Kria K26 SoM powered by Zynq UltraScale+ XCK26 FPGA MPSoC with a quad-core Arm Cortex-A53 processor, up to 250 thousand logic cells, and a H.264/265 video codec designed for Edge AI applications, as well as computer vision development kit. Kria K26 System-on-Module Kria K26 module specifications: MPSoC – Xilinx Zynq Ultrascale+ custom-built XCK26 with quad-core Arm Cortex-A53 processor  up to 1.5GHz, dual-core Arm Cortex-R5F real-time processor up to 600MHz, Mali-400 MP2 GPU up to 667MHz, 4Kp60 VPU, 26.6Mb On-Chip SRAM, 256K logic cells, 1,248 DSP slices System Memory – 4GB 64-bit DDR4 (non-ECC) Storage – […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on The OSFPGA Foundation aims to promote open-source FPGA tools and IP blocks

The OSFPGA Foundation aims to promote open-source FPGA tools and IP blocks

OSFPGA

There are been some initiatives to work on open-source tools for FPGA. Major FPGA vendors have made limited efforts, with for example Xilinx recently releasing the source code for HLS FPGA tool’s front-end, but most of the work is done by the community with projects like Symbiflow dubbed the GCC of FPGAs, or Project IceStorm for Lattice Semi FPGAs. Industry veterans and academics have decided to launch the Open-Source FPGA (OSFPGA) Foundation that aims to bring together companies, universities, and individuals to advance open-source FPGA capabilities, establish cooperation channels, promote outreach and education, and coordinate joint efforts around an open-source FPGA ecosystem. The OSFPGA Foundation goals go beyond just providing open-source tools, as the vision statement also mentions “open-source FPGA & eFPGA fabrics”, the Github page also includes IP blocks with the FuseSoC package manager for IP cores, the Skywater Open-source FPGAs, and LiteDRAM lightweight, configurable DRAM core. Current board […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Sparkfun Thing Plus – Quicklogic EOS S3 Arm eFPGA board launched in Crowd Supply

Sparkfun Thing Plus – Quicklogic EOS S3 Arm eFPGA board launched in Crowd Supply

Sparkfun Thing Plus Quicklogic EOS S3

SparkFun Electronics is a well-known electronics retailer that usually sells its in-house developed or third-party boards through its own online store. But this time around, the company decided to launch “Sparkfun Thing Plus – Quicklogic EOS S3” through Crowd Supply crowdfunding platform. The board is based on QuickFeather board designed with the same Quicklogic EOS S3 Arm Cortex-M4 plus embedded FPGA SoC, but follows Sparkfun’s Thing Plus form factor with a Qwiic connector and a different mix of sensors. Sparkfun Thing Plus – Quicklogic EOS S3 (QTPLUS-1.0) board specifications: SoC – QuickLogic EOS S3 MCU + eFPGA SoC with Arm Cortex-M4F Microcontroller up to 80 MHz, up to 512 Kb SRAM, and an embedded FPGA (eFPGA) with 2400 effective logic cells, 64 Kb RAM Storage – 16 Mbit SPI NOR flash (GigaDevice GD25Q16CEIGR) Sensors STMicro LIS2DH12TR accelerometer Digital pulse density modulation (PDM) microphone with Wake-on-Sound (WoS) feature: Vesper VM3011-U1 Expansion […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Xilinx open sources Vitis HLS FPGA tool (Front-end only)

Xilinx open sources Vitis HLS FPGA tool (Front-end only)

Vitis HLS software architecture

While there are some open-source programs for FPGA development such as Symbiflow or Yosys, FPGA vendors usually only provide closed-source programs for developers wanting to work on their chips. But Xilinx has recently made a move to fulfill its “commitment to supporting open-source initiatives for developers and researchers” with the release of the source code of Vitis HLS Front-End. What is Vitis HLS exactly? Before we look at the source code release, we may want to know what Vitis HLS does exactly. The company describes it as a high-level synthesis (HLS) tool that allows C, C++, and OpenCL functions to become hardwired onto the device logic fabric and RAM/DSP blocks. It implements hardware kernels in the Vitis application acceleration development flow, and to use C/C++ code for developing RTL IP for FPGA designs in the company’s Vivado Design Suite. Vitis HLS design flow goes as follows: Compile, simulate, and debug […]

Posted on by Saumitra Jagdale - No Comments on CN0549 CBM development kit monitors assets through vibration analysis

CN0549 CBM development kit monitors assets through vibration analysis

CN0549 CBM Development Kit interfaced with SMA Connector

Condition Based Monitoring (CBM) has become quite popular in the manufacturing sector due to its advantages. It is a type of pre-analysis monitoring that includes the use of sensors to evaluate the status of an asset over time while it is in operation. Hence, the data collected is used to establish trends, predict failure, and measure the life of an asset. Analog Devices has launched CN0549, a condition-based monitoring development kit. The monitoring functionality signifies the consideration for hardware applications involving vibration. The applications include industrial as well as IoT devices. Hence, the CN0549 CBM development board combines the resources for a dynamic domain of users. Discussing further, condition-based monitoring (CBM) through vibration sensing requires the capturing of full-bandwidth data to ensure that all harmonics, aliasing, and other mechanical interactions are taken care of in both, the time and frequency domain. The data collection by using the sensors and data […]