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Posts Tagged ‘imagination’

Synaptics Introduces VideoSmart BG5CT 4K HDR Multimedia Video Processor for Set-Top Boxes

October 23rd, 2017 1 comment

Marvell used to design Media SoCs running Android TV such as ARMADA 1500 Ultra (aka BG4CT). That part of Marvell business has very recently been sold to Synaptics, which has just unveiled VideoSmart BG5CT multimedia SoC with 4K “Advanced” HDR video processing for the set-top-box market.

The BG5CT is said to be pin-to-pin compatible with BG4CT Android TV SoC, features a quad core ARM CPU @ 1.6 GHz with 15K DMIPS, an Imagination PowerVR Series8XE GE8310 GPU, and a security engine enabling secure boot, Trusted Rendering Path, full TrustZone, and video watermarking carrier-grade security making it suitable for Pay TV operators and set-top-box manufacturers.

Synaptics’ Qdeo video processing technology adds 4K “Advanced HDR” – including HDR10, HLG, Dolby Vision, and Technicolor HDR, among user video processing technology. The company did not provide that many details, but BG5CT appears to mostly add HDR support compared to BG4CT, and replace Vivante GC7000 GPU by PowerVR GE8310.

Primary SDKs for BG5CT will include Android TV and RDK. We can expect the new SoC to be found in “operator tier” Android TV set-top boxes with a custom launcher, and designed to handle Pay TV services from a specific provider.Visit the product page for (not that many) more details.

Imagination Announces PowerVR Series2NX Neural Network Accelerator (NNA), and PowerVR Series9XE and 9XM GPUs

September 21st, 2017 3 comments

Imagination Technologies has just made two announcements: one for their PowerVR Series2NX neural network accelerator, and the other for the new high-end GPU families: PowerVR Series9XE and 9XM.

PowerVR Series2NX neural network accelerator

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The companies claims 2NX can deliver twice the performance and half the bandwidth of nearest competitor, and it’s the first dedicated hardware solution with flexible bit-depth support from 16-bit down to 4-bit.

Key benefits of their solution (based on market data available in August 2017 from a variety of sources) include:

  • Highest inference/mW IP cores to deliver the lowest power consumption
  • Highest inference/mm2 IP cores to enable the most cost-effective solutions
  • Lowest bandwidth solution with support for fully flexible bit depth for weights and data including low bandwidth modes down to 4-bit
  • 2048 MACs/cycle in a single core, with the ability to go to higher levels with multi core

The PowerVR 2NX NNA is expected to be found in smartphone and other mobile devices leveraging Tensorflow Lite and API for Android, as well as Caffe2Go framework, smart surveillance cameras, assisted and autonomous driving solutions, and home entertainment with TVs and set-top boxes using artificial intelligence to adapt preferences to certain users. NNA will find their ways in more and more SoC as shown in the diagram below by Imagination showing the evolution of SoCs over the years, and this has already started as we’ve seen with Huawei Kirin 970 mobile SoC featuring its own neural processing unit (likely not 2NX though).

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PowerVR 2NX development resources include mapping and tuning tools, sample networks, evaluation tools and documentation leveraging industry standard machine learning frameworks such as Caffe and Tensorflow. The Imagination DNN (Deep Neural Network) API, working across multiple SoC configuration, should ease transition between CPU, GPU and NNA.

PowerVR 2NX NNA is available for licensing now which should mean products with the solution possibly coming sometimes in 2018. Some more details about 2NX can be found in a blog post and the product page.

PowerVR Series9XE and 9XM GPUs

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The Series9XE GPU family is an up to the previous generation Series8XE family with the same fill-rate density, but improved application performance of up to 20%, with the GPU expected to be used in cost-sensitive products such as digital TVs, set-top boxes, streaming sticks/dongles, and entry-level to mid-range mobiles and tablets.

The Series9XM family improve performance by up to 50% over the Series8XEP family with increased compute density, and should be found in premium set-top boxes, mid-range smartphones, tablets and automotive ADAS applications.

Both families benefit from improvements in the memory subsystem, reducing bandwidth by as much as 25%, include a new MMU, standard support for 10-bit YUV, and are suitable for 4K output/displays.

Some of the key benefits of the new Series9XE/9XM family include:

  • Performance/mm2
    • 9XE GPUs’ improved gaming performance while maintaining the same fillrate density compared to the previous generation
    • 9XM GPUs’ several new and enhanced architectural elements enable up to 70% better performance density than the competition (as of August 2017), and up to 50% better than the previous 8XEP generation
  • Bandwidth savings of up to 25% over the previous generation GPUs through architectural enhancements including parameter compression and tile grouping
  • Memory system improvements: 36-bit addressing for improved system integration, improved burst sizes for efficient memory accesses, and enhanced compression capabilities
  • Low power consumption thanks to  Imagination’s Tile Based Deferred Rendering (TBDR) technology
  • Support for hardware virtualization and Imagination’s OmniShield multi-domain security, enabling customers to build systems in which applications and operating systems can run independently and reliably on the same platform
  • Support for Khronos graphics APIs: OpenGL ES 3.2, and Vulkan 1.0
  • Support for advanced compute and vision APIs such as RenderScript, OpenVX 1.1 and OpenCL 1.2 EP
  • Optional support for PVRIC3 PowerVR lossless image compression technology

The company also explains the Series9XE/9XM GPU are ideal for use with the new PowerVR 2NX Neural Network Accelerator, which means NNA’s will not only be found in premium devices, but also in entry level and mid range products.

The IP is available for licensing now with four Series9XE GPU IP cores:

  • 1 PPC with 16 F32 FLOPS/clock(GE9000)
  • 2 PPC with 16 F32 FLOPS/clock (GE9100)
  • 4 PPC with 32 F32 FLOPS/clock (GE9210)
  • 8 PPC with 64 F32 FLOPS/clock (GE9420)

and three Series9XM GPU IP cores:

  • 4 PPC with 64 FP32 FLOPS/clock (GM9220)
  • 4 PPC with 128 FP32 FLOPS/clock (GM9240)
  • 8 PPC with 128 FP32 FLOPS/clock (GM9240)

Visit the product page for more details about the new PowerVR GPU families.

Imagination PowerVR “Furian” Series8XT GT8525 GPU Targets High-end Smartphones, Virtual Reality and Automotive Products

May 11th, 2017 No comments

Imagination Technologies has unveiled their first GPU based on PowerVR Furian architecture with Series8XT GT8525 GPU equipped with two clusters and designed for SoCs going to into products such as high-end smartphones and tablets, mid-range dedicated VR and AR devices, and mid- to high-end automotive infotainment and ADAS systems.

Block Diagram for PowerVR Furian GT8525 GPU – Click to Enlarge

The Furian architecture is said to allow for improvements in performance density, GPU efficiency, and system efficiency, features a new 32-wide ALU cluster design, and can be manufactured using sub-14nm (e.g. 7nm process once available). PowerVR GT8525 GPU supports compute APIs such as OpenCL 2.0, Vulkan 1.0 and OpenVX 1.1.

Compared to the previous Series7XT GPU family, Series8XT GT8525 GPU delivers 80% higher fps in Trex benchmark, an extra 50% fps in GFXbench Manhattan benchmark, 50% higher fps in Antutu, doubles the fillrate throughput for GUI, and increases GFLOPs for compute applications by over 50%.

GT8525 GPU is available for licensing now, and has already been delivered to lead customers. More details should eventually surface on PowerVR Series8XT Core page.

Imagination PowerVR G6230 is the First GPU To Pass Khronos OpenVX 1.1 Conformance

December 19th, 2016 3 comments

The Khronos Group is the non-profit consortium group behind open standards and APIs for graphics, media and parallel computation such as OpenGL for 3D graphics, OpenCL for GPGPU, OpenVG for 2D vector graphics, etc… OpenVX is one of their most recent open, royalty-free standard, and targets power optimized acceleration of computer vision applications such as face, body and gesture tracking, smart video surveillance, advanced driver assistance systems (ADAS), object and scene reconstruction, augmented reality, visual inspection, robotics and more. The first revision of the standard was released in 2014, and the latest OpenVX 1.1 revision was just released in May 2016.

allwinner-a80-powervr-openvxWe’ve already seen OpenVX 1.1 support in Nvidia Jetson TX1 module & board, but Khronos has a conformance program to test  implementations, and if successful, allow companies to use the logo and name of the API. The version first GPU to pass OpenVX 1.1 conformance is Imagination Technologies PowerVR G6230 using an Allwinner A80 hardware platform and Imagination’s OpenVX DDK. OpenVX 1.1 is said to “expands node functionality and enhances graph framework” compared to OpenVX 1.0.

openvx-framework

OpenVX Framework Efficiency

Imagination Technologies also has a blog post with further details including a comparison between OpenCV open source software and OpenVX.

Actions Semi S900VR & V700 Processors are Designed for Virtual Reality Headsets

November 1st, 2016 2 comments

Earlier this summer, Actions Semi has announced two quad core ARM Cortex A53 SoC designed for virtual reality applications, S900VR with a PowerVR G6230 GPU for higher-end 2K headsets, and V700 with a ARM Mali-450MP GPU for mid-range Android VR headsets with Full HD displays.

actions-semi-s900vr-virtual-reality-soc

Actions Semi S900VR specifications and key features:

  • CPU – Quad-core 64-bit ARM Cortex-A53 processor
  • GPU – Imagination PowerVR G6230 with support for OpenGL ES1.1/2.0/3.0/3.1, OpenGL 3.2, OpenCL 1.2EP, DirectX10
  • Memory I/F – Dual channels DDR3/DDR3L/LPDDR2/LPDDR3
  • Storage I/F – SLC/MLC/TLC NAND, eMMC 4.5, SDIO 3.0
  • Video decode – HEVC/H.265 up to 4K
  • Video encode – H.264 1080p video encoding
  • Display – MIPI-DSI, LVDS, and eDP1.3 interfaces up to 2560×[email protected]
  • HDMI – HDMI 1.4b up to 4K and MHL 2.1
  • Camera sensor – MIPI-CSI2 interface up to 13M cameras
  • Power – ATC260x companion chip with embedded PMU and Audio Codec
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Actions Semi V700 Block Diagram – Click to Enlarge

V700 VR processor specifications:

  • CPU – Quad-core 64-bit ARM Cortex-A53 processor
  • GPU – ARM Mali-450 MP6 with support for OpenGL ES2.0/1.1, OpenVG 1.1, EGL 1.5
  • Memory I/F – DDR3/DDR3L/LPDDR2/LPDDR3, up to 4GB
  • Storage I/F – SLC/MLC/TLC NAND, eMMC 4.5, SDIO 3.0
  • Video decode – HEVC/H.265 up to 4K @ 30 fps
  • Video encode – H.264 1080p video encoding
  • Display – MIPI-DSI & LVDS interfaces up to 1920×[email protected]
  • HDMI – HDMI 1.4b up to 4K
  • Camera sensor – MIPI-CSI2 interface up to 12M cameras
  • Power – ATC260x companion chip with embedded PMU and Audio Codec

While the processors were announced in July, I found out about them about an Imagination press release mentioning Actions Semi, Imagination Technologies, and Nanjing Ruiyue Technology – better known as Nibiru – had partnered to released a 2K Android virtual reality kit running Nibiru OS powered by Actions Semi S900VR processor with sub 20ms latency.

You may want to visit Actions Semiconductor S900VR and V700 product pages for maximum confusion as both mentions 4K display support, contradicting the press release.

Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

October 13th, 2016 No comments

Imagination has just unveiled the successor of MIPS I6400 64-Bit Warrior Core with MIPS Warrior I-class I6500 heterogeneous CPU supporting up to 64 cluster, with up to 6 cores each (384 cores max), themselves up to 4 thread (1536 max), combining with IOCU (IO coherence units), and external IP such as PowerVR GPU or other hardware accelerators.

mips-i6500-scalable-computeThe main features of MIPS I6400 processor are listed as follows:

 

  • Heterogeneous Inside – In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels.
  • Heterogeneous Outside – The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system efficiency.
  • Simultaneous Multi-threading (SMT) – Based on a superscalar dual issue design implemented across generations of MIPS CPUs, this  feature enables execution of multiple instructions from multiple threads every clock cycle, providing higher utilization and CPU efficiency.
  • Hardware virtualization (VZ) – I6500 builds on the real time hardware virtualization capability pioneered in the MIPS I6400 core. Designers can save costs by safely and securely consolidating multiple CPU cores with a single core, save power where multiple cores are required, and dynamically and deterministically allocate CPU bandwidth per application.
  • SMT + VZ – The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, makes the I6500 ideal for applications which require deterministic code execution.
  • Designed for compute intensive, data processing and networking applications – The I6500 is designed for high-performance/high-efficiency data transfers to localized compute resources with data scratchpad memories per CPU, and features for fast path message/data passing between threads and cores.
  • OmniShield-ready – Imagination’s multi-domain security technology used across its processing families enables isolation of applications in trusted environments, providing a foundation for security by separation.

The processor is also based on the standard MIPS ISA, so developer will be able to leverage existing software and tools such as compilers, debuggers, operating systems, hypervisors and application software already optimized for the MIPS ISA.

mips-i6500-soc

 

The figure above shows what an SoC based on MIPS I6500 may look like with one cluster with 4 CPU cores, 2 IOCUs, another cluster with any CPU cores but instead eight IOCUs interlinked with third party accelerators, and one PowerVR GPU.

Target applications include advanced driver assistance systems (ADAS), autonomous vehicles, networking, drones, industrial automation, security, video analytics, machine learning, and more. One of the first customer for the new processor is Mobileye EyeQ5 SoC designed for  Fully Autonomous Driving (interestingly shortened as “FAD”) vehicles will eight multi-threaded MIPS CPU cores coupled with eighteen cores of Mobileye’s Vision Processors (VPs). EyeQ5 SoC should be found in vehicles as early as 2021.

MIPS I6500 CPU can be licensed now, with general availability planned for Q1 2017.You’ll find more technical details on the product page, and blog post for the announcement.

Imagination Solution to FCC Rules for WiFi Routers: Run OpenWrt / DD-WRT and the WiFi Driver in Separate Virtual Machines

June 10th, 2016 9 comments

About a year ago, discussions started about new rules from the FCC that could prevent routers from installing open source third party operating systems such as OpenWrt or DDWRT. Despite the FCC assurance that the rules were meant to prevent some users from illegally tweaking the RF settings, and that it would not have to impact installing of open source alternatives, the reality is that companies such as TP-Link ended up locking their routers up due to the new rules, while Linksys would only ensure OpenWrt/ DD-WRT compatibility on some of their routers, but not all. Companies are probably doing that due to the extra work that would be required to separate the RF settings which need to be locked, and the rest of the firmware. But Imagination Technology’s prpl security group has a solution for their MIPS Warrior P-Class processors using hardware virtualization.

OpenWrt_Virtualization_Block_Diagram

In order to show the concept works, they’ve developed the solution on an evaluation board based on Baikal T1 dual core MIPS P5600 communication processor, and using a Realtek RTL8192 WiFi adapter and the Ethernet port (WAN) for communications. The serial port was used for debugging Linux.

One the software side, they run an hypervisor, and three virtual machines (VM) leveraging the processor hardware capabilities:

  • Open source L4Re hypervisor comprised of an L4 microkernel that can run trusted native applications and act as a trusted hypervisor for operating systems.
  • Open VM for OpenWrt running OpenWrt and providing the main interface to the router facilities
  • Isolated VM for the Wi-Fi driver without direct access to the driver from other VMs, except through the virtual network connection using ports 85 for http, 449 for https or 29 for ssh. That’s the important part to comply with the FCC rules.
  • Dedicated VM for third party applications acting as a sandbox for running third party applications that provide additional functionality such as home automation apps.

Here’s the demo.

Of course, this will not solve the issues for existing cheap routers, but this could be a solution for future not-so-low-end WiFi routers.

Imagination Releases OpenWrt and LWM2M Stack Source Code for MIPS Creator Ci40 Development Board

March 25th, 2016 No comments

MIPS Creator Ci40 is a development board made by Imagination technology that features the company’s Creator cXT200 “Pistachio” SoC with a dual core MIPS interAptiv processor @ 550MHz and Ensigma C4500 RPU for 802.11ac/ BT 4.1 LE connectivity. The boards are supposed to be shipped to Kickstarter backers in April, but in the meantime, the company has released the source code for OpenWrt distribution as well as LWM2M stack for the board.

MIPS_Creator_Ci40_OpenWrt_LWM2M

OpenWRT source code is available in OpenWrt repo in FlowM2M gitbub account. Building the code for MIPS Creator Ci40 is quite straightforward:

IMG_MIPS_Pistachio

Select IMG MIPS Pistachio in make menuconfig, save the settings, and then run make to build OpenWrt for the board. This will also build the toolchain, so you don’t need to install any before hand.

LWM2M stands for Lightweight Machine to Machine, and is a protocol from the Open Mobile Alliance (OMA) for M2M / IoT device management, which defines the application layer communication protocol between a LWM2M Server and a LWM2M Client running on LWM2M Device. Imagination implementation is called Awa LWM2M. It’s a development suite that provides a number of components and tools.  For example a gateway will run both LWM2M daemon and client, but a sensor node would only run the client, Creator Ci40 board would communicate with sensors over 6LoWPAN using MikroElektronica 6LoWPAN Clicker boards.

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You can find the source code and documentation on Awa LWM2M github repo.