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Posts Tagged ‘ingenic’

Ingenic T10 is a MIPS Based Video Processor for 720p Cameras

June 13th, 2016 2 comments

Ingenic has been designing MIPS based SoCs using their Xburst processor engine for several years, which are found in tablets, development boards, and wearables. The company has now launched T10 smart video processor based on the same MIPS32 processor but mobile camera, security survey, video talking, video analysis and so on with image resolution up to 1280×960 (datasheet says 1280×1024), and videos up to 720p30 or VGA @ 30fps.

Ingenic T10 Block Diagram (Click to Enlarge)

Ingenic T10 Block Diagram (Click to Enlarge)

Ingenic T10 specifications:

  • CPU – XBurst single core MIPS32 processor up to 1GHz with FPU, 32KB L1 I-cache, 32KB L1 D-cache, and 128KB L2 unified cache.
  • Memory – Embedded [email protected] up to 512Mbit
  • Encoder engine -H.264 baseline, main profile; MJPEG/JPEG Baseline
  • Encode Performance
  • ISP
    • AE, AWB (automatic white balance), AF
    • Lens shading correction
    • Advanced spatial noise reduction
    • Motion-adaptive temporal noise reduction (3D de-noise)
    • Multi-exposure HDR image fusion (WDR)
    • Space-variant HDR processing
    • Host tuning tools
  • Computer Vision – Motion Detection/Perimeter Protection, Face Detection,Human Detection, People Counting, License Plate Recognition, etc…
  • CMOS Sensor Interface
    • Maximum 12 bit HSYNC/VSYNC (DVP)
    • I2C sensor control, Flash and DC control
    • Programmable sensor clock output
    • Up to 100M pixels/s input
  • Audio – Embedded audio CODEC; AAC, G726, G711, PCM encoding; Echo cancellation
  • On-chip Peripherals
    • POR, RTC, WDT
    • 2 channel ADC
    • 2x UART, 2x SMB, 2x SPI, 12x GPIO
    • 2x SDIO supporting SDHC
    • 4x PWM
    • USB OTG
    • RMII EMAC, supporting PHY clock output.
  • Security
    • Hardware AES/DES/3DES
    • Global unique Chip ID
    • 32Byte customer OTP
  • Power Consumption – Less than 400mW power consumption including DDRII
  • Package – TFBGA181 ROHS, ball pitch of 0.65mm, 10 x 10 mm package
  • Process – 40 nm CMOS low power

The company provides support for Linux-3.10 for the SoC. There’s no information about evaluation or development kits/boards for the video processor. You can find more details on Ingenic T10 product page where you’ll find the datasheet in English.

Thanks to Victor for the tip.

Categories: Ingenic, Linux Tags: camera, ingenic, Linux, mips

Ingenic X1000 MIPS Processor and X1000 Phoenix Board Target IoT and Embedded Applications

September 22nd, 2015 No comments

Ingenic is a Chinese SoC vendor that makes processors featuring their X-Burst cores based on MIPS architecture. Their JZ47 series can be found in tablets and development boards such a MIPS Creator CI20, while their M series, including Ingenic M200, are dedicated to wearables & IoT applications. The company has now launched X series starting with X1000 processor which include an audio codec, a Voice Trigger Engine (VTE) and 32MB RAM in package.

Ingenic X1000 Block Diagram

Ingenic X1000 Block Diagram

Ingenic X1000 features:

  • CPU Core – Ingenic MIPS XBurst 32-bit core up to 1.0 GHz, Double precision hardware float point unit, L1 cache 16KB/16KB, and L2 cache 128KB
  • Security Core – On-chip security ROM and RAM, hardware AES and RSA, supports security boot and user customization
  • Memory
    • 32MB LPDDR in package
    • Support 16-bit DDR2, DDR3 and LPDDR up to 512MB
    • Support Quad-SPI NOR/NAND, eMMC, SDHC
  • Display –  8-bit, 9-bit, 16-bit parallel interface SLCD up to 640×[email protected], 24 bpp
  • Hardware JPEG encoder Core – Up to 2.0 [email protected], motion JPEG encoder up to 1280×[email protected]
  • Voice Trigger Engine – Low-power DMIC controller, noise reduction for voice recognition, low trigger latency, filters for voice detection, far-field voice recognition, microphone array supported
  • Audio Codec – Hi-Fi quality audio codec, audio sample rate up to 192kbps
  • USB – USB OTG 2.0 High Speed, on-chip USB OTG 2.0 high speed PHY. Supports host only, device only and OTG modes
  • Other Peripherals and I/Os
    • 3x I2C, 1x SPI
    • 3x Full-duplex UART
    • 1x Smart card interface
    • 1x I2S, 1x PCM
    • 1x Ethernet MAC
  • Process Technology and Package – 65nm LP, BGA-190, 0.8mm pitch, 13mm x 13mm x 1.2mm

The processor is said to support “Linux 3.0 OS and greater”.

Ingenic_Phoenix_X1000

X1000 Phoenix Development Board

Ingenic also developed X1000 Phoenix evaluation/development board with X1000 processor, 16MB SPI NOR flash, 802.11 b/g/n Wi-Fi and Bluetooth 4.0 (AP6212), a micro SD slot (up to 32GB), an Ethernet port, a micro USB OTG port, a stereo audio power amplifier, 3 microphones (2 digital, 1 analog), as well as an expansion header that supports display and camera interfaces, a “payment” interface, and Zigbee. The board is powered by a 5V/3A power adapter, and also features a JTAG connector for debugging.

I could not find details with regards to pricing and availability. You may want to visit Ingenic X1000 product page (Chinese version) for some more information in both English and Chinese, at least until the company decides to complete the English version.

Thanks to Frederic, Victor and José for the tip.

Linux 4.2 Release – Main Changes, ARM and MIPS Architectures

September 2nd, 2015 No comments

Linus Torvalds released Linux Kernel 4.2 last Sunday:

So judging by how little happened this week, it wouldn’t have been a mistake to release 4.2 last week after all, but hey, there’s certainly a few fixes here, and it’s not like delaying 4.2 for a week should have caused any problems either.

So here it is, and the merge window for 4.3 is now open. I already have a few pending early pull requests, but as usual I’ll start processing them tomorrow and give the release some time to actually sit.

The shortlog from rc8 is tiny, and appended. The patch is pretty tiny too.

Go get it,

Linus

Some notable changes made to Linux 4.2 include:

  • File systems
    • New features for F2FS including per file encryption
    • CIFS support SMB 3.1.1 (experimental)
  • Cryptography – Jitter Entropy Random Number Generator, Chacha20 stream cipher and Poly1305 authentication (RFC7539),New RSA implementation. See lwn.net for details.
  • AMD GPU driver added support for AMD “Tonga,” “Iceland,” and “Carrizo” systems. That driver has now over 400,000 lines of code…
  • Networking

Some of the new features and improvements specific to the ARM architecture include (With a focus on Allwinner/Rockchip/Amlogic/Mediatek processors often discussed in this blog):

  • Allwinner:
    • A10/A10s/A13/A20/A31/A23 – SRAM Controller
    • A23 – SMP support, architected timer support
    • A31/A31s – CPUFreq support
    • A33 – Machine support, Bring-up sharing most drivers with A23, pinctl driver, PIO controller
    • A80 – Architected timer support, USB support
    • AXP221 PMIC driver
    • New boards and devices: LinkSprite pcDuino3 Nano, Cubietech Cubieboard4, Gemei G9, Auxtek T004, Utoo P66, Wexler TAB 7200, MK808C, Jesurun Q5, Xunlong Orange Pi, Xunlong Orange Pi Mini, Sinlinx SinA33
  • Rockchip
    • Fixes for GPU DRM driver
    • RK3368 – Added pinctrl and Ethernet (dwmac) support
    • Device tree – Files relicensed under GPLv2/X11 dual-license, Enable A12 HW PMU events in RK3288 boards, and TSADC for Firefly and PopMetal boards
    • Fixed IR receiver bug and modify some GPIO code in RK3288
  • Amlogic – Added documentation to the clock controller… nothing else.
  • Mediatek
    • Fixed clock registration in MT8135
    • Small changes and fixes to pinctrl driver
    • Added driver for Mediatek MT8173 I2C controller
    • Some fixes for PMIC
    • MT7601U driver (WiFi device)
    • Pinctrl driver for MT8127, MT6397,
  • Qualcomm
    • Added SPMI PMIC Arbiter device tree node for MSM8916
    • Added 8×16 chipset SPMI PMIC’s nodes
    • Added MSM8916 restart device node
    • Added initial set of PMIC and SoC pins for APQ8016 SBC board
  • Samsung
    • Fix exynos3250 MIPI DSI display and MIPI CSIS-2 camera sensor
    • Bring back cpufreq for exynos4210
  •  ARM64
    • New processors: Hisilicon ARM64 SoCs (e.g. Hi6220)
    • Various fixes for ARM64 for ACPI, MMU, SMP, perf, and more.
    • Enabled EDAC on ARM64
    • Support for Hikey board, ARM Juno r1 board
  • Various changes to some Atmel and Marvell processors, see Free Electrons blog post for details.
  • Other new ARM SoCs & hardware platforms – Freescale i.MX 7Dual, ZTE ZX29670, Buffalo WXR-1900DHP, ASUS RT-AC87U, SmartRG SR400ac, Compulab CM-A510, and more

There has also been some interesting changes for the MIPS architecture:

  • many bug fixes: LLVM build issue, KVM fixes, fix seccomp MIPS64, fix for oprofile (get_c0_perfcount_int), Fix JR emulation for R6, etc…
  • Some code cleanups (fixed misspellings, removes some code)
  • Added support for appended DTP
  • Improvements for R12000, R3000, Broadcom BCM47xx and BCM63xx,  ATH79
  • Large patchset for Ingenic JZ4740 SoC
  • Added support to Pistachio SoC
  • New MIPS platforms: MIPS Creator CI20 board and XWR-1750 board

A complete changelog for Linux 4.2 should soon be published on Kernelnewbies.org, and you’ll probably also want to look at their ARM architecture and drivers sections for more details about to various platforms including ARM and MIPS. I’ve also generated a complete Linux 4.2 Changelog with comments only (13.9MB) using git (git log v4.1..v4.2 --stat)

Ingenic Halley is a $20 Linux based IoT Board with Wi-Fi and Bluetooth 4.1 Connectivity

February 10th, 2015 5 comments

Ingenic introduced Newton2 platform for wearables a few months ago, and the kit with an AMOLED display, camera board and other accessories should go on sale in March for $80. In the meantime, the company has also been working on a lower cost internet of things (IoT) module and development kit powered by Ingenic M150 with Wi-Fi and Bluetooth 4.1 targeting smart appliances, Wi-Fi speakers, smart toys, industrial control applications, and other smart devices.

Ingenic_Halley

Halley IoT Module (Click to Enlarge)

Halley IoT module specifications:

  • SoC – Ingenic M150 XBurst (MIPS) single-core processor up to 1.0GHz with 128MB LPDDR on-chip, 2D graphics GPU, VPU supporintg 720p30 H.264 video decoding.
  • Storage – 8MP SPI NOR flash (GIGA GD25LQ64)
  • Connectivity – Wi-Fi 802.11 b/g/n and  Bluetooth 4.1 via Broadcom 43438 chip.
  • Expansion headers (2mm pitch)
    • 8-bit parallel LCD interface,
    • Audio – MIC, Line-In and headphone, 2x I2S,
    • SD card (MMC interface)
    • USB device 2.0, and USB host 1.1
    • 3x UART (2 with hardware flow control), 2x I2C, 1x SPI up to 50Mbps,
    • 5-pin JTAG
    • 2x 12-bit ADC,
    • 2x PWM
  • Power Supply – 3.3V
  • Power Consumption – 2mW (Standby, no radio); 10 mW (Standby, Wi-Fi)
  • Dimensions – 24 x 40 x 2.4 mm
Halley Module Block Diagram and Pinout

Halley Module Block Diagram and Pinout

The module is running Linux 3.10 with TCP/IP stack, and the company claims Android OS could also run on external storage. This would have to be a lightweight version of Android as only 128MB RAM is available. The development kit is comprised of the module, a baseboard, and a debug board.

Halley_Development_Kit

Ingenic Halley Devkit (Click to Enlarge)

The baseboard includes power circuitry to power the board with a micro USB port, reset and boot keys, some LEDs, a 14-pin male header, and UART connection to the debug board. It would have been good to have a micro SD slot on the back of the board, but none seems to have been included.

Even the board has not been formally launched, some documentation is already available for download including a product brief, a datasheet, and a developer’s guide. A Linux demo image and the SDK have also been released. The SDK includes a toolchain, source code for Linux and U-boot, drivers & tools, and a demo Android app (Airkiss).

M150 Block Diagram

M150 Block Diagram

It’s the first time I see details about Ingenic M150, so it might interesting to go through the specs:

  • CPU – XBurst core, 1.0GHz (MIPS-based). 32KB L1 cache, 256KB L2 cache.
  • GPU – X2D: Resizing, Rotating, Mirror, Color Convention and OSD etc.
  • VPU – Video encoder: H.264, [email protected] Video decoder: H.264, MPEG-1/2/4, VC-1, VP8, RV9, [email protected]
  • Memory
    • On-chip 128MB LPDDR, up to 320Mbps.
    • 64-bit ECC NAND flash, 512B/2KB/4KB/8KB/16KB page size.
    • Conventional and toggle NAND flash.
  • Display
    • LCD controller with OSD: TFT, SLCD, up to 1280*[email protected](BPP24).
    • Embedded E-Ink controller with color engine.
  • Camera – DVP interface, up to 2048 x 2048.
  • Audio – Embedded audio CODEC; Digital DMIC controller; AC97/I2S/SPDIF interface for external audio codec; PCM interface, master and slave mode.
  • ADC – 7 channels SAR A/D controller, 12-bit resolution.
  • On-chip Peripherals
    • USB 2.0 OTG, USB 1.1 Host.
    • MMC/SD/SDIO controller.
    • Full-duplex UART port.
    • Synchronous serial interface.
    • Two-wire SMB serial interface.
  • Security – Total 256bits OTP memory.
  • Package – BGA261, 11 x 11 x 1.4 (mm), 0.5mm pitch.

That confirms it’s one of the rare SoC with enough built-in RAM to run Linux. Renesas RZ/A1 is another one, but with only 10MB RAM, and a Cortex A9 core.

Halley IoT module and development kit will be available around March 10, for respectively $20 and $50. You can find more information, and ordering information on Ingenic’s Halley module page.

Thanks to Victor for the tip.

Ingenic Unveils Newton2 Platform for Wearables with M200 Dual Core SoC

November 13th, 2014 5 comments

Ingenic Newton is a development platform for wearables powered by Ingenic JZ4775, an application processor mostly used in tablets. Many companies are now making SoCs speficially designed for wearables with a powerful application core, and a low power core serving as a sensor hub, an Ingenic M200 SoC found in the new Ingenic Newton2 platform, uses the sample principle by combinging a MIPS XBurst processor @ 1.2GHz with a low power MIPS XBurst core @ 300MHz combined with low power GPU and VPU.

Inegnic Newton2 Board (Click to Enlarge)

Inegnic Newton2 Board (Click to Enlarge)

Ingenic Newton2 specifications:

  • SoC – Ingenic M200 dual core processor with MIPS XBurst @ 1.2 GHz, MIPS XBurst @ 300 MHz, 2D/3D GPU, and VPU supporting H.264, VP8, MPEG-1/2/4, VC-1, and RV9 up to 720p30
  • System Memory – 512 MB LPPDR2 (Samsung eMCP)
  • Storage – 4GB eMMC (Samsung eMCP)
  • Connectivity – 802.11 b/g/n Wi-Fi + Bluetooth 4.1 (Broadcom BCM43438) + connector for GPS
  • Sensors – Gyroscope, accelerometer, magnetometer (IvenSense MPU-9250)
  • Expansion Headers –  24-pin display connector, MIPI CSI / I2C camera connector, DMIC and AOHPL/R audio connector, GPS and sensors header including UART, I2C, and GPIO pins. touch connector, 14-pin button connector, and 4-pin Wi-Fi and 2.4 GHz BT connector.
  • Power Supply – Li-on battery: 3.7~4.2V or Micro USB: 5.0V;  Ricoh RC5T619 PMIC; Standby power consumption: < 3 mW
  • Dimensions – 15 x 30 x 2.4 mm
Newton2 Block Diagram

Newton2 Board Block Diagram

Compared to the original Newton board, Newton2 is about 50% smllaer, and consumes much less power resulting in improved battery life. Target applications include smartwatches, augmented reality headsets, smart glasses, smart cameras, wearable healthcare monitors, activity trackers, smart clothing, etc… The platform runs Android 4.4 + Linux 3.10, but there’s no mention of Android Wear support.

Ingenic_M200_SoC_Block_Diagram

 Key features of Ingenic M200 as listed on Anandtech:
Package BGA270, 7.7mm x 8.9mm x 0.76mm, 0.4mm pitch
CPU XBurst1-HP core, 1.2 GHz
XBurst1-LP core, 300 MHz
GPU 2D/3D acceleration with OpenGL ES 2.0/1.1. OpenVG 1.1
VPU Video encoder up to 720p @ 30fps: H.264, VP8
Video decoder up to 720p @ 30fps: H.264, VP8, MPEG-1/2/4, VC-1, RV9
ISP HDR, video and image stabilization, crop and rescale, auto exposure + gain + white balance + focus control, edge sharpening, noise reduction, color correction, contrast enhancement, gamma correction
Memory DDR2, DDR3, LPDDR, LPDDR2 up to 667 Mbps
64-bit ECC NAND flash support Toggle 1.0 and ONFI2.0
Display LCD controller with OSD: TFT, SLCD and MIPI-DSI (2-lanes)
E-Ink controller
Camera MIPI-CSI2 (2-lanes), DVP
Audio Audio CODEC with 24-bit ADC/DAC, stereo line-in, MIC in, and headphone interface
Low power DMIC controller
AC97/I2S/SPDIF interface for external audio codec
One PCM interface, supports both master and slave modes
Voice trigger engine to wake system by programmable specific voice
ADC 3 channels 12-bit SAR
Interfaces USB 2.0 OTG x 1
MMC/SD/SDIO controller x 2
Full-duplex UART port x 5
Synchronous serial interface x 2
Two-wire SMB serial interface x 4
Software Android 4.4

Ingenic M200, or another Ingenic SoC for wearables (M150), is said to be used in GEAK Watch 2, which can deliver 2-week of battery life. The crowdfunding campaign for the watch is still on-going.

Pricing and availability have not been disclosed for Ingenic Newton2, and if history is any guide, the board will be reserved to corporate customers, just like Ingenic Newton was. More details may be found on Ingenic Newton2 ad M200 SoC product page.

MIPS Creator CI20 Development Board Powered by Ingenic JZ4780 SoC

August 13th, 2014 2 comments

There are plenty of ARM based development boards running Linux and Android, but with MIPS it’s a different story. Microchip does have some affordable development board powered by their MIPS MCUs, but these don’t have the hardware specs to run Linux based operating systems, and Ingenic Newton Platform for wearables can run Android and Linux, but it appears to be reversed to companies with virtual no documentation. There are some MIPS platform running OpenWRT on hardware such as routers or Wi-Fi boards, but these can’t be considered fully supported development boards. But Imagination Technologies is trying to make MIPS more relevant, first by launching Prpl developers’ community, and MIPS Creator CI20 development board powered by Ingenic JZ4780 dual core MIPS32 (Xburst) core processor with PowerVR SGX540 GPU should soon be available with complete documentation and source code.

MIPS Creator CI20

MIPS Creator CI20

Let’s go through the hardware specifications first:

  • SoC – Ingenic JZ4780 dual core MIPS32 processor @ 1.2 GHz with Imagination PowerVR SGX540 GPU. 32kI + 32kD per core, 512K shared L2.
  • System Memory – 1GB DDR3
  • Storage – 8GB NOR flash, 1x SD card slot, 1x SD card slot via expansion
  • Video Output – HDMI up to 1080p
  • Audio I/O – HDMI, Andio In and Out via 3.5mm jack
  • Video Playback – Up to 1080p60
  • Connectivity – 10/100M Ethernet, Wi-Fi + Bt 4.0 module (IW8103)
  • USB – 1x USB OTG, 1x USB 2.0 Host.
  • Expansions Headers – Access to 23x GPIOs, 2x SPI, 1x I2S, 7x ADC on header, including 5-wire touch and battery monitoring function, 1x UART, Transport Stream I/F.
  • Debugging – UART, and 14-pin MIPS EJTAG header
  • Misc – IR receiver, power LED, and button
  • Power Supply – 5V via 4mm/1.7mm barrel connector
  • Dimensions – 90x95mm
MIPS Creator CI20 Board Components' Description (Click to Enlarge)

MIPS Creator CI20 Board Components’ Description (Click to Enlarge)

The board will come pre-loaded with Debian 7, but more operating systems will soon be available such as Android, Gentoo, Yocto Sato, Arch Linux, and Angstrom. Software and hardware documentation is available on eLinux. Hardware documentation includes components’ datasheets including JZ4780m, header pinout, and the schematics in PDF format only, so the project is not open source hardware, but it’s the case for most ARM development boards too. The source code for Linux, U-Boot, as well as various hardware libs for JZ4780 is available on Imagination Technologies MIPS github account, which instructions provided via eLinux Wiki which is still in construction, but looks promising. Software projects in the pipeline include XBMC, TSSI tuner, and a Raspberry Pi compatibility layer with the R-Pi like header, as well as support for OpenOCD.

The board has not been formally announced, so I do not know when it will become available, nor the price, but based on the Wiki’s progress, it should be very soon, and be sold on Imagination Technologies e-store for a competitive price since it’s clearly made for hobbyists / makers / individual developers.

Thanks to Frederic for the idea.

Prpl Non-Profit Organization to Work on Linux, Android, and OpenWRT for MIPS based Processors

May 28th, 2014 5 comments

prplIn what looks like an answer, albeit fairly late, to Linaro, the non-profit organization working on open source software for ARM based SoCs, a consortium of companies composed of Imagination Technologies, Broadcom, Cavium, Lantiq, Qualcomm, Ingenic, and a few others, has funded Prpl (pronounced Purple), “an open-source, community-driven, collaborative, non-profit foundation targeting and supporting the MIPS architecture—and open to others—with a focus on enabling next-generation datacenter-to-device portable software and virtualized architectures”.

The Prpl foundation will focus on three key objectives:

  • Portability – To create ISA agnostic software for rapid deployment across multiple architecture
  • Virtualization & security – To enable multi-tenant, secure, software, environments in datacenter, networking & storage, home, mobile and embedded
  • Heterogeneous Computing – To leverage compute resources enabling next generation big data analytics and mining

Initially there will PEG (Prpl Engineering Group) to take of the following projects for 4 market segments (datacenter, network & storage, connected consumers, and Embedded & IoT):

  • Linux –  Optimizations for enterprise, home and embedded Linux.
  • Android – Getting started with Android, and Android source code
  • Developer Tools – Used in conjunction with Android and Linux OS
  • Virtualization & Secure Supervisor – Secure multi-container frameworks
  • OpenWRT – Enabling carrier-grade features to complement OpenWRT
Arduino Yun

Arduino Yun

It also appears some low cost MIPS32 & MIPS64 development board and reference designs will be supported such as Newton wearable platform, Microchip chipKit WF32 board, and Arduino Yun.

Companies can join Prpl as Board Members or Contributors Members, and individuals can join the foundation for free to engage with the community and access source code and tools.

Since the the Prpl foundation has just been launched, there aren’t any tools or software available right now, but if you are interested in MIPS development, and possibly other architecture which may be part of Prpl later on, you can get more information and/or join the foundation on Prpl Foundation Website.

Ingenic Newton Platform for Wearables is Powered by MIPS Based JZ4775 SoC

April 2nd, 2014 1 comment

Imagination Technologies has published a blog post about Newton, a tiny reference design for wearables based on Ingenic JZ4775 MIPS SoC found in some recent smartwatches such as SmartQ Z1 (The CPU not the module). This module targets wearables, IoT, healthcare, home appliances, security, industrial control, consumer electronics and more.

Ingenic_Newton

Newton Specifications:

  • SoC – Ingenic JZ4775 MIPS Xburst processor @ 1 GHz with 2D GPU, and VPU supporting [email protected] for MPEG-2, MPEG-4, VC-1, H.264, VP8, and RV9 codecs.
  • System Memory –  Up to 3GB mobile DDR3/DDR2/LPDDR1
  • Storage – Up to 32 GB eMCP eMMC flash
  • Display Support – LCD or EPD, with touch panel and  backlight
  • Audio – Digital MIC and Speaker
  • Connectivity – 4-in-1 combo with Wi-Fi (802.11 a/b/g/n at 2.4/5 GHz), Bluetooth 4.0 + EDR (including Bluetooth LE support), NFC, and FM
  • Sensors – 3-axis gyroscope, accelerometer magnetometer, pressure, humidity and temperature, bio-signal detection and processing
  • USB – USB OTG signals
  • Expansion ports – UART, I2C, USB, GPIO, and “motor” support (PWM?)
  • Power Supply – USB (5V) or Battery (3.7 to 4.2V) with PMU  and charger
  • Power Consumption – Standby power:  4mW,  MP3 playback: 100mW on average,  with peak power consumption at ~260mW.
  • Dimensions – 21.6mm x 38.4mm x 3.2mm (But hardware manual: Max size is 41.4mm x 21.6mm)

Ingenic_JZ4775_Newton

Linux 3.0.8, Android 4.4 KitKat and several real-time operating systems have already been ported to the Newton platform, and developers/customers can access the open source drivers. Ingenic can also provide software packages for voice or gesture control for user interfaces.

During Google recent Android Wear announcement, Google mentioned Broadcom, Intel, Mediatek and Qualcomm, as well as Imagination Technolgies as key SoC and IP partners, so this module might also be used in devices running Android Wear. This was strongly implied in Imagination’s blog post, but they never explicitly confirmed Ingenic Newton was an Android Wear platform.

PD_JZ4775_NEWTON Board Description (Click to Enlarge)

PD_JZ4775_NEWTON Board Description (Click to Enlarge)

Neither pricing and availability have been disclosed. Since they will only provide source code to “customers”, I doubt this type of module will be available to hobbyists. Further details about the module, including an hardware reference manual, are available on Ingenic Newton page.