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Posts Tagged ‘low power’

Embedded Linux Conference & IoT Summit 2018 Schedule

February 13th, 2018 No comments

The Embedded Linux Conference 2018 and the OpenIoT Summit 2018 will jointly take place next month, on March 12 – 14, 2018 in Portland, Oregon, USA. The former is a “vendor-neutral technical conference for companies and developers using Linux in embedded products”, while the latter is a “technical conference for the developers and architects working on industrial IoT”. The Linux Foundation has already published the schedule, and it’s always useful to learn what will be discussed about even for people who won’t attend.

With that in mind, here’s my own virtual schedule with some of the talks I find interesting / relevant to this blog.

Monday, March 12

  • 10:50 – 11:40 – Progress in the Embedded GPU Ecosystem by Robert Foss, Collabora Ltd.

Ten years ago no one would have expected the embedded GPU ecosystem in Linux to be what it is now. Today, a large number of GPUs have Open Source support and for those that aren’t supported yet, improvements are happening at a rapid pace.

In just the last year Vivante GPUs have gained mainline support and Mali GPUs have seen good progress being made.

In this talk, Robert will cover GPUs in the embedded space and give an overview about their current status, what lies ahead and how the Open Source state of the art compares to the proprietary alternatives.

  •  11:50 – 12:40 – Zephyr LTS Release, What to Expect and Why are We Doing This by Anas Nashif, Intel

After eleven 1.x.x releases of Zephyr since the project has launched 2 years ago, the Zephyr project is planning to release Zephyr LTS in 2018 with many new features that have been in the works for the last year, stable APIs and with the goal of taking a subset of the released project code through various certification activities.

In this talk the status plans for Zephyr LTS will be presented and discussed and the next steps that the project will take after the LTS release.

  • 14:00 – 14:50 – Preempt-RT Raspberry Pi Linux by Tiejun Chen, VMware

As we know, the Raspberry Pi is a series of small single-board computers developed in the United Kingdom by the Raspberry Pi Foundation to promote the teaching of basic computer science in schools and in developing countries. Now it is very popular around our IoT world, and you can see many guys use Pi to build great things, and even it can play a role in the production environment. The official Raspberry Pi Linux maintains Linux kernel specific to Pi platform. But it does not include Preempt RT Linux support. Obviously, in some IoT cases we really need to meet hard real time requirement. In this presentation, we will review if-how we can integrate Preempt RT Linux patches to Pi Linux, an see what the problems are for this particular hardware platform.

  • 15:00 – 15:50 – OpenEmbedded/Yocto on RISC-V – New Kid on the Block by Khem Raj, Comcast

RISC-V a new open source ISA based architecture is rapidly gaining acceptance in embedded space. Several core packages e.g. gcc toolchain, linux kernel, binutils, newlib, qemu has already been ported for RISC-V. At this point, OpenEmbedded is one of first embedded linux distribution frameworks to support RISC-V architecture. This talk will cover the status of support as the core support has been upstreamed into OpenEmbedded-core, additionally SOC layer meta-riscv is also created which would serve as common layer for all RISC-V based SOCs.

  • 16:10 – 17:00 – Bluetooth Mesh with Zephyr OS and Linux by Johan Hedberg, Intel

Bluetooth Mesh is a new standard that opens a whole new wave of low-power wireless use cases. It extends the range of communication from a single peer-to-peer connection to a true mesh topology covering large areas, such as an entire building. This paves the way for both home and industrial automation applications. Typical home scenarios include things like controlling the lights in your apartment or adjusting the thermostat. Although Bluetooth 5 was released over a year ago, Bluetooth Mesh can be implemented on any device supporting Bluetooth 4.0 or later. This means that we’ll likely see very rapid market adoption of the feature.

The presentation will give an introduction to Bluetooth Mesh, covering how it works and what kind of features it provides. The talk will also give an overview of Bluetooth Mesh support in Zephyr OS and Linux and how to create new wireless solutions with them.

  • 17:10 – 18:00 – Drive your NAND within Linux by Miquèl Raynal, Bootlin (formerly Free Electrons)

NAND flash chips are almost everywhere, sometimes hidden in eMMCs, sometimes they are just parallel NAND chips under the orders of your favorite NAND controller. Each NAND vendor follows its own rules. Each SoC vendor creates his preferred abstraction for interacting with these chips.

Handling all of that requires some abstraction, and that is currently being enhanced in Linux! A new interface, called exec_op is showing up. It has been designed to match the most diverse situations. It should ease the support of advanced controllers as well as the implementation of vendor-specific NAND flash features.

This talk will start with some basics about NAND memories, especially their weaknesses and how we get rid of them. It will also show how the interaction between NAND chips and controllers has been standardized over the years and how it is planned to drive NAND controllers within Linux.

Tuesday, March 13

  •  10:50 – 11:40 – Comparing and Contrasting Embedded Linux Build Systems and Distributions by Drew Moseley, Mender.io

We will discuss the various options for creating embedded Linux operating systems. We will provide a basic description of each option, including an overview of the workflow for each choice. The talk will cover the advantages and disadvantages of each of these options and provide viewers with a matrix of design considerations to help them pick the right choice for their design. We will cover the following options:

  • Yocto/OpenEmbedded
  • Buildroot
  • OpenWRT/LEDE
  • Slimmed down desktop distributions (e.g. Debian, Raspbian, Ubuntu)

We will also touch upon other tools, such as crosstool-ng and ucLinux, which are peripherally related to building embedded Linux systems. The focus for this section will be to make the viewers aware of these tools as they frequently come up while researching embedded Linux so that you are better informed which tools are available.

  • 11:50 – 12:40 – The Things Network: An IOT Global Phenomenon by Bryan Smith, Tacit Labs

IoT has many connectivity options and systems based on Low Power Networks(LPN’s) such as LoraWAN are showing a great deal of promise. LoraWAN uses the ISM Band which doesn’t require a license for use.

The Things Networks (TTN) is a community about LoraWAN, Low Power Wide Area Network (LPWAN). It’s collaboratively built by passionate people, Open Source Software and Open Governance. The network has a manifesto and fair access policy that governs its use and management. In the session we’ll discuss:

  • The technology behind LoraWAN, TTN and similar networks.
  • TTN’s impact on public and private LPWAN’s.
  • The initiators and communities that install and build LoraWAN gateways.
  • Lastly we’ll discuss the impact of the deployments in real world use cases.

There will also be a live demo of a LoraWAN gateway and node in action on several public networks including TTN as well as others.

  • 14:00 – 14:50 – I + I2C = I3C: What’s in this Additional ‘I’? by Boris Brezillon, Bootlin (formerly Free Electrons)

The MIPI Alliance recently released version 1 of the I3C (pronounce ‘eye-three-see’) bus specification, which is supposed to be an improvement over the long-standing I2C and SPI protocols. Compared to I2C/SPI, I3C provides a higher data rate, lower power consumption and additional features such as dynamic address assignment, host join, in-band interrupts. For the last year or so, Free Electrons has been working with Cadence Design Systems on supporting this new kind of bus in Linux.

With this talk we would like to introduce this new bus and the concepts it brings to the table. We will also detail how we plan to expose the new features exposed by the I3C protocol in Linux and go through future possible improvements of the I3C framework that has already been submitted for review on the Linux kernel mailing list.

  • 15:00 – 15:50 – Android Common Kernel and Out of Mainline Patchset Status by Amit Pundir & John Stultz, Linaro

A quick overview of what the speakers ares going to cover in this session.

  • A brief background on Android common kernels – Out of tree Android patches and how they have evolved over time.
  • The current/active patchset introduction and status – Their use cases in Android and on-going upstreaming efforts if any.
  • A brief Intro to android-mainline-tracking tree.
  • Rebasing latest android-$LTS tree to latest linux release tag
  • Find/Report/Fix Android regressions or ABI breakages in mainline kernel.
  • 16:20 – 17:10 – Tock, The Operating System for a Programmable IoT by Amit Levy, Stanford University

Tock is an open-source operating system for low-power ARM Cortex-M microcontrollers that enables radically different kinds of embedded and IoT products.

In typical embedded systems, every line of code is fully trusted because embedded operating systems lack traditional isolation mechanisms like processes. Unfortunately, this makes developing secure products difficult, and running third-party applications virtually impossible.

Tock uses a language sandbox in the kernel and a process-like hardware enforced mechanism in userspace to isolate third-party and other untrusted code in the system.

In this presentation I’ll introduce Tock’s vision for IoT and how its isolation mechanisms work. Then, I’ll use examples of deployed systems and products using Tock to show how developers can use it to build more secure and extensible IoT systems today.

  • 19:00 – 20:00 – BoF: Open Source Hardware by Drew Fustini, OSH Park

Open Source Hardware BoF (Birds of a Feather) session for those interested in how Open Source Hardware design can benefit embedded Linux systems.

The session will start will start with a short presentation of a few slides to clarify terminology and highlight Open Source Hardware projects relevant to Linux. The panelists will then lead a discussion with the BoF attendees about the benefits and challenges of designing Open Source Hardware.

Jason and Drew can talk about the experience of working with community, manufacturers, and distributors to create an Open Source Hardware platform. Leon can speak about his experience of learning hardware design as a software engineer, and how he took his Raspberry Pi HATs from concept to product. John can speak about his experience leading an Open Source Hardware platform within a large corporation.

Wednesday, March 14

  • 11:05 – 11:55 – Landscape of Linux IoT Ecosystems by Christian Daudt, Cypress Semiconductor

IoT products are getting richer in their functionality daily, and as a result there is a trend for increased use of Linux in these products. As we are early in the IoT ecosystem cycle, there is a large number of projects and products vying for developer attention as frameworks and protocols to be used in new product development. This talk provides an overview of the options available and how they relate to each other. It covers OS stacks such as EdgeX Foundry, Automotive Grade Linux, Android Things, IoTivity, Tizen, etc.. as well as IoT-tailored cloud integrations from cloud vendors such as AWS, Google, Microsoft.

  • 12:05 – 12:55 – CPU Power Saving Methods for Real-time Workloads by Ramesh Thomas, Intel

Configurations created for real time applications mostly disable power management completely to avoid any impact on latency. It is however, possible to enable power management to a degree to which the impact on latency is tolerable based on application requirements. This presentation addresses how CPU idle states can be enabled and tuned to allow power savings while running real time applications.

The presentation will give a background of the issues faced by real-time applications when CPU power management is enabled. It will then explain tools, configurations and methods that can be used to tune applications and CPU power management in the kernel to be able to save power without impacting the deterministic latency tolerance requirements.

  • 14:30 – 15:20 – Debian for Embedded Systems: Best Practices by Vagrant Cascadian, Aikidev, LLC

As embedded hardware becomes more capable, Debian becomes an attractive OS for projects. Debian provides clear licensing, a solid technical foundation, and over twenty-five thousand software projects already available within Debian.

Unfortunately, embedded system projects may make changes to a customized Debian OS in ways that make it difficult to apply security updates or system upgrades. This can lead to an unmaintained fork of Debian with long-standing security vulnerabilities unfixed in the hands of end-users. Nobody likes bit-rot.

Many of these common pitfalls can be mitigated or avoided entirely by understanding Debian’s culture, infrastructure, technical norms, and contribution processes. These understandings will improve embedded systems using Debian over the long-term.

  • 15:30 – 16:20 – Civil Infrastructure Platform: Industrial Grade Open Source Base-Layer by Yoshitake Kobayashi, Toshiba Corporation, Software Development and Engineering Center

The Civil Infrastructure Platform (CIP) is creating a super long-term supported (SLTS) open source “base layer” of industrial grade software. The base-layer consists of the SLTS kernel and a basic set of open source software and standardization concepts. By establishing this “base layer,” the CIP Project will enable the use and implementation of software building blocks in civil infrastructure projects. Currently, all civil infrastructure systems are built from the ground up, with little re-use of existing software building blocks, which drains resources, money and time. In this devroom, we’ll share project strategy, use cases, roadmap, milestones and policies. We’ll also share technical details for each development activities for the base-layer that includes open source, real-time development tools, testing and answer questions.

  • 16:30 – 17:20 – 3D Printing with Linux and Xenomai by Kendall Auel, 3D Systems Corp.
Software running on embedded Linux with Xenomai is used to control a 3D printer. The lessons learned and practical advice will be shared in this presentation. There were many challenges to overcome. A complete 3D printing system requires precise motion control, thermal control, material delivery and monitoring, and coordinated data transfers. All concurrent real time processes must be coordinated and managed, while providing interactive response to user input. In parallel with the real time processing, the system must slice the 3D model into layers for printing, which is by its nature a compute-bound application. The dual-kernel architecture of Linux with Xenomai was ideal for maintaining low and predictable latencies for real time control, while allowing the complex and resource intensive slicing application to run in parallel.

Selecting the sessions was not easy as most talks are relevant, so I’d recommend checking out the whole schedule.

The Embedded Linux Conference & OpenIoT Summit require registration with the fees listed as follows:

  • Early Bird Fee: US$550 (through January 18, 2018)
  • Standard Fee: US$700 (January 19,  February 17, 2018)
  • Late Fee: US$850 (February 18, 2017 – Event)
  • Academic Fee: US$200 (Student/Faculty attendees will be required to show a valid student/faculty ID at registration.)
  • Hobbyist Fee: US$200 (only if you are paying for yourself to attend this event and are currently active in the community)

PicoCORE MX7ULP is a Compact Module Based on NXP i.MX 7ULP Ultra Low Power Processor

February 7th, 2018 13 comments

NXP unveiled another variant of their i.MX 7 Cortex A7 processor last year, and I missed it. NXP i.MX 7ULP offers many of the same features as i.MX 7, but is manufactured using FD-SOI (Fully Depleted Silicon On Insulator) process technology to offer lower power consumption, as low as 15 mW or less in deep sleep, or 17 times less in comparison to i.MX 7 devices, while the dynamic power efficiency is improved by 50 percent on the real time domain (Cortex-M4).

I found out about it thanks to an email from F&S Elektronik Systeme about the introduction of their  PicoCORE MX7ULP module – based on i.MX 7ULP processor – at  the Embedded World 2018 conference.

PicoCORE MX7ULP CoM specifications:

  • SoC – NXP i.MX 7ULP Arm Cortex-A7 processor @ up to 800 MHz,  with Arm Cortex-M4 real-time core, and 2D/3D graphics accelerator
  • System Memory – Up to 1GB LPDDR3
  • Storage – Up to 64 MB SPI flash, up to 32GB eMMC flash, optional SD card
  • Connectivity – WiFi 802.11b/g/n, optional BT 2.1/ EDR 3.0/ 4.1 LE
  • Two board-to-board connectors exposing
    • Display – MIPI DSI
    • Touch Panel – Analog resistive and PCAP Touch ext. via I2C
    • USB – 1x USB OTG device
    • 2x UART, 2x I2C, 1x SPI
    • 33x Digital I/O
    • Audio – Line In/Out, Mic, Headphone
  • Misc – RTC integrated in CPU
  • Supply Voltage – +5VDC/ ±5% / 4.2V Battery
  • Power Consumption – 1W typ.
  • Operating Temperature – 0°C – +70°C; optional: -20°C – +85°C
  • Dimensions – 40 x 35 mm
  • Weight – ~10g

i.MX 7ULP Block Diagram – Click to Enlarge

The module is suited to projects requiring small size and/or low energy consumption. The company will provide support for Linux running on the Cortex A7 core via the Yocto Project, and FreeRTOS for the Cortex-M4 core. A starter kit will also be available, but no details have been released at this stage.

Official launch is planned for Q3 2018, and Long Term Availability is ensured until 2028. More details and documentation should eventually be found on the product page.

CoM Block Diagram

STMicro Introduces Ultra-efficient STM32L4+ Series MCUs with Better Performance, Chrom-GRC Graphics Controller

November 16th, 2017 3 comments

STMicroelectronics has announced an upgrade to their STM32L4 series Cortex-M4 micro-controllers with STM32L4+ series upping the maximum frequency from 80 MHz to 120 MHz delivering up to 150 DMIPS (233 ULPMark-CP) , and ultra low power consumption as long as 33 nA in shutdown mode without RTC.

The new family also adds Chrom-GRC graphics controller (GFXMMU) that can handle both circular and square TFT LCD displays together with a MIPI DSI interface and displayer controller, making it ideal for wearables, Chrom-ART 2D accelerator for better graphics performance, two Octo SPI interfaces, and more memory (640KB max) and storage (up to 2MB flash).

STM32L4+ Block Diagram (Parts in Red Show New/Updated Features vs STM32L4)

If you want to know all differences between STM32L4 and STM32L4+, and/or learn how to use peripherals, STMicro has setup a nice free STM32L4+ online training page, which allow you to do just that either by downloading PDF documents, or following e-Presentations with slides and audio.

STM32L4+ appears to have the same power modes as STM32L4, except that it can turn SRAM3 on or off in STOP 2 mode.

Click to Enlarge

STM32L4+ series are available in different lines: STM32L4R5/S5, STM32L4R7/S7 (with TFT interface) and STM32L4R9/S9 (with MIPI‐DSI and with TFT interface) with details provided in the table below.

STM32L4+ series are software compatible with STM32L4 series, and mostly (but not entirely) pin-to-pin compatible.  Developers can use the same STM32 tools such as ST-Link and STM32CubeL4 embedded software, and three development board have been launched to get started with the new MCUs:

  • For headless development – NUCLEO-L4R5ZI STM32 Nucleo-144 development board with STM32L4R5ZI MCU. Supports Arduino, ST Zio and morpho connectivity ($19)

  • For wearables with round display – 32L4R9IDISCOVERY Discovery kit with STM32L4R9AI MCU ($89)

  • More complete kit with both a 4.3″ LCD TFT display and a 1.2″ MIPI DSI round LCD display – STM32L4R9I-EVAL Evaluation board with STM32L4R9AI MCU ($320)

STMicro STM32L4+ devices are already in production with price starting at $6.52 for orders of 10,000 pieces. Visit the product page for more information.

Via Time4EE

Save Power, Hibernate Your Embedded Linux System

August 30th, 2017 4 comments

This is a guest post by Tharma Rajan G, Project Lead, e-con Sytems.

What is the best way to save power consumption of your embedded Linux system? Is there any way to save max power and resume operation ? Yes. It is ‘hibernate’ mode, one of the Power Modes in Linux. This article talks about how we utilized this ‘hibernate mode’ in our Reference Platform Kit Meissa-I with eSOMiMX6-micro SOM.

Click to Enlarge

Meissa-I is a dual board solution that features eSOMiMX6-micro Computer on Module & carrier board. Meissa-I development board runs Linux and Android Marshmallow (under development). eSOMiMX6-micro is based on Dual/Quad core ARM CortexTM-A9 based CPU @ 800MHz/Core. It has 1GB LPDDR2 and 4GB eMMC FLASH (expandable upto 32GB). The eSOMiMX6-micro module also has the Wireless LAN and Bluetooth module.

Linux Power Modes

Power Management is a key feature in embedded Linux system and there are two types for implementing the power management on x86 platforms:

  1. Advanced Power Management (APM)
  2. Advanced Configuration and Power Interface (ACPI)

ACPI is the newer of the two technologies and puts power management in the hands of the operating system, allowing for more intelligent power management than is possible with BIOS controlled APM.

For ARM based systems however, APM/ACPI is not used. Instead power management in ARM Linux System, is implemented using sysfs entries. Following are sysfs entries for power management.

SI.No Sysfs Entry Purpose Notes
1 /sys/power/state
  1. To get supported system sleep states
  2. To set one of the supported system sleep states
Comparing to ACPI, this entry handles System Sleep States (Sx)
2 /sys/devices/system/cpu/cpu0/cpufreq/
  1. To get supported cpufreq governors and current governor for DVFS
  2. To set one of the supported cpufreq governors as current governor
Comparing to ACPI, this entry handles Processor low-power states (Px)
3 /sys/devices/system/cpu/cpuN/online
  1. To check whether CPUN is turned on in SMP (or multi core) system. Here N is not 0 (i.e boot core)
  2. To turn CPUN on/off in SMP (or multi core) system. Here N is not 0 (i.e boot core)
Comparing to ACPI, this entry handles CPU states (Cx)
4 /sys/devices/…/power/wakeup
  1. To set this device as wake up source for waking up the system from one of sleep states.
  2. To check whether this device is wakeup source or not
A wake up source device can not be put in low power states. Other non wake up source devices can be in low-power states.For example,

  1. Debug Serial port as wake up source

2. Ethernet LAN receive data as wake up source

3. RTC alarm as wake up source

5 /sys/class/thermal/thermal_zone0/temp 1. To get the CPU temperature current CPU temp in milli-celcius.
6 /sys/class/thermal/thermal_zone0/trip_point_1_temp 1. To get critical temperature value2. To set critical temperature value when the measured on die temperature exceeds the critical threshold → reboot the system (protection mechanism to prevent damage).
7 /sys/class/thermal/thermal_zone0/trip_point_0_temp 1. To get passive temperature value2. To set passive temperature value The passive trip point is a preventative measure before reaching critical that does things to lower temperature such as reducing cpu/gpu frequencies. The thermal driver works with CPU Freq mechanism

The power management subsystem provides a unified sysfs interface to userspace, regardless of what architecture or platform one is running. Generally sysfs filesystem is mounted in /sys directory and one can see that power management related entries in /sys/power path.

Using the entry /sys/power/state, one can get supported power states (or power modes) of the embedded system. And also one can put that embedded system in one of those supported power states.

System Sleeping States and Description

Sl.No

Label

Description

Alternative name

1

freeze

Will freeze user space process and put all I/O Devices into low-power state.

Make the processors to spend more time in idle state.

Suspend-To-Idle

2

standby

Addition to freeze power mode features , nonboot cpus are put into offline and all low-level system functions are suspended during transition into this state.

None of the operating state is lost ( i.e the cpu retains power ), so the system easily starts up again where it left off.

Power-On Suspend

3

mem

Offer more power savings as everything in the system is put into low power state except RAM, and RAM will be working in self refresh mode to retains its contents.

This mode also supports standby power mode.

Suspend-to-RAM or STR

4

disk

Take a snapshot of current system state and save it into a disk ( i.e swap space ) . While resuming , snapshot image is read and memory is restored to its pre-suspend state.

STD will put the system to the lowest power state.

Suspend-to-Disk or STD or Hibernate

Swap Memory for Hibernate Power Mode

Swap memory

Swap memory is the area on disk that is reserved to be used as extra RAM when your system needs more RAM than what is available. When your embedded Linux system runs out of free memory, then kernel can move some of the inactive pages into swap partition to make free room for active pages in RAM memory. If you plan to use hibernation in your embedded Linux systems, then you swap space have to be at least twice the RAM capacity.

Kernel support for swap memory

Enable swap support in Linux kernel

Click to Enlarge

Test swap memory

  1. To test swap memory, we created a simple test application test_swap_mem which will allocate memory infinitely using malloc() API and fill that allocated memory using memset() API. Let’s have a look at the source code
  2. Before creating swap space, Check whether swap space is enabled using free command
    Here swap total , used and free space is marked as 0 which means swap space in not enabled yet.
  3. Run test_swap_mem application as discussed below

    Let us wait till the application reaches OOM.

    Click to Enlarge

    From the above image, you can observe test_swap_mem allocates maximum of 799MB, after that it reaches OOM and also you can confirm swap space is not used by observing Free swap and Total swap is marked as 0 kB and no swap pages are used

  4. Now let we create a swap memory region and test with the same application. Once you decided about the partition block to be used as swap space , you have to mark that partition block as swap partition.
  5. After marking that specific partition as swap partition , you have to prepare it using mkswap tool
  6. Now your swap space is ready to use , then activate swap partition.
  7. First notice how much swap memory is available and then run test_swap_mem application.
    Here 892892 bytes of swap memory region is available. Try to explore how much swap space is used and when OOM will be reached.

    Click to Enlarge

    Yes , swap memory is utilized. As there is no free memory (including swap) available for allocation, kernel throws OOM error hence kills that test application.

Hibernate – Power Mode

Hibernation power mode saves the system state (i.e all the pages created in RAM memory) to swap space and put the system power down.When the system is powered on, the state is restored (i.e pages are moved from swap to RAM memory). To write the system state to swap space, a mechanism called ‘swsusp’ (Swap Suspend ) is used.

Kernel Configuration for Hibernate mode

Click to Enlarge

Now we will prepare the Swap Space to hold the Hibernation Image.

Setup the swap area,

Enable partition for swapping

Run a process, to verify restoring the hibernation image.

Entering into Hibernate

  1. Enter into hibernation state by executing below command.

Resume from Hibernate

Before starting to resume from hibernate state, append resume=/pathto/swapspace command line parameter to read back hibernate image from that specific swap partition. Let us change the bootargs for hibernate resume state , and run the bootcmd.

Click to Enlarge

Now you will observe, hibernate image is read from swap partition and resumed.

Click to Enlarge

Analysis

Power Measurement Analysis

The power data is obtained by computing the product of voltage and current measured.

Hardware and Software Used:

  1. The software version used for the measurement is
    • U-Boot 2016.03
    • Linux Kernel Version 4.1.15.
    • Yocto Krogoth X11 image.
  2. The board used for the measurement is Meissa-I with eSOMiMX6-micro SOM.
  3. The measurements were performed using Fluke 15B+ Digital Multimeter.

Power Consumption details in tested power modes.

Sl.No

Power Mode

Current

(mA)

Voltage

(V)

Power Consumption

(mW)

Description

1

Active

288

3.3

950

In active state, no peripheral is connected with the MEISSA development board except HDMI monitor , MicroSD card and a debug cable which is connected to the development system.

2

Standby

55

3.3

181.5

In standby mode, all the peripherals will be put into sleep state. ARM core and DDR will be active.

3

Suspend

10

3.3

33

In suspend state, all the peripherals along with ARM core will be put into sleep state. DDR will be put into self refreshing mode.

4

Hibernate

0

3.3

0

In hibernate mode , entire system will be put into low power state.

System Power Consumption Chart

Click to Enlarge

Active Mode Power Consumption

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated (mW)

VCC_SW1AB_CORE

1.3

29

37.7

VCC_SW1C_SOC

1.3

262

340.6

VCC_HIGH_IN

3.1

73

226.3

VCC_LDO5

2.4

10

24

VCC_SW3_LPDDR2

1.1

43

47.3

VCC_LDO4_1P8

1.8

1.96

3.52

VCC_SW_3P3

3.3

24

79.2

VCC_1P2

1.1

62

68.2

VCC_1P8

1.8

0.55

0.99

VCC_WIFI_VBAT

3.3

0

0

Total Power

827.81

Standby Mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

1.3

13

16.9

VCC_SW1C_SOC

1.3

11

14.3

VCC_HIGH_IN

3.1

34

105.4

VCC_LDO5

2.4

0.27

0.648

VCC_SW3_LPDDR2

1.1

7

7.7

VCC_LDO4_1P8

1.8

0.38

0.684

VCC_SW_3P3

3.3

0

0

VCC_1P2

1.1

0

0

VCC_1P8

1.8

0.24

0.432

VCC_WIFI_VBAT

3.3

0

0

Total Power

146.064

Suspend Mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

0.97

0

0

VCC_SW1C_SOC

0.97

3

2.91

VCC_HIGH_IN

2.9

1.64

4.756

VCC_LDO5

2.4

1

2.4

VCC_SW3_LPDDR2

1.1

6

6.6

VCC_LDO4_1P8

1.8

0.37

0.66

VCC_SW_3P3

3.3

1.32

4.35

VCC_1P2

1.1

0

0

VCC_1P8

1.8

0.85

1.53

VCC_WIFI_VBAT

3.3

0

0

Total Power

23.206

Hibernate mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

0

0

0

VCC_SW1C_SOC

0

0

0

VCC_HIGH_IN

0

0

0

VCC_LDO5

0

0

0

VCC_SW3_LPDDR2

0

0

0

VCC_LDO4_1P8

0

0

0

VCC_SW_3P3

0

0

0

VCC_1P2

0

0

0

VCC_1P8

0

0

0

VCC_WIFI_VBAT

0

0

0

Total Power

0

Domain Power Consumption Chart :

Click to Enlarge

Boot Time Analysis

App launch time Measurement in Normal Boot.

We have taken our eSOMiMX6Micro SOM as reference, it takes nearly 19 secs to execute watch command which is part of rc.local script file.

Click to Enlarge

App launch time measurement in Resume Mode.

While resuming from hibernate, it takes 16.76 secs to retain and execute the same watch command process state.

Click to Enlarge

Normal Boot and Hibernation Resume Comparison Chart.

Conclusion

From the above analysis on ‘hibernate mode’, we find it to be the best choice for putting the system in low power state. Also, it consumes minimal time for ‘hibernate resuming’ as compared to normal booting time. The only downside we observed is that, manual interaction was required to resume the device from hibernate mode.
I believe, this hibernate power mode analysis will be very useful to you. We will see you next time with another interesting article.

ESP32-PICO-D4 System-in-Package Combines ESP32, 4MB SPI Flash, a Crystal Oscillator, and Passive Components

August 22nd, 2017 2 comments

Espressif Systems has revealed another ESP32 variant, but this time it’s not an SoC, but a 7x7mm system-in-package (SIP) that comes ESP32 dual core processor, a 4MB  SPI flash, a crystal oscillator and various passive components, so that you don’t need to include those in your design, and create an ultra-compact PCB for wearables and other space-constrained applications.

ESP32-PICO-D4 Internal Schematics – Click to Enlarge

ESP32-PICO-D4 SiP specifications:

  • SoC – ESP32 with two Tensilica LX6 cores, 448 KB ROM, 520 KB SRAM (inc. 8KB RTC memory), 1kbit eFuse
  • On-module Flash – 4MB SPI flash
  • Connectivity
    • WiFi – 802.11 b/g/n/e/i (802.11n up to 150 Mbps)
    • Bluetooth – Bluetooth V4.2 BR/EDR and BLE specification; ; class-1, class-2 and class-3 transmitter; Audio: CVSD and SBC
  • SIP Interfaces
    • SD card, UART, SPI, SDIO, LED PWM, Motor PWM, I2S, I2C, IR
    • GPIO, capacitive touch sensor, ADC, DAC, LNA pre-amplifier
  • Sensors –  On-chip Hall sensor & temperature sensor
  • Clock – On-module 40 MHz crystal
  • Power supply – 2.3 ~ 3.6V
  • Operating current – Average: 80 mA
  • Temperature range –  -40°C ~ 85°C
  • Package dimensions –  7.0±0.1 mm x 7.0±0.1 mm x 0.94±0.1 mm

I understand ESP32 supports up to 16MB flash, so future ESP32-PICO-D16 SIP might be possible too. The second schematics in the datasheet shows what a basic board with ESP32-PICO SIP looks like.

ESP32-PICO-D4 Module Peripheral Schematics – Click to Enlarge

The company explains the SiP is particularly suited for any space-limited or battery-operated applications, such as wearable electronics, medical equipment, sensors and other IoT products. Beside the datasheet, there’s currently very little information about ESP32-PICO-D4 on the web, so we’ll have to wait to see what comes out of it.

[Update: Photo of module with ESP32-PICO-D4

]

Via ESP32net Tweet

Microchip EERAM Combines SRAM and Backup EEPROM into a Single Chip

August 9th, 2017 1 comment

Most micro-controllers comes with both SRAM volatile memory, and flash or EEPROM for non-volatile (persistent) memory, but Texas Instruments – and other companies – have been selling MCUs with FRAM (Ferroelectric Random Access Memory) and standalone FRAM chip, a non-volatile memory that delivers performance and power efficiency similar to SRAM, and much better endurance that either flash or EEPROM. You don’t see FRAM in that many MCUs and solutions, because it’s more expensive than having SRAM + flash, but some applications requiring ultra low power consumption and non-volatile storage write capabilities may benefit from the technology. Those include data logging, sensor networks, and batteryless applications. Microchip has also it own technology with EERAM, a non-volatile SRAM memory that includes a “shadow” EEPROM used to automatically backup data on power down with a small external capacitor providing enough power to save SRAM to the EEPROM.

Once power is recovered (Vdd > Vtrip), the content of the EEPROM is copied back into the SRAM. The company can hence combines the performance of SRAM with EEPROM non-volatile storage and reliability with this solution. Store and Recall actions can also be triggered by software commands. The end results is similar to what is achieved with FRAM, but Microchip claims EERAM is much cheaper. The company provide both 4Kbit and 16Kbit of the EERAM with the following specifications:

  • Capacity – 4Kb – 16Kb
  • Interface – I2C
  • Non-volatile (with external capacitor)
  • Unlimited erase/write cycles
  • Instantaneous, random read/write
  • Temperature Range – -40°C to +125°C
  • 8-pin packages

Just like FRAM, it’s also well suited to data logging applications, however capacity is quite lower since you can get 1 Mbit FRAM chips, and standby current is higher than some other Serial NVSRAM (Non-volatile SRAM) chips. Price starts at $0.50 per unit for 5K orders. Visit Microchip EERAM product page for more details.

Via Embedded Computing

Categories: Hardware Tags: eeprom, fram, low power, microchip

EtaCore ARM Cortex M3 Core Operates at Low Voltage (0.25V and up) for Higher Power Efficiency

July 14th, 2017 1 comment

We’ve previously seen Ambiq Micro offering Apollo ARM Cortex M4F MCU with Cortex M0+ energy efficiency, and later the upgraded Apollo 2 MCU with even lower power consumption and better performance. The company can achieve such efficiency thanks to low sub-thresold operating voltage in the 0 to 0.5V range. Another startup – Eta Compute – is now offering another low voltage solution with their EtaCore ARM Cortex M3 IP, and other IP blocks operating at low voltage (0.25 to 1.2V).

Eta Compute claims a “10x improvement in power efficiency over any alternative”, and battery life of over 10 years on a CR2032 coin cell. Their website does not provide that many details about the core and development tools, but still mentions the following:

  • The only commercially available self-timed technology supporting dynamic voltage scaling (DVS) that is insensitive to process variations, inaccurate device models, and path delay variations
  • Includes M0+ and M3 ARM cores scaling 0.3 to 1.2 volt operation with additional low voltage logic support functions such as RTC, AES, and DSP
  • Analog to Digital Converter (ADC) sensor interface consuming less than 5uW for the most power constrained applications
  • Efficient power management device that supports dynamic voltage scaling down to 0.25V with greater than 80% efficiency
  • Encryption and Decryption, signal processing, and real time clocks are other examples of Eta Compute IP supported by DVS, Eta Compute’s technology can be implemented in any standard foundry process with no modifications to the process. This allows ease of adoption of any IP and delivers robust, process and delay insensitive operation. The company’s IP is portable to technology nodes at any foundry simplifying the manufacturing process.

Eta Compute further explains that they developed delay insensitive asynchronous logic (DIAL) design IP for maximum power efficiency allowing small batteries and energy harvesting – such as solar, thermal, vibration, or RF energy harvesting- to power the design.

The company does not appear to make MCU themselves, but they provide EtaCore IP for other companies to design and manufacture MCU based on their solutions. To allow for an evaluation of their solutions, they designed EtaCore ARM Cortex M3 reference design which includes sensors for ambient light, temperature, humidity and pressure, is powered by a half-inch square solar cell, and optionally support LoRaWAN components. The reference design measures 8.9 x 3.8 cm, and can be programmed with Eclipse, Keil and Linux debug and development environments.

8Power Vibration Energy Harvesting Technology Powers Batteryless LPWAN GPS Trackers, MEMS Sensors

May 23rd, 2017 No comments

While IoT products usually promises one to 10 years battery life, they will be several billions of them, and ARM’s CEO even forecast one trillion IoT devices in the next 20 years. Recharging batteries at home may be fine, but imagine having to recharge or replace batteries on top of electric poles, inside walls, in remote locations, and other hard to reach places, considerable resources would have to be deployed just to replace or recharge battery every year or whenever the battery is close to being depleted.  That’s why work on energy harvesting technology for batteryless devices may be so important, and 8Power is one of the companies working in the field through their vibration energy harvesting technology that is said to harvest up to 10x the power of competing devices under comparable condition thanks to the use of parametric resonance phenomenon.

8Power LTE NB-IoT GPS Tracker (Left) and MEMS Sensor (Right)

The company has recently announced their Track 100 family of LPWAN GPS tracker, such as Track 100XL relying on LTE NB-IoT, but they also have models supporting LTE Cat M1 and LoRaWAN. The IP67 devices include vibration energy harvesting technology, as well as optionally a solar panel. The company also provides a “secure cloud hosted data platform to provide dashboards, analytics, device management, security and application API access to manage fleets of devices”. There’s no battery, and no need for (battery related) maintenance. Track 100 trackers are powered through the vibration generated by trucks, trains, or other vehicles.

The company is also working on integrating the technology into MEMS sensors that consume very little power (10 mW) in continuous operations. Beside leveraging vibrations from the transportation industry, and 8Power technology can also generate power from vibrations from  infrastructure (bridges, embankments, transmission lines) or machinery (high-power motors and rotating equipment), and the technology has already been validated through a experiment to monitor the structure of an older bridge in Scotland.

The company showcased their technology and latest products at IDTechEx 2017.

Via ARMDevices.net