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Posts Tagged ‘low power’

Save Power, Hibernate Your Embedded Linux System

August 30th, 2017 4 comments

This is a guest post by Tharma Rajan G, Project Lead, e-con Sytems.

What is the best way to save power consumption of your embedded Linux system? Is there any way to save max power and resume operation ? Yes. It is ‘hibernate’ mode, one of the Power Modes in Linux. This article talks about how we utilized this ‘hibernate mode’ in our Reference Platform Kit Meissa-I with eSOMiMX6-micro SOM.

Click to Enlarge

Meissa-I is a dual board solution that features eSOMiMX6-micro Computer on Module & carrier board. Meissa-I development board runs Linux and Android Marshmallow (under development). eSOMiMX6-micro is based on Dual/Quad core ARM CortexTM-A9 based CPU @ 800MHz/Core. It has 1GB LPDDR2 and 4GB eMMC FLASH (expandable upto 32GB). The eSOMiMX6-micro module also has the Wireless LAN and Bluetooth module.

Linux Power Modes

Power Management is a key feature in embedded Linux system and there are two types for implementing the power management on x86 platforms:

  1. Advanced Power Management (APM)
  2. Advanced Configuration and Power Interface (ACPI)

ACPI is the newer of the two technologies and puts power management in the hands of the operating system, allowing for more intelligent power management than is possible with BIOS controlled APM.

For ARM based systems however, APM/ACPI is not used. Instead power management in ARM Linux System, is implemented using sysfs entries. Following are sysfs entries for power management.

SI.No Sysfs Entry Purpose Notes
1 /sys/power/state
  1. To get supported system sleep states
  2. To set one of the supported system sleep states
Comparing to ACPI, this entry handles System Sleep States (Sx)
2 /sys/devices/system/cpu/cpu0/cpufreq/
  1. To get supported cpufreq governors and current governor for DVFS
  2. To set one of the supported cpufreq governors as current governor
Comparing to ACPI, this entry handles Processor low-power states (Px)
3 /sys/devices/system/cpu/cpuN/online
  1. To check whether CPUN is turned on in SMP (or multi core) system. Here N is not 0 (i.e boot core)
  2. To turn CPUN on/off in SMP (or multi core) system. Here N is not 0 (i.e boot core)
Comparing to ACPI, this entry handles CPU states (Cx)
4 /sys/devices/…/power/wakeup
  1. To set this device as wake up source for waking up the system from one of sleep states.
  2. To check whether this device is wakeup source or not
A wake up source device can not be put in low power states. Other non wake up source devices can be in low-power states.For example,

  1. Debug Serial port as wake up source

2. Ethernet LAN receive data as wake up source

3. RTC alarm as wake up source

5 /sys/class/thermal/thermal_zone0/temp 1. To get the CPU temperature current CPU temp in milli-celcius.
6 /sys/class/thermal/thermal_zone0/trip_point_1_temp 1. To get critical temperature value2. To set critical temperature value when the measured on die temperature exceeds the critical threshold → reboot the system (protection mechanism to prevent damage).
7 /sys/class/thermal/thermal_zone0/trip_point_0_temp 1. To get passive temperature value2. To set passive temperature value The passive trip point is a preventative measure before reaching critical that does things to lower temperature such as reducing cpu/gpu frequencies. The thermal driver works with CPU Freq mechanism

The power management subsystem provides a unified sysfs interface to userspace, regardless of what architecture or platform one is running. Generally sysfs filesystem is mounted in /sys directory and one can see that power management related entries in /sys/power path.

Using the entry /sys/power/state, one can get supported power states (or power modes) of the embedded system. And also one can put that embedded system in one of those supported power states.

System Sleeping States and Description

Sl.No

Label

Description

Alternative name

1

freeze

Will freeze user space process and put all I/O Devices into low-power state.

Make the processors to spend more time in idle state.

Suspend-To-Idle

2

standby

Addition to freeze power mode features , nonboot cpus are put into offline and all low-level system functions are suspended during transition into this state.

None of the operating state is lost ( i.e the cpu retains power ), so the system easily starts up again where it left off.

Power-On Suspend

3

mem

Offer more power savings as everything in the system is put into low power state except RAM, and RAM will be working in self refresh mode to retains its contents.

This mode also supports standby power mode.

Suspend-to-RAM or STR

4

disk

Take a snapshot of current system state and save it into a disk ( i.e swap space ) . While resuming , snapshot image is read and memory is restored to its pre-suspend state.

STD will put the system to the lowest power state.

Suspend-to-Disk or STD or Hibernate

Swap Memory for Hibernate Power Mode

Swap memory

Swap memory is the area on disk that is reserved to be used as extra RAM when your system needs more RAM than what is available. When your embedded Linux system runs out of free memory, then kernel can move some of the inactive pages into swap partition to make free room for active pages in RAM memory. If you plan to use hibernation in your embedded Linux systems, then you swap space have to be at least twice the RAM capacity.

Kernel support for swap memory

Enable swap support in Linux kernel

Click to Enlarge

Test swap memory

  1. To test swap memory, we created a simple test application test_swap_mem which will allocate memory infinitely using malloc() API and fill that allocated memory using memset() API. Let’s have a look at the source code
  2. Before creating swap space, Check whether swap space is enabled using free command
    Here swap total , used and free space is marked as 0 which means swap space in not enabled yet.
  3. Run test_swap_mem application as discussed below

    Let us wait till the application reaches OOM.

    Click to Enlarge

    From the above image, you can observe test_swap_mem allocates maximum of 799MB, after that it reaches OOM and also you can confirm swap space is not used by observing Free swap and Total swap is marked as 0 kB and no swap pages are used

  4. Now let we create a swap memory region and test with the same application. Once you decided about the partition block to be used as swap space , you have to mark that partition block as swap partition.
  5. After marking that specific partition as swap partition , you have to prepare it using mkswap tool
  6. Now your swap space is ready to use , then activate swap partition.
  7. First notice how much swap memory is available and then run test_swap_mem application.
    Here 892892 bytes of swap memory region is available. Try to explore how much swap space is used and when OOM will be reached.

    Click to Enlarge

    Yes , swap memory is utilized. As there is no free memory (including swap) available for allocation, kernel throws OOM error hence kills that test application.

Hibernate – Power Mode

Hibernation power mode saves the system state (i.e all the pages created in RAM memory) to swap space and put the system power down.When the system is powered on, the state is restored (i.e pages are moved from swap to RAM memory). To write the system state to swap space, a mechanism called ‘swsusp’ (Swap Suspend ) is used.

Kernel Configuration for Hibernate mode

Click to Enlarge

Now we will prepare the Swap Space to hold the Hibernation Image.

Setup the swap area,

Enable partition for swapping

Run a process, to verify restoring the hibernation image.

Entering into Hibernate

  1. Enter into hibernation state by executing below command.

Resume from Hibernate

Before starting to resume from hibernate state, append resume=/pathto/swapspace command line parameter to read back hibernate image from that specific swap partition. Let us change the bootargs for hibernate resume state , and run the bootcmd.

Click to Enlarge

Now you will observe, hibernate image is read from swap partition and resumed.

Click to Enlarge

Analysis

Power Measurement Analysis

The power data is obtained by computing the product of voltage and current measured.

Hardware and Software Used:

  1. The software version used for the measurement is
    • U-Boot 2016.03
    • Linux Kernel Version 4.1.15.
    • Yocto Krogoth X11 image.
  2. The board used for the measurement is Meissa-I with eSOMiMX6-micro SOM.
  3. The measurements were performed using Fluke 15B+ Digital Multimeter.

Power Consumption details in tested power modes.

Sl.No

Power Mode

Current

(mA)

Voltage

(V)

Power Consumption

(mW)

Description

1

Active

288

3.3

950

In active state, no peripheral is connected with the MEISSA development board except HDMI monitor , MicroSD card and a debug cable which is connected to the development system.

2

Standby

55

3.3

181.5

In standby mode, all the peripherals will be put into sleep state. ARM core and DDR will be active.

3

Suspend

10

3.3

33

In suspend state, all the peripherals along with ARM core will be put into sleep state. DDR will be put into self refreshing mode.

4

Hibernate

0

3.3

0

In hibernate mode , entire system will be put into low power state.

System Power Consumption Chart

Click to Enlarge

Active Mode Power Consumption

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated (mW)

VCC_SW1AB_CORE

1.3

29

37.7

VCC_SW1C_SOC

1.3

262

340.6

VCC_HIGH_IN

3.1

73

226.3

VCC_LDO5

2.4

10

24

VCC_SW3_LPDDR2

1.1

43

47.3

VCC_LDO4_1P8

1.8

1.96

3.52

VCC_SW_3P3

3.3

24

79.2

VCC_1P2

1.1

62

68.2

VCC_1P8

1.8

0.55

0.99

VCC_WIFI_VBAT

3.3

0

0

Total Power

827.81

Standby Mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

1.3

13

16.9

VCC_SW1C_SOC

1.3

11

14.3

VCC_HIGH_IN

3.1

34

105.4

VCC_LDO5

2.4

0.27

0.648

VCC_SW3_LPDDR2

1.1

7

7.7

VCC_LDO4_1P8

1.8

0.38

0.684

VCC_SW_3P3

3.3

0

0

VCC_1P2

1.1

0

0

VCC_1P8

1.8

0.24

0.432

VCC_WIFI_VBAT

3.3

0

0

Total Power

146.064

Suspend Mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

0.97

0

0

VCC_SW1C_SOC

0.97

3

2.91

VCC_HIGH_IN

2.9

1.64

4.756

VCC_LDO5

2.4

1

2.4

VCC_SW3_LPDDR2

1.1

6

6.6

VCC_LDO4_1P8

1.8

0.37

0.66

VCC_SW_3P3

3.3

1.32

4.35

VCC_1P2

1.1

0

0

VCC_1P8

1.8

0.85

1.53

VCC_WIFI_VBAT

3.3

0

0

Total Power

23.206

Hibernate mode Power Consumption:

Power Domain

Voltage ( V )

Current Consumption (mA)

Power Calculated ( mW )

VCC_SW1AB_CORE

0

0

0

VCC_SW1C_SOC

0

0

0

VCC_HIGH_IN

0

0

0

VCC_LDO5

0

0

0

VCC_SW3_LPDDR2

0

0

0

VCC_LDO4_1P8

0

0

0

VCC_SW_3P3

0

0

0

VCC_1P2

0

0

0

VCC_1P8

0

0

0

VCC_WIFI_VBAT

0

0

0

Total Power

0

Domain Power Consumption Chart :

Click to Enlarge

Boot Time Analysis

App launch time Measurement in Normal Boot.

We have taken our eSOMiMX6Micro SOM as reference, it takes nearly 19 secs to execute watch command which is part of rc.local script file.

Click to Enlarge

App launch time measurement in Resume Mode.

While resuming from hibernate, it takes 16.76 secs to retain and execute the same watch command process state.

Click to Enlarge

Normal Boot and Hibernation Resume Comparison Chart.

Conclusion

From the above analysis on ‘hibernate mode’, we find it to be the best choice for putting the system in low power state. Also, it consumes minimal time for ‘hibernate resuming’ as compared to normal booting time. The only downside we observed is that, manual interaction was required to resume the device from hibernate mode.
I believe, this hibernate power mode analysis will be very useful to you. We will see you next time with another interesting article.

ESP32-PICO-D4 System-in-Package Combines ESP32, 4MB SPI Flash, a Crystal Oscillator, and Passive Components

August 22nd, 2017 2 comments

Espressif Systems has revealed another ESP32 variant, but this time it’s not an SoC, but a 7x7mm system-in-package (SIP) that comes ESP32 dual core processor, a 4MB  SPI flash, a crystal oscillator and various passive components, so that you don’t need to include those in your design, and create an ultra-compact PCB for wearables and other space-constrained applications.

ESP32-PICO-D4 Internal Schematics – Click to Enlarge

ESP32-PICO-D4 SiP specifications:

  • SoC – ESP32 with two Tensilica LX6 cores, 448 KB ROM, 520 KB SRAM (inc. 8KB RTC memory), 1kbit eFuse
  • On-module Flash – 4MB SPI flash
  • Connectivity
    • WiFi – 802.11 b/g/n/e/i (802.11n up to 150 Mbps)
    • Bluetooth – Bluetooth V4.2 BR/EDR and BLE specification; ; class-1, class-2 and class-3 transmitter; Audio: CVSD and SBC
  • SIP Interfaces
    • SD card, UART, SPI, SDIO, LED PWM, Motor PWM, I2S, I2C, IR
    • GPIO, capacitive touch sensor, ADC, DAC, LNA pre-amplifier
  • Sensors –  On-chip Hall sensor & temperature sensor
  • Clock – On-module 40 MHz crystal
  • Power supply – 2.3 ~ 3.6V
  • Operating current – Average: 80 mA
  • Temperature range –  -40°C ~ 85°C
  • Package dimensions –  7.0±0.1 mm x 7.0±0.1 mm x 0.94±0.1 mm

I understand ESP32 supports up to 16MB flash, so future ESP32-PICO-D16 SIP might be possible too. The second schematics in the datasheet shows what a basic board with ESP32-PICO SIP looks like.

ESP32-PICO-D4 Module Peripheral Schematics – Click to Enlarge

The company explains the SiP is particularly suited for any space-limited or battery-operated applications, such as wearable electronics, medical equipment, sensors and other IoT products. Beside the datasheet, there’s currently very little information about ESP32-PICO-D4 on the web, so we’ll have to wait to see what comes out of it.

[Update: Photo of module with ESP32-PICO-D4

]

Via ESP32net Tweet

Microchip EERAM Combines SRAM and Backup EEPROM into a Single Chip

August 9th, 2017 1 comment

Most micro-controllers comes with both SRAM volatile memory, and flash or EEPROM for non-volatile (persistent) memory, but Texas Instruments – and other companies – have been selling MCUs with FRAM (Ferroelectric Random Access Memory) and standalone FRAM chip, a non-volatile memory that delivers performance and power efficiency similar to SRAM, and much better endurance that either flash or EEPROM. You don’t see FRAM in that many MCUs and solutions, because it’s more expensive than having SRAM + flash, but some applications requiring ultra low power consumption and non-volatile storage write capabilities may benefit from the technology. Those include data logging, sensor networks, and batteryless applications. Microchip has also it own technology with EERAM, a non-volatile SRAM memory that includes a “shadow” EEPROM used to automatically backup data on power down with a small external capacitor providing enough power to save SRAM to the EEPROM.

Once power is recovered (Vdd > Vtrip), the content of the EEPROM is copied back into the SRAM. The company can hence combines the performance of SRAM with EEPROM non-volatile storage and reliability with this solution. Store and Recall actions can also be triggered by software commands. The end results is similar to what is achieved with FRAM, but Microchip claims EERAM is much cheaper. The company provide both 4Kbit and 16Kbit of the EERAM with the following specifications:

  • Capacity – 4Kb – 16Kb
  • Interface – I2C
  • Non-volatile (with external capacitor)
  • Unlimited erase/write cycles
  • Instantaneous, random read/write
  • Temperature Range – -40°C to +125°C
  • 8-pin packages

Just like FRAM, it’s also well suited to data logging applications, however capacity is quite lower since you can get 1 Mbit FRAM chips, and standby current is higher than some other Serial NVSRAM (Non-volatile SRAM) chips. Price starts at $0.50 per unit for 5K orders. Visit Microchip EERAM product page for more details.

Via Embedded Computing

Categories: Hardware Tags: eeprom, fram, low power, microchip

EtaCore ARM Cortex M3 Core Operates at Low Voltage (0.25V and up) for Higher Power Efficiency

July 14th, 2017 1 comment

We’ve previously seen Ambiq Micro offering Apollo ARM Cortex M4F MCU with Cortex M0+ energy efficiency, and later the upgraded Apollo 2 MCU with even lower power consumption and better performance. The company can achieve such efficiency thanks to low sub-thresold operating voltage in the 0 to 0.5V range. Another startup – Eta Compute – is now offering another low voltage solution with their EtaCore ARM Cortex M3 IP, and other IP blocks operating at low voltage (0.25 to 1.2V).

Eta Compute claims a “10x improvement in power efficiency over any alternative”, and battery life of over 10 years on a CR2032 coin cell. Their website does not provide that many details about the core and development tools, but still mentions the following:

  • The only commercially available self-timed technology supporting dynamic voltage scaling (DVS) that is insensitive to process variations, inaccurate device models, and path delay variations
  • Includes M0+ and M3 ARM cores scaling 0.3 to 1.2 volt operation with additional low voltage logic support functions such as RTC, AES, and DSP
  • Analog to Digital Converter (ADC) sensor interface consuming less than 5uW for the most power constrained applications
  • Efficient power management device that supports dynamic voltage scaling down to 0.25V with greater than 80% efficiency
  • Encryption and Decryption, signal processing, and real time clocks are other examples of Eta Compute IP supported by DVS, Eta Compute’s technology can be implemented in any standard foundry process with no modifications to the process. This allows ease of adoption of any IP and delivers robust, process and delay insensitive operation. The company’s IP is portable to technology nodes at any foundry simplifying the manufacturing process.

Eta Compute further explains that they developed delay insensitive asynchronous logic (DIAL) design IP for maximum power efficiency allowing small batteries and energy harvesting – such as solar, thermal, vibration, or RF energy harvesting- to power the design.

The company does not appear to make MCU themselves, but they provide EtaCore IP for other companies to design and manufacture MCU based on their solutions. To allow for an evaluation of their solutions, they designed EtaCore ARM Cortex M3 reference design which includes sensors for ambient light, temperature, humidity and pressure, is powered by a half-inch square solar cell, and optionally support LoRaWAN components. The reference design measures 8.9 x 3.8 cm, and can be programmed with Eclipse, Keil and Linux debug and development environments.

8Power Vibration Energy Harvesting Technology Powers Batteryless LPWAN GPS Trackers, MEMS Sensors

May 23rd, 2017 No comments

While IoT products usually promises one to 10 years battery life, they will be several billions of them, and ARM’s CEO even forecast one trillion IoT devices in the next 20 years. Recharging batteries at home may be fine, but imagine having to recharge or replace batteries on top of electric poles, inside walls, in remote locations, and other hard to reach places, considerable resources would have to be deployed just to replace or recharge battery every year or whenever the battery is close to being depleted.  That’s why work on energy harvesting technology for batteryless devices may be so important, and 8Power is one of the companies working in the field through their vibration energy harvesting technology that is said to harvest up to 10x the power of competing devices under comparable condition thanks to the use of parametric resonance phenomenon.

8Power LTE NB-IoT GPS Tracker (Left) and MEMS Sensor (Right)

The company has recently announced their Track 100 family of LPWAN GPS tracker, such as Track 100XL relying on LTE NB-IoT, but they also have models supporting LTE Cat M1 and LoRaWAN. The IP67 devices include vibration energy harvesting technology, as well as optionally a solar panel. The company also provides a “secure cloud hosted data platform to provide dashboards, analytics, device management, security and application API access to manage fleets of devices”. There’s no battery, and no need for (battery related) maintenance. Track 100 trackers are powered through the vibration generated by trucks, trains, or other vehicles.

The company is also working on integrating the technology into MEMS sensors that consume very little power (10 mW) in continuous operations. Beside leveraging vibrations from the transportation industry, and 8Power technology can also generate power from vibrations from  infrastructure (bridges, embankments, transmission lines) or machinery (high-power motors and rotating equipment), and the technology has already been validated through a experiment to monitor the structure of an older bridge in Scotland.

The company showcased their technology and latest products at IDTechEx 2017.

Via ARMDevices.net

Ambiq Micro Introduces Ultra-Low Power Apollo 2 Cortex-M4F MCU Consuming Less than 10 μA/MHz

December 18th, 2016 1 comment

Last year Ambiq Micro unveiled their Apollo Cortex-M4F MCU with Cortex M0+ energy efficiency thanks to operation in sub-threshold voltage (< 0.5 V), and the MCU is said found in Matrix Powerwatch, a fitness tracker powered by body heat that you never need to charge. The company has recently announced a new version of the micro-controller with Apollo 2 MCU with better maximum performance thanks to a higher maximum clock speed (48 MHz vs 24 MHz), and higher efficiency (10 μA/MHz vs 30 μA/MHz @ 3.3V).

apollo-2-mcu

Apollo 2 MCU key features and specifications:

  • Ultra-low supply current
    • <10 μA/MHz executing from flash at 3.3 V
    • <10 μA/MHz executing from RAM at 3.3 V
  • ARM Cortex-M4 Processor up to 48 MHz with FPU, MMU, wake-up interrupt controller with 32 interrupts
  • Ultra-low power memory
    • Up to 1 MB of flash memory for code/data
    • Up to 256 KB of low leakage RAM for code/data
    • 16kB 1 or 2-way Associative Cache
  • Ultra-low power interface for off-chip sensors
    • 14 bit, 15-channel, up to 1.2 MS/s ADC
    • Voltage comparator
    • Temperature sensor with +/-2ºC accuracy
  • Serial peripherals – 6x I2C/SPI master,1x I2C/SPI slave,2x UART, PDM for mono and stereo audio microphone
  • Clock sources
    • 32.768 kHz XTAL oscillator
    • Low frequency RC oscillator – 1.024 kHz
    • High frequency RC oscillator – 48 MHz
    • RTC based on Ambiq’s AM08X5/18X5 families
  • Wide operating range – 1.8-3.6 V, –40 to 85°C
  • Package –  2.5 x 2.5 mm 49-pin CSP with 34 GPIO; 4.5 x 4.5 mm 64-pin BGA with 50 GPIO

The MCU promises weeks, months, and years of battery life thanks to Ambiq Micro’s patented Subthreshold Power Optimized Technology (SPOT) Platform. Apollo 2 will be suitable for battery operated devices, or even batteryless devices leveraging energy harvesting such as wireless sensors, activity and fitness trackers, consumer medical devices, smart watches, and smart home/IoT devices.

Documentation and devkits are available but you’d need to contact the company to learn more. Ambiq Micro’s Apollo 2 is currently sampling to some partners, and will be sampling more broadly in the coming months. A few more details may be found on Ambiq Micro Apollo 2’s product page.

STMicro SensorTile is a Tiny STM32 Module with Bluetooth 4.1 LE and Four Sensor Chips

December 8th, 2016 1 comment

STMicroelectronics SensorTile is a 13.5 x 13.5mm sensor board based on STM32L4 ARM Cortex-M4 microcontroller, a MEMS accelerometer, gyroscope, magnetometer, pressure sensor, a MEMS microphone, as well as a 2.4Ghz radio chip for Bluetooth 4.1 Low Energy connectivity for wearables, smart home, and IoT projects.

stmicro-sensortile

SensorTile hardware specifications:

  • MCU – STMicro STM32L476 ARM Cortex-M4 [email protected] up to 80 MHz with 128 KB RAM, 1MB flash
  • Connectivity – Bluetooth 4.1 Smart/LE via BlueNRG-MS network processor with integrated 2.4GHz radio compliant with
  • Sensors
    • LSM6DSM 3D accelerometer + 3D gyroscope
    • LSM303AGR 3D Magnetometer + 3D accelerometer
    • LPS22HB pressure sensor/barometer
    • MP34DT04 digital MEMS microphone
  • I/Os – 2x 9 half holes with access to UART, SPI, SAI (Serial Audio Interface), I2C, DFSDM, USB, OTG, ADC, and GPIOs signals
  • Debugging – SWD interface (multiplexed with GPIOs)
  • Power Supply Range – 2V to 5.5 V
  • Dimensions – 13.5 x 13.5 mm
SensorTile's Functional Block Diagram - Click to Enlarge

SensorTile’s Functional Block Diagram – Click to Enlarge

Software development can be done through a sets of APIs based on the STM32Cube Hardware Abstraction Layer and middleware components, including the STM32 Open Development Environment. The module is supported by Open Software eXpansion Libraries, namely Open.MEMS, Open.RF, and Open.AUDIO, with various example programs allowing you to get started. Several third-party embedded sensing and voice-processing projects also support the module. The module also comes pre-loaded with BLUEMICROSYSTEM2 firmware, and can be controlled with “ST BlueMS” app found on Apple Store and Google Play.

sensortile-kit

But the best way to get started is with SensorTile kit including SensorTile core module and:

  • STLCR01V1 cradle board with a footprint for SensorTile core board, HTS221 humidity and temperature sensor, a micro-SD card socket, a micro USB port, a lithium-polymer battery (LiPo) charger, and a SWD header.
  • A LiPo rechargeable battery and a plastic case for the cradle board, SensorTile module, and battery
  • STLCX01V1 Arduino UNO R3 compatible cradle expansion board with analog stereo audio output, a micro-USB connector for power and communication, a reset button and a SWD header.
  • A programming cable

I could not find a price for SensorTile core module, but STEVAL-STLKT01V1 SensorTile kit can be purchased for $80.85 directly on STMicro website or their distributors. Visit SensorTile kit’s product page for further information include hardware design files, quick start guide, software and firmware downloads, purchase links, and more.

Embedded Linux Conference and OpenIoT Summit Europe 2016 Videos are Now Available Online

November 8th, 2016 1 comment

The Embedded Linux Conference and OpenIoT Summit Europe 2016 conferences took place on October 11 – 13 in Berlin, Germany, with many interesting talks about Linux, development boards, power management, embedded systems, software optimization, tools, and so on, as well as a few keynotes.

elce-openiot-2016

The Linux Foundation has recorded most talks and keynotes, and made the videos available on their website. A free registration is required, and will redirect you to the full unlisted playlist on YouTube.

Tim Bird keynote can be watch directly without registration.

You can also download the slides for each presentation.

Thanks to Harley for the tip.