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Posts Tagged ‘prototype’

STEGO BOARD Enables Neat Prototypes with Development Boards and Accessories (Crowdfunding)

October 13th, 2017 1 comment

If you’ve ever created a quick prototype for your own use, or for your company, you may have based it on a development board, and added some extra modules or add-on modules, as well as potentially accessories such as hard drives or power supply. Software is complete and it works, but it may look like a mess, and transporting it may cause cables to disconnect or other problems.

STEGO BOARD should help in this case. It’s some kind of mounting systems compatible with the most common boards like Raspberry Pi 3, Rock64, or ASUS Tinkerboard, mini-ITX motherboards, mini PCs with VESA mounts, 2.5″ and 3.5″ drives, and so on. So you can create prototypes like the ones below.

Six different products are available:

  • STEGO BOARD 102 – 2 layers of the smaller board with 106 parts (stands, screws, zip ties). Can be used with mini PC, development board, up to 2 SATA drives
  • STEGO BOARD 103 – 3 layers of the smaller board with 144 parts. Up to 3 SATA drives
  • STEGO BOARD 104 – 4 layers of the smaller board with 206 parts. Up to 4 SATA drives
  • STEGO BOARD 105 – 5 layers of the smaller board with 246 parts. Up to 5 SATA drives
  • STEGO BOARD 400 – Larger board with 220 parts can be be used for up to 4 SATA drives, mini ITX motherboard, graphics card, etc…
  • STEGO BOARD 400+ – BOARD 400 and 102 together

They also have 3D printers accessories to create prisms and cubes with the STEGO BOARDs, as well as hard drive caddies, power supply brackets, and cable guard. The developers also released a Windows based simulator to create a virtual prototype.

The STEGO BOARD has been launched on Kickstarter and almost reached its $8,850 CAD target. A $39 CAD pledge (~$31 US) should get you a STEGO BOARD 102 kit, while at the other end of the scale, STEGO BOARD 400+ requires a $105 CAD pledge (~$84 US). Shipping adds $17 CAD to $56 CAD, and sadly the company has decided to limit shipping to USA, Canada, and the United Kingdom only. Delivery is planned for December 2017. The 3D printed accessories are available on a separate website.

Imperas Releases ARM Cortex A53 & A57 Open Source Models for OVPsim

May 8th, 2014 1 comment

Since the end of 2012, it has been possible to use ARM 64-bit Fast models to run code compiled for the new ARMv8 architecture by emulating a 64-bit ARM processor inside an Intel / AMD processor. ARM fast models are not the only “free” option anymore, as Imperas has released OVPsim 20140430 with open source models for ARM Cortex A53 and Cortex A57 cores. OVPsim is a virtual platform that’s available free of charge for personal usage. The simulator itself (OVPsim) is closed source, but processor, peripheral and platform models are released under the Apache License version 2.0.

Open Virtual Platform Architecture with SystemC

Open Virtual Platform using SystemC Environment

OVP models of the ARM Cortex-A53 and Cortex-A57 are fully instruction accurate models, and you can use them for personal with an additional free license key, but if you want to make use of advanced features such as TrustZone and hardware virtualization you’ll need to purchase a commercial version (Imperas Developer or Imperas Advanced Multicore Software Development Kit).

OVPsim is available both for Windows and Linux, and I’ve given it a try in Ubuntu 14.04. The whole process is not as enjoyable as it could be due to registration and licensing requirements. Here’s what I’ve managed to do so far:

  1. Register or login to ovpworld.org
  2. Go to the Download page to download  OVPsim Fast Simulator, the ARM Cortex A models and OVPsim_demo_arm_ARMv8 (single and multi- core demos for Cortex A53 and Cortex A57). You can also find other models, demos, as well as documentation there. You may especially want to download Imperas_Installation_and_Getting_Started.pdf.
  3. Install OVPsim

    You’ll need a accept the software license to complete the installation. I will create Imperas.20140430 directory by default.
  4. Configure OVPsim
  5. Get a license key. The hostid & hostname correspond to your  MAC address and hostname that you can retrieve with /sbin/ifconfig and hostname commands. Email to [email protected] to request a license key for ARMv8 models.
  6. Copy the license keys, you’ve received to $IMPERAS_HOME/OVPsim.lic
  7. Install the ARM models (Cortex A, R, and

    Accept the license agreement to go ahead with the installation.
  8. Install the Cortex A53 and A57 demos (binary and source code).

    You’ll need to accept another license agreement…
  9. You should now be able to go to Imperas.20140430/Demo, and go inside OVPsim_arm_Cortex-A53, OVPsim_manycore_arm_Cortex-A53, OVPsim_arm_Cortex-A57, and OVPsim_manycore_arm_Cortex-A57 to try various demos: linpack, dhrystone, peakSpeed2, fibonacci, and more.

At the time of writing, I’ve only received my standard OVPsim license key, and I’m still waiting for my ARMv8 license key, so I haven’t been able to try it successfully yet, and I get the following error:

Fatal (LIC) No such feature exists.
Feature:       IMP_MODEL_ARMv8
License path:  /home/jaufranc/edev/sandbox/Imperas.20140430/OVPsim.lic:
FLEXnet Licensing error:-5,357

If you want to check out the source, it is located in Imperas.20140430/ImperasLib/source/arm.ovpworld.org/ for processors, peripherals, and platforms. It’s a bunch of hpp files written using SystemC TLM 2, a set of C+ classes or macros used for virtual platform modeling.

You can find more information about OVPSim and various models on ovpworld.org.

[Update: I’ve finally received the IMP_MODEL_ARMv8 license by email, and tried a few tests from a single core Cortex A53 to a 24-core Cortex A57 model.  I’ve also been told the Linux kernel can’t boot on the model right now, but will for next release

Here’s the output for Dhrystone test on a single Cortex A53 core:

Virtual Hardware Platforms: Test & Debug Software Before the Silicon is Ready

March 28th, 2012 2 comments

Historically software could only be tested and debugged when the first silicon sample was ready, and the software team could not participate in the design process.

But thanks to Virtual Hardware Platforms, software can be executed at speeds close to real time on an abstract model of the hardware, available long before a design has been completed. The virtual platform is designed to simplify the creation and support of virtual prototypes and allow design teams to begin developing software weeks to months before a hardware prototype is available, and software teams can use it as their application development platform. For example, Freescale is using a Virtual Hardware Platform for their new Vybrid Controllers to emulate both Cortex A5 and Cortex M4 cores, as well as peripherals and run OS such as Linux or MQX before the Controllers are ready (Q2 2012).

Cadence Virtual System Platform Block Diagram

Cadence Virtual System Platform Software and Hardware

One Virtual Hardware Platform has just won the ACE AWARDS ULTIMATE PRODUCTS of 2011 in the Software category. The Cadence’s Virtual System Platform (part of Cadence System Development Suite) is based on SystemC TLM 2.0 and IEEE 1666 standard (open SystemC models), supports third-party processor models (ARM Fast Models, Imperas OVP models),  Legacy RTL languages (Verilog, VHDL and SystemVerilog), third-party software debuggers (ARM DS 5, Lauterbach, GDB) and scales from single-core to multi-core software development and debug with performance reaching hundreds of MHz.

The Virtual System Platform debug GUI provides fully synchronized, coherent multi-core hardware/software (HW/SW) debugging. It comes with consistent breakpoints, single stepping, probing, tracing, and memory/register source-level debugging in either HW or SW models. Hardware debugging is based on a virtual platform-aware abstraction, built on a core of TLM-aware and SystemC debugging features.  The GUI itself is segmented and can be configured for the views most familiar to software or hardware engineers, or a combination of the two for efficient HW/SW debugging.

Figure 2: Coherent hardware/software debugging

Cadence Virtual System Platform GUI (Click to Enlarge)

You can use models for all sort of basics I/O including UART, keyboard/mouse controller, real time clock, programmable timer, interrupt controller, multimedia card, audio codec interface, programmable LED, color LCD, etc.  Cadence also provides most advanced models for Ethernet, controller, I2C, SPI, bus controller,
serial interface, buffer, memory logger, battery, touch screen input, flash memory, initiator, multi-plexor, arbiter, router and more.

In your use such software to create a system,  you’ll need a Linux machine with the following requirements:

  • 64-bit Red Hat Enterprise or SUSE Enterprise
  • 32GB of RAM

For software development in C/C++/Assembler, a 32-bit or 64-bit Red Hat or Suse Linux distribution with at least 2 GB of RAM is required.

You can get more information on Cadence Virtual System Platform page. Other virtual hardware platforms include Wind River Simics Virtual  Platforms and the open source Imperas OVPsim simulator with examples for different processor models (ARM, MIPS, ARC, NEC v850, openCores OR1K, PowerPC).  All of processor and peripheral models are a;sp open source and can be downloaded (after free registration) on OVPWorld.org forum.