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Embedded Linux Conference & IoT Summit 2018 Schedule

February 13th, 2018 No comments

The Embedded Linux Conference 2018 and the OpenIoT Summit 2018 will jointly take place next month, on March 12 – 14, 2018 in Portland, Oregon, USA. The former is a “vendor-neutral technical conference for companies and developers using Linux in embedded products”, while the latter is a “technical conference for the developers and architects working on industrial IoT”. The Linux Foundation has already published the schedule, and it’s always useful to learn what will be discussed about even for people who won’t attend.

With that in mind, here’s my own virtual schedule with some of the talks I find interesting / relevant to this blog.

Monday, March 12

  • 10:50 – 11:40 – Progress in the Embedded GPU Ecosystem by Robert Foss, Collabora Ltd.

Ten years ago no one would have expected the embedded GPU ecosystem in Linux to be what it is now. Today, a large number of GPUs have Open Source support and for those that aren’t supported yet, improvements are happening at a rapid pace.

In just the last year Vivante GPUs have gained mainline support and Mali GPUs have seen good progress being made.

In this talk, Robert will cover GPUs in the embedded space and give an overview about their current status, what lies ahead and how the Open Source state of the art compares to the proprietary alternatives.

  •  11:50 – 12:40 – Zephyr LTS Release, What to Expect and Why are We Doing This by Anas Nashif, Intel

After eleven 1.x.x releases of Zephyr since the project has launched 2 years ago, the Zephyr project is planning to release Zephyr LTS in 2018 with many new features that have been in the works for the last year, stable APIs and with the goal of taking a subset of the released project code through various certification activities.

In this talk the status plans for Zephyr LTS will be presented and discussed and the next steps that the project will take after the LTS release.

  • 14:00 – 14:50 – Preempt-RT Raspberry Pi Linux by Tiejun Chen, VMware

As we know, the Raspberry Pi is a series of small single-board computers developed in the United Kingdom by the Raspberry Pi Foundation to promote the teaching of basic computer science in schools and in developing countries. Now it is very popular around our IoT world, and you can see many guys use Pi to build great things, and even it can play a role in the production environment. The official Raspberry Pi Linux maintains Linux kernel specific to Pi platform. But it does not include Preempt RT Linux support. Obviously, in some IoT cases we really need to meet hard real time requirement. In this presentation, we will review if-how we can integrate Preempt RT Linux patches to Pi Linux, an see what the problems are for this particular hardware platform.

  • 15:00 – 15:50 – OpenEmbedded/Yocto on RISC-V – New Kid on the Block by Khem Raj, Comcast

RISC-V a new open source ISA based architecture is rapidly gaining acceptance in embedded space. Several core packages e.g. gcc toolchain, linux kernel, binutils, newlib, qemu has already been ported for RISC-V. At this point, OpenEmbedded is one of first embedded linux distribution frameworks to support RISC-V architecture. This talk will cover the status of support as the core support has been upstreamed into OpenEmbedded-core, additionally SOC layer meta-riscv is also created which would serve as common layer for all RISC-V based SOCs.

  • 16:10 – 17:00 – Bluetooth Mesh with Zephyr OS and Linux by Johan Hedberg, Intel

Bluetooth Mesh is a new standard that opens a whole new wave of low-power wireless use cases. It extends the range of communication from a single peer-to-peer connection to a true mesh topology covering large areas, such as an entire building. This paves the way for both home and industrial automation applications. Typical home scenarios include things like controlling the lights in your apartment or adjusting the thermostat. Although Bluetooth 5 was released over a year ago, Bluetooth Mesh can be implemented on any device supporting Bluetooth 4.0 or later. This means that we’ll likely see very rapid market adoption of the feature.

The presentation will give an introduction to Bluetooth Mesh, covering how it works and what kind of features it provides. The talk will also give an overview of Bluetooth Mesh support in Zephyr OS and Linux and how to create new wireless solutions with them.

  • 17:10 – 18:00 – Drive your NAND within Linux by Miquèl Raynal, Bootlin (formerly Free Electrons)

NAND flash chips are almost everywhere, sometimes hidden in eMMCs, sometimes they are just parallel NAND chips under the orders of your favorite NAND controller. Each NAND vendor follows its own rules. Each SoC vendor creates his preferred abstraction for interacting with these chips.

Handling all of that requires some abstraction, and that is currently being enhanced in Linux! A new interface, called exec_op is showing up. It has been designed to match the most diverse situations. It should ease the support of advanced controllers as well as the implementation of vendor-specific NAND flash features.

This talk will start with some basics about NAND memories, especially their weaknesses and how we get rid of them. It will also show how the interaction between NAND chips and controllers has been standardized over the years and how it is planned to drive NAND controllers within Linux.

Tuesday, March 13

  •  10:50 – 11:40 – Comparing and Contrasting Embedded Linux Build Systems and Distributions by Drew Moseley, Mender.io

We will discuss the various options for creating embedded Linux operating systems. We will provide a basic description of each option, including an overview of the workflow for each choice. The talk will cover the advantages and disadvantages of each of these options and provide viewers with a matrix of design considerations to help them pick the right choice for their design. We will cover the following options:

  • Yocto/OpenEmbedded
  • Buildroot
  • OpenWRT/LEDE
  • Slimmed down desktop distributions (e.g. Debian, Raspbian, Ubuntu)

We will also touch upon other tools, such as crosstool-ng and ucLinux, which are peripherally related to building embedded Linux systems. The focus for this section will be to make the viewers aware of these tools as they frequently come up while researching embedded Linux so that you are better informed which tools are available.

  • 11:50 – 12:40 – The Things Network: An IOT Global Phenomenon by Bryan Smith, Tacit Labs

IoT has many connectivity options and systems based on Low Power Networks(LPN’s) such as LoraWAN are showing a great deal of promise. LoraWAN uses the ISM Band which doesn’t require a license for use.

The Things Networks (TTN) is a community about LoraWAN, Low Power Wide Area Network (LPWAN). It’s collaboratively built by passionate people, Open Source Software and Open Governance. The network has a manifesto and fair access policy that governs its use and management. In the session we’ll discuss:

  • The technology behind LoraWAN, TTN and similar networks.
  • TTN’s impact on public and private LPWAN’s.
  • The initiators and communities that install and build LoraWAN gateways.
  • Lastly we’ll discuss the impact of the deployments in real world use cases.

There will also be a live demo of a LoraWAN gateway and node in action on several public networks including TTN as well as others.

  • 14:00 – 14:50 – I + I2C = I3C: What’s in this Additional ‘I’? by Boris Brezillon, Bootlin (formerly Free Electrons)

The MIPI Alliance recently released version 1 of the I3C (pronounce ‘eye-three-see’) bus specification, which is supposed to be an improvement over the long-standing I2C and SPI protocols. Compared to I2C/SPI, I3C provides a higher data rate, lower power consumption and additional features such as dynamic address assignment, host join, in-band interrupts. For the last year or so, Free Electrons has been working with Cadence Design Systems on supporting this new kind of bus in Linux.

With this talk we would like to introduce this new bus and the concepts it brings to the table. We will also detail how we plan to expose the new features exposed by the I3C protocol in Linux and go through future possible improvements of the I3C framework that has already been submitted for review on the Linux kernel mailing list.

  • 15:00 – 15:50 – Android Common Kernel and Out of Mainline Patchset Status by Amit Pundir & John Stultz, Linaro

A quick overview of what the speakers ares going to cover in this session.

  • A brief background on Android common kernels – Out of tree Android patches and how they have evolved over time.
  • The current/active patchset introduction and status – Their use cases in Android and on-going upstreaming efforts if any.
  • A brief Intro to android-mainline-tracking tree.
  • Rebasing latest android-$LTS tree to latest linux release tag
  • Find/Report/Fix Android regressions or ABI breakages in mainline kernel.
  • 16:20 – 17:10 – Tock, The Operating System for a Programmable IoT by Amit Levy, Stanford University

Tock is an open-source operating system for low-power ARM Cortex-M microcontrollers that enables radically different kinds of embedded and IoT products.

In typical embedded systems, every line of code is fully trusted because embedded operating systems lack traditional isolation mechanisms like processes. Unfortunately, this makes developing secure products difficult, and running third-party applications virtually impossible.

Tock uses a language sandbox in the kernel and a process-like hardware enforced mechanism in userspace to isolate third-party and other untrusted code in the system.

In this presentation I’ll introduce Tock’s vision for IoT and how its isolation mechanisms work. Then, I’ll use examples of deployed systems and products using Tock to show how developers can use it to build more secure and extensible IoT systems today.

  • 19:00 – 20:00 – BoF: Open Source Hardware by Drew Fustini, OSH Park

Open Source Hardware BoF (Birds of a Feather) session for those interested in how Open Source Hardware design can benefit embedded Linux systems.

The session will start will start with a short presentation of a few slides to clarify terminology and highlight Open Source Hardware projects relevant to Linux. The panelists will then lead a discussion with the BoF attendees about the benefits and challenges of designing Open Source Hardware.

Jason and Drew can talk about the experience of working with community, manufacturers, and distributors to create an Open Source Hardware platform. Leon can speak about his experience of learning hardware design as a software engineer, and how he took his Raspberry Pi HATs from concept to product. John can speak about his experience leading an Open Source Hardware platform within a large corporation.

Wednesday, March 14

  • 11:05 – 11:55 – Landscape of Linux IoT Ecosystems by Christian Daudt, Cypress Semiconductor

IoT products are getting richer in their functionality daily, and as a result there is a trend for increased use of Linux in these products. As we are early in the IoT ecosystem cycle, there is a large number of projects and products vying for developer attention as frameworks and protocols to be used in new product development. This talk provides an overview of the options available and how they relate to each other. It covers OS stacks such as EdgeX Foundry, Automotive Grade Linux, Android Things, IoTivity, Tizen, etc.. as well as IoT-tailored cloud integrations from cloud vendors such as AWS, Google, Microsoft.

  • 12:05 – 12:55 – CPU Power Saving Methods for Real-time Workloads by Ramesh Thomas, Intel

Configurations created for real time applications mostly disable power management completely to avoid any impact on latency. It is however, possible to enable power management to a degree to which the impact on latency is tolerable based on application requirements. This presentation addresses how CPU idle states can be enabled and tuned to allow power savings while running real time applications.

The presentation will give a background of the issues faced by real-time applications when CPU power management is enabled. It will then explain tools, configurations and methods that can be used to tune applications and CPU power management in the kernel to be able to save power without impacting the deterministic latency tolerance requirements.

  • 14:30 – 15:20 – Debian for Embedded Systems: Best Practices by Vagrant Cascadian, Aikidev, LLC

As embedded hardware becomes more capable, Debian becomes an attractive OS for projects. Debian provides clear licensing, a solid technical foundation, and over twenty-five thousand software projects already available within Debian.

Unfortunately, embedded system projects may make changes to a customized Debian OS in ways that make it difficult to apply security updates or system upgrades. This can lead to an unmaintained fork of Debian with long-standing security vulnerabilities unfixed in the hands of end-users. Nobody likes bit-rot.

Many of these common pitfalls can be mitigated or avoided entirely by understanding Debian’s culture, infrastructure, technical norms, and contribution processes. These understandings will improve embedded systems using Debian over the long-term.

  • 15:30 – 16:20 – Civil Infrastructure Platform: Industrial Grade Open Source Base-Layer by Yoshitake Kobayashi, Toshiba Corporation, Software Development and Engineering Center

The Civil Infrastructure Platform (CIP) is creating a super long-term supported (SLTS) open source “base layer” of industrial grade software. The base-layer consists of the SLTS kernel and a basic set of open source software and standardization concepts. By establishing this “base layer,” the CIP Project will enable the use and implementation of software building blocks in civil infrastructure projects. Currently, all civil infrastructure systems are built from the ground up, with little re-use of existing software building blocks, which drains resources, money and time. In this devroom, we’ll share project strategy, use cases, roadmap, milestones and policies. We’ll also share technical details for each development activities for the base-layer that includes open source, real-time development tools, testing and answer questions.

  • 16:30 – 17:20 – 3D Printing with Linux and Xenomai by Kendall Auel, 3D Systems Corp.
Software running on embedded Linux with Xenomai is used to control a 3D printer. The lessons learned and practical advice will be shared in this presentation. There were many challenges to overcome. A complete 3D printing system requires precise motion control, thermal control, material delivery and monitoring, and coordinated data transfers. All concurrent real time processes must be coordinated and managed, while providing interactive response to user input. In parallel with the real time processing, the system must slice the 3D model into layers for printing, which is by its nature a compute-bound application. The dual-kernel architecture of Linux with Xenomai was ideal for maintaining low and predictable latencies for real time control, while allowing the complex and resource intensive slicing application to run in parallel.

Selecting the sessions was not easy as most talks are relevant, so I’d recommend checking out the whole schedule.

The Embedded Linux Conference & OpenIoT Summit require registration with the fees listed as follows:

  • Early Bird Fee: US$550 (through January 18, 2018)
  • Standard Fee: US$700 (January 19,  February 17, 2018)
  • Late Fee: US$850 (February 18, 2017 – Event)
  • Academic Fee: US$200 (Student/Faculty attendees will be required to show a valid student/faculty ID at registration.)
  • Hobbyist Fee: US$200 (only if you are paying for yourself to attend this event and are currently active in the community)

SiFive Introduces HiFive Unleashed RISC-V Linux Development Board (Crowdfunding)

February 4th, 2018 19 comments

RISC-V free and open architecture has gained traction in the last couple of years. SiFive has been one of the most active companies with RISC-V architecture, introducing Freedom U500 and E500 open source RISC-V SoCs in the summer of 2016, before launching their own HiFive1 Arduino compatible board, and later the official Arduino Cinque board.

That’s fine if you are happy with MCU class boards, but RISC-V is getting into more powerful processors, and recently got initial support o Linux 4.15, so it should come as no surprise the company has now launched HiFive Unleashed, the first RISC-V-based, Linux-capable development board.

Click to Enlarge

HiFive Unleashed key features and specifications:

  • SoC – SiFive Freedom U540 with 4x U54 RV64GC application cores @ up to 1.5GHz with Sv39 virtual memory support, 1x E51 RV64IMAC Management Core, 2 MB L2 cache;  28 nm TSMC process
  • System Memory – 8GB DDR4 with ECC
  • Storage –  32MB Quad SPI Flash from ISSI, MicroSD card for removable storage
  • Connectivity – Gigabit Ethernet port
  • Debugging – Micro USB port connector to FTDI chip
  • Expansion – FMC Connector for future add-in cards
  • Misc – On-off switch, various configuration jumpers
  • Power Supply – 12V DC input
  • Dimensions – TBD

Freedom U540 SoC Block Diagram

The board is mostly for developers and enthusiasts and currently the main use cases including building a RISC-V computer, adding features to Linux, or port packages to a Linux distribution. It’s unlikely to be a plug and play board suitable for anybody, at least at the beginning.

The company simultaneously unveiled & showcased the board at FOSDEM 2018 (See embedded video below), and launched it on CrowdSupply with a symbolic $1 funding goal. The downside is that as with most new technologies it’s pretty expensive at first, and you’d have to pledge $999 to get the board shipped at the end of June 2018, or $1,250 to get one of the first 75 boards in March/April 2018. Shipping is free to the US, but adds another $40 to the rest of the world. More details may eventually be available in the product page.

 

SiFive U54-MC Coreplex is the First Linux Ready RISC-V based 64-bit Quad-Core Application Processor

October 6th, 2017 8 comments

We first covered SiFive when they unveiled their open source Freedom RISC-V SoCs. Since then, they moved away from open source for their customizable IP, since their customers did not require fully open source designs, but kept releasing more RISC-V cores such as 32-bit E31 Coreplex & 64-bit E51 Coreplex, as well as offering their one-time fee pricing without recurring royalties, contrary to what some competitors – such as Arm – are doing.

The company has now just announced U54-MC Coreplex quad core real-time capable application processor with support for full featured operating systems such as Linux.

Click to Enlarge

U54-MC Coreplex main specifications / features:

  • Fully compliant with the RISC-V ISA specification
  • 4x RV64GC U54 Application Cores
    • 32KB L1 I-cache with ECC, 32KB L1 D-cache with ECC
    • 8x Region Physical Memory Protection
    • 48x Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • 1x RV64IMAC E51 Monitor Core
    • 4KB L1 I-Cache with ECC
    • 8KB DTIM with ECC
    • 8x Region Physical Memory Protection
    • 48x Local Interrupts
  • Fully Coherent TileLink Bus
  • Integrated 2MB L2 Cache with ECC
  • Real-time capabilities – Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
  • CLINT for multi-core timer and software interrupts
  • PLIC with support for up to 511 interrupts with 7 priority levels
  • Debug with instruction trace
  • U54 Performance – 1.7 DMIPS/MHz; 2.75 CoreMark/MHz

U54-MC Coreplex has been taped out as part of Freedom Unleashed platform with all 5 cores, including U54 and E51, running at over 1.50 GHz and manufactured using 28nm technology. The company compares it to Arm Cortex A35 cores in the table below which shows the added features.

U54-MC Coreplex ARM Cortex-A35
RV64GC
M + S + U Mode
ARMv8-A, AArch32, AArch64
16 bit instructions AArch32 only
Physical Memory Protection (PMP) and MMU None, MMU only
Real-time capable Not applicable
E51 Monitor Core Requires additional IP
Integrated interrupt controller Requires additional IP

More details about the U54-MC Coreplex can be found on the product page, and the company plans to release an U54-MC Coreplex development board in Q1 2018.

Categories: Linux, Processors, SiFive Tags: risc-v, sifive, soc

LoFive is a Tiny Open Source Hardware Board based on SiFive FE310 RISC-V Open SoC

August 31st, 2017 11 comments

Do you remember HiFive1? It’s an Arduino compatible board based on the SiFive FE310 open source RISC-V SoC. Michael Welling has now started working on LoFive board using the same processor, but in a much smaller & breadboard friendly form factor.

LoFive board specifications:

  • MCU – SiFive Freedom E310 (FE310) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz)
  • Storage – 128-Mbit SPI flash (ISSI IS25LP128)
  • Expansion – 2x 14-pin headers with JTAG, GPIO, PWM, SPI, UART, 5V, 3.3V and GND
  • Misc – 1x reset button, 16 MHz crystal
  • Power Supply – 5V via pin 1 on header; Operating Voltage: 3.3 V and 1.8 V
  • Dimensions – 38 x 18 mm (estimated)

The board will be programmable with Arduino IDE + Cinco just like HiFive1 board.

Click to Enlarge

The board is also open source hardware, so beside the aforelinked info on Hackster,io, you’ll also find the KiCAD schematics, PCB layout, and 3D renders, released under CERN Open Hardware License v1.2, on Github.

Arduino Cinque Combines SiFive RISC-V Freedom E310 MCU with ESP32 WiFi & Bluetooth SoC

May 22nd, 2017 5 comments

SiFive introduced the first Arduino compatible board based on RISC-V processor late last year with HiFive1 development board powered by Freedom E310 MCU, but  the company has been working with Arduino directly on Arduino Cinque board equipped with SiFive Freedom E310 processor, ESP32 for WiFi and Bluetooth, and an STM32 ARM MCU to handle programming.

Click to Enlarge

Few other technical details have been provided for the new board, but since it looks so similar to HiFive1, I’ve come with up with preliminary/tentative Arduino Cinque specifications:

  • MCU – SiFive Freedom E310 (FE310) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz)
  • WiSoC – Espressif ESP32 for WiFi and Bluetooth 4.2 LE
  • Storage – 32-Mbit SPI flash
  • I/Os
    • 19x Digital I/O Pins
    • 19x external interrupt pins
    • 1x external wakeup pin
    • 9x PWM pins
    • 1/3 SPI Controllers/HW CS Pins
    • I/O Voltages –  3.3V or 5V supported
  • USB – 1x micro USB port for power, programming and debugging
  • Misc – 6-pin ICSP header, 2x buttons
  • Power Supply – 5 V via USB or 7 to 12V via DC Jack; Operating Voltage: 3.3 V and 1.8 V
  • Dimensions – 68 mm x 51 mm

Image Source: Olof Johansson

The board will obviously be programmable with the Arduino IDE, something that’s already possible on HiFive5 possibly with limitations since the platform is still new. Freedom E310 SoC RTL source code is also available via the Freedom SDK.

There’s no availability nor price information, but considering HiFive1 board is now sold for $59, and Arduino Cinque may cost about the same or a little more once it is launched since it comes with an extra ESP32 chip, but a smaller SPI flash. Hopefully, it will take less time than the one year gap experienced between the announcement and the release of Arduino Due.

SiFive Launches 32-bit E31 Coreplex & 64-bit E51 Coreplex RISC-V Processors, Reveals Pricing

May 5th, 2017 4 comments

SiFive unveiled their Freedom U500 and E500 open source RISC-V SoCs last year, and a little layer launched HiFive1 Arduino compatible development board based on SiFive Freedom E310 processor. The company has now launched their non-open source Coreplex IP also based on RISC-V ISA with the 32-bit E31 Coreplex and 64-bit E51 Coreplex, and explained details about pricing.

E51 Coreplex – Click to Enlarge

Some of the key features of the processors are listed below:

  • E31 Coreplex
    • 32-bit RV32IMAC core @ 900 to 1.5 GHz (with 28nm process)
    • Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support
    • Up to 16 local interrupts with vectored addresses
    • Performance – 1.61 DMIPS/MHz  ; 2.73 Coremark/MHz
    • Power Consumption
      • 28nm HPC process – Core only: 150 DMIPS/mW ; Coreplex: 41 DMIPS/mW
      • 55nm LP process – Core only: 95 DMIPS/mW; Coreplex: 16 DMIPS/mW
    • Applications: Edge Computing, Smart IoT or Wearables.
    • Suited to replace the Cortex-M3 and Cortex-M4, but provides even higher performance without sacrificing area or power.
  • E51 Coreplex
    • 64-bit RV64IMAC embedded core @ 900 to 1.5 GHz (28nm process)
    • Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support
    • Support for up to 40 physical address bits
    • Up to 16 local interrupts with vectored addresses
    • Performance – 1.8 DMIPS/MHz  ; 2.76 Coremark/MHz
    • Power Consumption
      • 28nm HPC process – Core only: 125 DMIPS/mW ; Coreplex: 36 DMIPS/mW
      • 55nm LP process – Core only: 36 DMIPS/mW; Coreplex: 15 DMIPS/mW
    • Applications:
      • System or host control core within a larger 64-bit SoC
      • SSD controllers and network processors which require 64-bit compute without the requirement of virtual memory or full-featured operating systems.

SiFive R31 Coreplex Block Diagram – Click to Enlarge

If you want to manufacture an ARM processor, you first need to buy a license before accessing any information, and once you’re shipping your chips, you’ll pay royalties for each SoC sold with one or more ARM cores. SiFive business model is different. First, it’s free to try Coreplex IP on FPGA boards such as Digilent Arty, or evaluate RTL code in your own environment, so you don’t need to commit to any large investment before knowing whether you’ll go ahead with the cores. SiFive Coreplex IP is also royalty-free so how much you pay does not depend on how many chips you sell, and the way they make money is through a one-time license that costs $275,000 and up for E31 Coreplex, and $595,000 and up for E51 Coreplex with the exact price depending on options.

You’ll find the full details on Sifive Coreplex IP product page.

Categories: Hardware Tags: fpga, risc-v, sifive, soc

$59 HiFive1 Arduino Compatible Board is Powered by Sifive Open Source RISC-V MCU (Crowdfunding)

November 30th, 2016 8 comments

Royalty-free RISC-V instruction sets has been getting in the news in the last few years with various MMU designs from companies or projects like lowRISC, PULPino, and SiFive, and recently there are been rumors that Samsung may use RISC-V in their future IoT SoCs. Many projects are still in progress, and while you can get involved in OnChip Open-V MCU crowdfunding campaign to their get the MCU or a development board, the cost for the MCU ($49) and development board ($99) is a little on the high side, and delivery is expected in 2018 for most rewards. SiFive appears to have a more interesting open source RISC-V solution with HiFive1 Arduino compatible board going for $59 and slated to ship between December 2016 and February 2017.

HiFive1 Board

HiFive1 Board

HiFive1 development board specifications:

  • MCU – SiFive Freedom E310 (FE310) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz)
  • Storage – 128 Mbit SPI flash
  • I/Os
    • 19x Digital I/O Pins
    • 19x external interrupt pins
    • 1x external wakeup pin
    • 9x PWM pins
    • 1/3 SPI Controllers/HW CS Pins
    • I/O Voltages –  3.3V or 5V supported
  • USB – 1x micro USB port for power, programming and debugging
  • Power Supply – 5 V via USB or 7 to 12V via DC Jack; Operating Voltage: 3.3 V and 1.8 V
  • Dimensions – 68 mm x 51 mm
  • Weight – 22 g

sifive-fe310

The company’s Freedom SDK with the RTL files for Freedom E310 (and U500) MCUs will allow you to actually play and/or modify the MCU on an FPGA platform, which can be useful for education or if you want to create your own MCU based on SiFive design. If you don’t have the know-how the company’s “chips-as-a-service” offering can customize FE310/U500 MCU to meet your needs.

 Most users will probably just program the board with the Arduino IDE, and many of the usual development tools have already been ported to RISC-V architecture. The processor is also quite faster than our typical Arduino, being about 10 times faster than Intel Curie and Atmel SAMD21G18 used in respectively Arduino 101 and Arduino Zero.

hifive1-vs-arduino

Power efficiency (@ 200 MHz) appears to be much higher compared to Atmel AVR and Intel Quark. However, based on ARM Cortex M0 product brief (I could not find data for M0+), 10DMIPS/mW can be achieved using 180ULL process, and 75 DMIPS/mW with 65LP process.

If you are interested, you can get the board on Crowdsupply with the HiFive1 devkit going for $59 and shipping in February 2017, but if you want to have a piece of history, you may consider HiFive1 Founder Edition for $79 with SiFive Founding Team’s Signature on the silkscreen and shipping at the end of December 2016. Shipping is free to the US, and $15 to the rest of the world.

RISC-V could be a serious competitor to ARM and MIPS in the MCU/IoT space in the years ahead, as it’s royalty-free, and the RISC-V foundation has many players including some heavy weights such as Google, AMD, Microsemi, Qualcomm, Nvidia and more…

Thanks to noone for the tip.

OnChip Open-V Open Source 32-bit RISC-V Processor Launched on CrowdSupply

November 23rd, 2016 10 comments

Open source hardware gives mostly full control over software and hardware, but there are different levels of openess, with some companies wrongly claiming their product to be open source hardware – with a nice accompanying logo – once they dump some source code somewhere and publish the PDF schematics, while others are doing it right with the release of schematics and PCB layout in source format, as well as software and proper documentation. However even for the latter group, the actual chips are closed source bought directly from silicon vendors or their distributors. So the good news is that you now have the opportunity to bring the meaning of open source hardware to a whole new level thanks to OnChip Open-V 32-bit  processor that is open source, and getting launched on Crowd Supply crowdfunding platform.

open-vOnChip Open-V is based on RISC-V (pronounced “risk-five”), comes with peripherals, and should be competitive against ARM Cortex M0 based micro-controllers. The MCU would also be the first RISC-V chip available on the market.

Open-V chip specifications:

  • Processor – RISC-V ISA version 2.1 @ up to 160 MHz
  • Memory – 8 KB SRAM
  • Clock – 32 KHz – 160 MHz; Two PLLs, user-tunable with muxers and frequency dividers
  • Analog Signals
    • 2x 10-bit ADC channels, each running at up to 10 MS/s
    • 2x 12-bit DAC channels
  • Timers
    • 1x general-purpose 16-bit timer
    • 1x 16-bit watch dog timer (WDT)
  • General Purpose Input/Ouput
    • 16x programmable GPIO pins
    • 2x external interrupts
  • Interfaces
    • SDIO port for example to add a micro SD slot
    • 2x SPI ports, I2C, UART
  • Programming and Testing
    • Built-in debug module for use with gdb and JTAG
    • Programmable PRBS-31/15/7 generator and checker for interconnect testing
  • 1.2 V operation
  • Package – QFN-32
Open-V vs

Open-V vs STM32L0 vs PIC32MX vs SAMD21 vs EFM32Z vs LPC812M vs MSP430F vs  ATMega-328p

You can find the complete OnChip Open-V design, including the RTL (register-transfer level) files for the CPU and peripherals, as well as the development and testing tools in Github, all released under the MIT license. The source can be used to teach silicon designs, debug and correct errors in the chip without asking the vendor, and if you plan to roll your own cut reducing costs by cutting out licensing fees.

Development Board for Open-V RISC-V MCU

Development Board for Open-V RISC-V MCU

Now most people would not be able to do much with just the MCU only, so the company will also develop an Open-V development board with the following specifications:

  • MCU – 32-pin QFN Open-V microcontroller
  • Storage – 32 KB EEPROM, microSD receptacle
  • USB – 1x USB 2.0 controller + micro USB port for power and data
  • Expansion – Breadboard-compatible breakout header pins
  • Debugging – JTAG connector
  • Power – 1.2 V and 3.3 V voltage regulators
  • Dimensions: 55 mm x 30 mm

The board will be programmed with the Arduino IDE, so it should be not harder than programming any Arduino boards, or any platforms using the popular IDE.

However, getting silicon to market is an expensive endeavor, and the only way to bring prices down to to manufacture millions of units. OnChip is starting small with a first target of 70,000 chips, which still converts to a $480,000 funding target. There are several ways to help reach that goal starting with a $49 “Chip Pioneer” reward to get on of the first chips to be manufactured, but the most popular reward is likely to be Open-V development board going for $99. Shipping is free to the US and $7 to the rest of the world. You’ll also have to patient, quite understandably due to the task at hand,  as rewards are only expected to ship in April and May 2018, unless you pledge for one of the most expensive rewards giving access to early chips in May 2017.

Thanks to Nanik the tip.