SiFive U8-Series Out-of-Order RISC-V Core IP Takes on Arm Cortex-A72 Core

SiFive U8-Series Processors U84 and U87

Earlier this week, we wrote about SiFive Shield open security platform as the equivalent of Arm TrustZone security technology, but the company had had another important announcement this week with the introduction of SiFive U8-Series Out-of-Order (OoO) RISC-V Core IP with much higher performance than the company’s earlier U7-series core and competing with Arm Cortex A72 core. At first, the company will offer two standard cores with SiFive U84 RISC-V core optimized for power efficiency and area efficiency, and the SiFive U87 RISC-V core with vector processing. SiFive U84 Performance & Efficiency We do not have much information about U87, but SiFive already published some interesting details about U84 cores. SiFive U84 core offers about 3.1 times higher performance compared to their earlier U74 standard core thanks to a 2.3x increase in IPC combined with a 1.4x increase in maximum frequency. Compared to SiFive U54, U84 delivers 5.3x higher performance (isolated process) and when taking into account the improved process …

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SiFive Shield is an Open Security Platform for RISC-V Processors

SiFive WorldGuard

Most Arm processors and Armv8-M microcontrollers support Arm TrustZone security with hardware-enforced isolation built into the CPU. But so far, I had not read anything about equivalent solutions for RISC-V processors. It turns out Hex-Five’s MultiZone security is one of the RISC-V hardware-security providing an answer to Arm TrustZone, and besides checking out the presentation slides, you can also watch the video filmed at RISC-V Workshop Taiwan last March. But what brought me to write about RISC-V security is SiFive announcement for their Shield open security platform for RISC-V processors SiFive Shield Overview SiFive Shield is an open, scalable security platform designed for RISC-V processors.  It supports root-of-trust, customizations, and offers per-memory protected memory regions and multi-core privilege modes.  Combined with SiFive WorldGuard, SiFive Shield enables greater isolation. SiFive WorldGuard Isolation SiFive WorldGuard is a fine-grain security model for isolated code execution and data protection. It offers core-driven and process-id driven modes to offer data protection for core, cache, interconnect, …

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Wio Lite RISC-V WiFi Board with ESP8266 Module Launches for $6.9

Wio Lite RISC-V

Released this summer, GigaDevice GD32V generated a lot of buzz, as a cheap general-purpose 32-bit RISC-V MCU, and soon after the $5 Longan Nano development board with LCD display and enclosure was launched to the market. However, many applications benefit or require some network connectivity with WiFi. Espressif Systems is a founding member of the RISC-V Foundation, so RISC-V WiSoCs (Wireless SoCs) are coming, but AFAIK none of those are available yet. In the meantime, Seeed Studio has launched Wio Lite RISC-V board which brings WiFi connectivity to GD32V MCU through an ESP8266 WiFi module. Wio Lite specifications: MCU – Gigadevice GD32VF103CBT6 RISC-V (rv32imac) microcontroller @ 108 MHz with 128KB Flash, 32KB SRAM Wireless Module – ESP8266 WiFi Wio Core with 802.11b/g/n/ WiFi 4 connectivity Storage – MicroSD card slot USB – 1x USB Type-C port for power and programming Expansion – I/O headers for GD32 MCU, I/O header for Wio core ESP8266 module Debugging – Unpopulated 6-pin JTAG header …

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PicoLibC is a Lightweight C library for Embedded Systems

PicolibC

Well-known developer,  Keith Packard has recently announced the launch of “picolibc” through his blog.  Picolibc is a C Library for embedded systems which  is suitable for small micro-controllers, and this standard C library API’s allows to run even in low memory (RAM) devices. This is an upgraded version of “newlib-nano” with few interesting changes which includes replacement of “stdio” lib with ATMEL-specific printf code adopted from avrlibc. As part of this library, Keith also launched picocrt,  which is responsible for initializing memory and invoking various constructors before calling its own C program, the main function. Features picolibc is a revised version of newlibc, without full-fledged stdio lib and uses lightweight stdio lib from avrlibc, which is more suitable to low memory embedded devices. Meson build-system eases the build process of picolibc source tree for various target platform and hardware. Updated the math test suite to use Glibc as a reference The library is BSD licensed, and non-BSD components were removed …

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Linux 5.3 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linux 5.3 Changelog

Linus Torvalds has just announced the release of Linux 5.3: So we’ve had a fairly quiet last week, but I think it was good that we ended up having that extra week and the final rc8. Even if the reason for that extra week was my travel schedule rather than any pending issues, we ended up having a few good fixes come in, including some for some bad btrfs behavior. Yeah, there’s some unnecessary noise in there too (like the speling fixes), but we also had several last-minute reverts for things that caused issues. One _particularly_ last-minute revert is the top-most commit (ignoring the version change itself) done just before the release, and while it’s very annoying, it’s perhaps also instructive. What’s instructive about it is that I reverted a commit that wasn’t actually buggy. In fact, it was doing exactly what it set out to do, and did it very well. In fact it did it _so_ well that …

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$5 Longan Nano GD32V RISC-V Development Board Comes with LCD Display and Enclosure

Longan Nano

There’s been some exciting news about RISC-V microcontrollers recently with Gigadevice announcing GD32V, one of the first RISC-V general-purpose microcontrollers, which outperforms its Arm Cortex-M3 equivalent in terms of performance and power consumption. The company also announced some development boards, but they are not quite that easy to purchase being listed on Tmall website in China. The good news is that Sipeed has introduced Longan Nano development board powered by GD32VF103CBT6 microcontroller, and it’s up for sale on Seeed Studio for $4.9. Longan Nano board specifications: MCU – Gigadevice GD32VF103CBT6 32-bit RISC-V (rv32imac) microcontroller @ 108 MHz with 128KB Flash, 32KB SRAM Storage – MicroSD card slot Display – 0.96″ 160×80 IPS RGB LCD connected via SPI USB – 1x USB Type-C port for power and programming Expansion – 2x 16 through holes (2.54mm pitch) exposing 3x USART, 2x I2C, 3x SPI, 2x I2S, 2x CAN, 1x USBFS (OTG), 2x ADC (10 channel), 2x DAC Timers – 4x general-purpose 16-bit …

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AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets

Andes N22 RISC-V vs Arm Cortex M3 / M0+

We covered Gigadevice GD32V general-purpose microcontroller with a RISC-V “Bumblebee” core last week, and I was informed that Andes Technology had recently introduced AndesCore N22 RISC-V “Bumblebee” IP core capable of supporting either RV32IMAC or RV32EMAC instruction sets. A web search did not reveal any specific information about what “Bumblebee” RISC-V cores are exactly, or maybe it’s in reference that many can be coupled in parallel. But that’s just a small detail, let’s check out in some details what AndesCore N22 core has to offer. The RISC-V core is designed for entry-level MCUs found in IoT devices and wearables, and is capable of deeply embedded protocol processing for I/O control, storage, networking, AI and AR/VR. Highlights of AndesCore N22: AndeStar V5 (RV32IMAC) / V5e (RV32EMAC) Instruction Set Architecture (ISA), compliant to RISC-V technology plus Andes extensions architectured for performance and functionality enhancements 32-bit, 2-stage pipeline CPU architecture 16/32-bit mixable instruction format for compacting code density Branch prediction to speed up …

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OrangeCrab is an Open Source Hardware, Feather-Compatible Lattice ECP5 FPGA Board

Lattice ECP5 Feather board

Lattice ECP5 FPGA powered OrangeCrab is the work of Greg Davill who designed the Adafruit Feather-compatible board in KiCAD, crowdsourced schematics/PCB checking and published his progress on Twitter, and published the files  of the open source hardware board on Github. OrangeCrab board hardware specifications: FPGA – Lattice ECP5 25/45/85 variants System Memory – Up  to 8Gbit DDR3 Memory (x16) Storage – 128Mbit QSPI FLASH Memory (Bitstream + User storage), 4-bit MicroSD socket USB – Micro USB connector, full-speed direct USB connection to FPGA Programming – 10-pin FPGA programming header Expansion – I/O’s broken out via 30 through holes: GPIO, SPI, I2C, Analog, … 7x diff pairs, 1x single ended only Misc – Reset Button, charge LED (Green:  external power, Yellow: when charging, No color: when running off battery), 48MHz Oscillator Power Supply – 5V via USB port, battery header for LiPo battery + battery charger chip Dimensions – Adafruit Feather form factor There aren’t any sample FPGA bitstream on Github …

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