Ingenic T31 AI Video Processor Combines MIPS & RISC-V Cores

Last week we asked “is MIPS dead?” question following the news that Wave Computing had filed for bankruptcy, two MIPS Linux maintainers had left, and China-based CIP United now obtained the exclusive MIPS license rights for mainland China, Hong Kong, and Macau. Ingenic is one of those Chinese companies that have offered MIPS-based processors for several years, but one commenter noted that Ingenic joined the RISC-V foundation, and as a result, we could speculate the company might soon launch RISC-V processors, potentially replacing their MIPS offerings. But Ingenic T31 video processor just features both with a traditional Xburst  MIPS Core combines with a RISC-V “Lite” core Ingenic T31 specifications: Processors XBurst 1 32-bit MIPS core clocked at 1.5GHz with Vector Deep Learning accelerator based on SIMD128, 64KB + 128KB L1/L2 Cache RISC-V independent lite core System Memory – Built-in 512Mbit (64MB) or 1Gbit (128MB) DDR2 Storage – Quad SPI flash, NAND flash, SD card I/F Display I/F – Supports Smart …

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Getting Started with RT-Thread Nano RTOS on RISC-V Processors

CNXSoft: This is a guest post by RT-Thread explaining how to create your first program running on their real-time operating system using a GD32V  RISC-V MCU board as an example. This article describes how to “port” RT-Thread Nano to the RISC-V architecture, using the Eclipse IDE, GCC toolchain, and a basic project for the Gigadevice GD32V103 MCU. Foreword RT-Thread is an open-source embedded real-time operating system. RT-Thread has a standard version and a Nano version. The standard version consists of a kernel layer, components and service layer, and IoT framework layer, while the Nano version has a very small footprint and refined hard real-time kernel, better suited to resource-constrained microcontroller units (MCU). The main steps for porting Nano are as follows: Prepare a basic Eclipse project and get the RT-Thread Nano source code. Add the RT-Thread Nano source code to the base project and add the corresponding header path. Modify Nano, mainly for the interrupt, clock, memory, and application, to …

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Google Summer of Code 2020 Mentoring Organizations Announced

Every year Google organizes the Summer of Code inviting students to work on open-source projects and even get paid for it. The company first select mentoring organizations, before accepting applications from students. Google has now announced the 200 organizations/projects that have been selected for Summer of Code 2020. Many projects are higher-level software development such as web development or desktop programs development but there are also projects closer to the hardware-side of things with operating systems and multimedia projects. Some interesting organization and/or  projects part of the audio / graphics / video / multimedia category include: apertus Association developing AXIOM open-source hardware camera FFmpeg multimedia framework to decode, encode, transcode, de/mux, stream, filter & play audio and video stream found in many projects OpenCV Open Source Computer Vision Library for computer vision and deep learning applications. XOrg foundation for X Window System and related projects such as Mesa, DRI, Wayland, etc… Some operating systems part of GSoC 2020 include: Amahi …

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RISC-V based PolarFire SoC FPGA and Devkit Coming in Q3 2020

Microsemi unveiled PolarFire FPGA + RISC-V SoC about one year ago, but at the time, development was done on a $3,000 platform with SiFive U54 powered HiFive Unleashed board combined with an FPGA add-on board from Microsemi. I’ve now been informed that Microchip has announced its Linux-capable PolarFire FPGA+RISC-V SoC would start shipping in Q3 2020 at the RISC-V summit and that a development kit will be sold for a few hundred dollars. PolarFire SoC FPGA   PolarFire SoC FPGA key features and specifications: Mid-Range FPGA optimized for Low Power High-speed serial connectivity with built-in multi-gigabit/multi-protocol transceivers from 250 Mbps to 12.7 Gbps Up to 461k logic elements consisting of a 4-input Look-Up Table (LUT) with a fracture-able D-type flip-flop Up to 31.6 Mb of RAM Power optimized transceivers Up to 1420 18 × 18 multiply-accumulate blocks with hardened pre-adders Integrated dual PCIe for up to ×4 Gen 2 Endpoint (EP) and Root Port (RP) designs High-Speed I/O (HSIO) supporting …

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Think Silicon NEOX|V is the First RISC-V ISA based GPU

RISC-V GPU

We are seeing more and more RISC-V microcontrollers and processors hitting the market, but so far they all lacked a GPU for 3D graphics acceleration. Think Silicon, the make of NEMA GPU for IoT and wearables, has now announced it will demonstrate NEOX|V GPU, the first RISC-V ISA based 3D, at the RISC-V Summit at the San Jose Convention Center, on December 10-12, in San Jose, California. NEOX|V key features: Parallel multi-core and multi-threaded architecture based on the RISC-V64GC ISA instruction set with adaptive NoC (Networks-on-Chip) Configurable from 4 to 64 cores Variety of cache sizes and thread counts organized in 1 to 16 cluster elements Variety of cluster/core configurations with compute power ranging from 12.8 to 409.6 GFLOPS at 800 MHz Support for FP16, FP32, and FP64 plus SIMD instructions Beside 3D graphics, the RISC-V GPU can also be used for machine learning, vision/video processing, and open GPGPU compute framework applications. NEOX|V SDK features System Verilog RTL, Integration Tests, …

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GigaDevice Releases GD32V RISC-V MCU and Development Boards

GD32VF103 RISC-V General Purpose MCU

A few years ago, we came across GigaDevice GD32 microcontroller compatible with STMicro STM32F103, but with a higher 108 MHz clock, and zero wait state internal flash. The MCU was also a drop-in replacement for the STMicro alternative since beside being software compatible, it was also pin-to-pin compatible. The company is now back with a new microcontroller, but it’s not Arm-based. Instead, GigaDevice GD32V is based on RISC-V open source architecture. GD32V General Purpose RISC-V MCU GigaDevice GD32V is a 32-bit RISC-V general-purpose MCU that targets industrial and consumer applications such as IoT, edge computing, artificial intelligence and “vertical industries”. The new GD32VF103 series RISC-V MCU family features 14 models with the following key specifications: Core – GD32VF103 32-bit rv32imac RISC-V “Bumblebee Core” @ 108 MHz Memory – 8KB to 32KB SRAM Storage  – 16KB to 128KB flash Peripherals – USB OTG and CAN 2.0B I/O – 3.3V, 5V tolerant Supply Voltage – 2.6 to 3.6V Package – QFN36, LQFP48, …

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miriac MPX-LS1028A NXP QorIQ LS1028A SoM Targets TSN Applications with HMI Display

LS1028A System-on-Module

NXP QorIQ LayerScape LS1028A communication SoC was first unveiled in March 2017 with two Armv8 cores, GPU and LCD controller for HMI systems, as well as Time-Sensitive Networking (TSN) capabilities useful in industrial settings. As usual it takes a while before the company finalize their design and software support, but LS1028A has started to appear at least in one hardware platform that’s supposed to launch this quarter (Q2 2019): MicroSys miriac MPX-LS1028A system-on-module. miriac MPX-LS1028A SoM specifications: SoC – NXP QorIQ LS1018 / LS1028 single / dual core Arm Cortex-A72 clocked at up to 1.3 GHz with MXC Vivante GPU, Mali Display Processor, configurable cryptographic offload engines (Optional: LS1017/LS1027 without GPU for cost saving) System Memory – Up to 4GB 32 Bit DDR4 with ECC RAM at up to 1600 MT/s Storage – Up to 256MB Serial NOR Flash & up to 4GB Serial NAND Flash; EEPROM MXM 2.0 edge connector with: Up to two eSDHC interfaces (SD3.0, up to …

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Cypress PSoC 64 Microcontrollers Target Secure IoT Applications

PSoC 64 Secure MCU

If you are like me, you probably don’t remember, but back in 2017 Arm announced the Platform Security Architecture (PSA) that defines a set of requirements to secure low cost Internet of Things devices. There’s now at least on PSA compliant microcontroller, as Cypress Semiconductor introduced their PSoC 64 Secure MCU at Embedded World 2019 last month. The press release claims that PSoC 64 MCU family is one of “the first Arm Cortex-M processors to be certified as Level 1 compliant within the Arm Platform Security Architecture (PSA) certification scheme, PSA Certified, utilizing a secure Trusted Firmware-M (TF-M) implementation integrated into the Arm Mbed OS open-source embedded operating system”. PSoC 64 secure MCU key features and specifications: Arm Cortex-M4F core with 22‑µA/MHz active power consumption Optional Arm Cortex-M0+ core with 15‑µA/MHz power consumption System Memory – 160KB to 1MB SRAM Storage – 512KB to 2MB flash Security HW Cryptography – Symmetric: AES, 3DES; Asymmetric: RSA, ECC; Hashing: SHA-256, SHA-512;True Random …

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