Posts Tagged ‘xilinx’

Linaro Connect SF 2017 Welcome Keynote – New Members, Achievements, the Future of Open Source, and More…

September 26th, 2017 No comments

Linaro Connect San Francisco 2017 is now taking place until September 29, and it all started yesterday with the Welcome Keynote by George Grey, Linaro CEO discussing the various achievements since the last Linaro Connect in Budapest, and providing an insight to the future work to be done by the organization.

The video is available on YouTube (embedded below), and since I watched it, I’ll provide a summary of what was discussed:

  • Welcoming New Members – Kylin (China developed FreeBSD operating systems) joined LEG (Enterprise Group), NXP added LHG (Home Group) membership, and Xilinx joined LITE (IoT and Embedded).
  • Achievements
    • OPTEE open portable trusted environment execution more commonly integrated into products. Details at
    • LEG 17.08 ERP release based on Linux 4.12, Debian 8.9 with UEFI, ACPI, DPDK, Bigtop, Hadoop, etc…
    • LITE group has been involved in Zephyr 1.9 release, notably contributing to LwM2M stack
    • More projects to be found on download page.
  • Open source future with many fields involved including artificial intelligence, security, automotive, automation, etc.
    • Security requires software/hardware combination, and with a single global standard such as OPTEE desirable
    • Artificial Intelligence / Machine Learning
      • Trend is to move out of the CPU to off-load tasks to GPU, FPGA, or NNA (Neural Network Accelerators)
      • Not single API, for example TensorFlow supports CPU and NVIVIA CUDA, using other platforms require heavy customization
      • Linaro to work abstraction layer/ common API for machine learning
      • A.I will bring many benefits, but also potential dangers/issues: privacy, military use, etc… Development in the open is better.
    • Automotive
      • Currently Intel and NVIDIA provides ADAS / autonomous driving platform, both closed sources
      • More open platform needed, maybe a 96Boards Automotive platform with 6x cameras, GPS, touch screen display, processing power good enough for ADAS and IVI (In Vehicle-Entertainment)
      • Linux now mostly handles non-safety critical code, will change in the future. Containers will help.
      • Currently working on proof-of-concept with StreetDrone One autonomous driving development platform, DragonBoard 410c and Gumstix AeroCore 2 mezzanine. More details, maybe demo, at next Linaro Connect
  • 96Boards
    • Recently (and soon to be) announced – Hikey 960, Orange Pi i96, Uranus (WiFi board based on TI CC3220, to run Zephyr OS)
    • Mezzanine boards – NeonKey with sensors and LEDs, Secure96 with crypto chips & TPM (used to play with OPTEE)
  • ARM Platforms for developers – Three types:
  • Microplatforms
    • Definition – open source, minimal, secure, OTA upgradeable distributions
    • Cortex M platforms will use Zephyr OS, Cortex A support will be based on OpenEmbedded with a unified multi-SoC kernel
    • Currently tested on Hikey, DragonBoard 410c, and Raspberry Pi 3, more platforms to be supported in the future
    • Demos with 6x Carbon + Nitrogen board with BLE running Zephyr OS, Raspberry Pi 3 IoT gateway:
      • 1. Use Linaro Developer Cloud (running LED Enterprise Reference Platform) + Hawkbit dash to monitor temperature sensors on the board
      • 2. Switch Raspberry Pi 3 gateway to use Softbank cloud using Alibaba infrastructure on-the-fly, and control lights from Japan severs.
      • The two demos above shows how a multi-standard automation gateway could be implemented solving the problem of incompatibility of devices from different manufacturers
      • BLE mesh demo with six board controlling lights
      • Source code for demos can be found on Github
    • Going forwards downstream microplatforms will be developed by a separate entity: Open Source Foundries, unrelated to Linaro which will keep on focusing on upstream work
  • Linaro also launched the Associate Program for OEMs, ODMs, service providers, startups, and university who want to join Linaro. No details were provided, only an email address [email protected]

You’ll also find the presentation slides on Slideshare.

Amazon EC2 F1 Instances Put Xilinx Virtex Ultrascale+ FPGA Boards into the Cloud

February 22nd, 2017 4 comments

We’ve covered several board and modules based on Xilinx Zynq Ultrascale+ MPSoC such as the AXIOM Board and Trenz TE0808 SoM, both featuring ZU9EG MPSoC, with systems selling for several thousands dollars. But I’ve been informed you may not need to purchase a board to use Virtex UltraScale+ FPGAs, which are different from Zynq UltraScale+ since they lack the ARM CPU & GPU and normally feature a more capable FPGA, as last November, Amazon launched a developer preview of F1 instances giving access to this type of hardware from their cloud.

That’s the FPGA hardware you’ll be able to access from one F1 instance:

  • Xilinx UltraScale+ VU9P manufactured using a 16 nm process.
  • 64 GB of ECC-protected memory on a 288-bit wide bus (four DDR4 channels).
  • Dedicated PCIe x16 interface to the CPU.
  • Approximately 2.5 million logic elements.
  • Approximately 6,800 Digital Signal Processing (DSP) engines.
  • Virtual JTAG interface for debugging.

I understand those FPGA boards are PCIe card plugged into servers with an Intel Broadwell E5 2686 v4 processor, up to 976 GB of memory, and up to 4 TB of NVMe SSD storage. This is obviously only usable if the FPGA do not need extra hardware connected to the board.

You can choose from two instance types as described in the table below.

Instance Type FPGA Cards vCPUs Instance Memory (GiB) SSD Storage (GB) Enhanced Networking EBS Optimized
f1.2xlarge 1 8 122 480 Yes Yes
f1.16xlarge 8 64 976 4 x 960 Yes Yes

Amazon provides an hardware development kit or FPGA Developer AMI (Amazon Instance), where developers write and debug FPGA code on their own hardware/instance, before creating an “Amazon FPGA image” (AFI), and attaching it to an F1 instance as describe in the first diagram of this post. If you’re a customer who needs a specific “acceleration routine”, you don’t even need the FPGA development kit, as you can purchase the AFI on the market place, and deploy it on F1 instances.

If you are interested in Amazon solution and want to know more and get started, Amazon organized a one hour webinar last December.

Hardware-accelerated computing leveraging FPGAs is especially used for genomics research, financial analytics, real time video processing, big data search and analytics, and security applications.

AFAIK, Amazon has still not officially launched F1 instances commercially, at which point you’ll be able to pay by the hour for the use of the instance, but you can still sign up for the F1 preview.

Thanks to Jon for the tip.

EU funded AXIOM Board is Powered by Xilinx Zynq UltraScale+ FPGA + ARM SoC

February 17th, 2017 9 comments

Back in 2015, Xilinx unveiled Zynq Ultrascale+ MPSoC combining ARM Cortex A53 & Cortex R5 cores, a Mali-400MP2 GPU, and UltraScale FPGA, and the company recently launched ZCU102 Evaluation Kit based on the SoC, which sells for just under $3,000. But if you are based in the European Union, you’ll be glad to learn about 4 millions Euros of your taxes have been spent to design a board based on the same MPSoC family as part of the AXIOM project, which was developed in collaboration with European universities and companies with the “aim of researching new software/hardware architectures for Cyber-Physical Systems (CPS) to meet the expectations” in terms of computational power, energy efficiency, scalability through modularity, easy programmability, and leverage of the best existing standards at minimal costs.

AXIOM (Agile, eXtensible, fast I/O Module) board’s key specifications:

  • SoC – Xilinx Zynq Ultrascale+ ZU9EG MPSoC with four ARM Cortex A53 cores @ 1.2GHz, two Cortex R5 “real-time” cores @ 500MHz, a Mali-400MP GPU @ 600 MHz, 600K System Logic Cells;
  • System Memory – 32 GB of swappable SO-DIMM RAM  (up to 32GB) for the Processing System, plus a soldered 1 GB Programmable Logic.
  • Storage – 8 GB eMMC flash (PCN layout supports up to 32GB), and a micro SD card reader.
  • Display – miniDP connector, single channel 24-bit LVDS interface, touch panel connector
  • Connectivity – Gigabit Ethernet port (RJ45)
  • USB – 4x USB Type C ports, 2x USB Type A ports
  • Expansion
    • Arduino UNO headers
    • 12x GTH transceivers @ 12.5 Gbps  (8 on USB Type C connectors + 4 on HS connector)

There’s also mention of an Axiom Link interface that would allow to interconnect multiple AXIOM boards in order to arrange small clusters.

Since it’s a public project I would have expected it to be open source. While there are some deliverables available for download, they appear to be outdated with “the technical specification of AXIOM board” PDF mentioning only AXIOM-15 and AXIOM-35 boards based on the previous Xilinx Zynq-7000 series SoCs. We can also find links to a Wiki, as well as git and svn repository, but all those are in a private area that requires a login, and as far as I could tell, it’s not possible to register. So maybe the EU commission wants to protect its investment, or we just need to be a little more patient. [Update: This Download page  seems to have more public info available]

Click to Enlarge

The AXIOM Board is said to combine features required for High-Performance Computing, Embedded Computing and Cyber-Physical Systems, with typical applications including real-time data analysis of a huge amount of data, machine learning, neural networks, server farms, bitcoin miners, and so on.

It’s unclear when/if the board will be available for sale, and at what price.

Via Board DB and Single Board Computers G+ community.

NovaVGA Shield Adds VGA Output to Arduino Boards

January 30th, 2017 2 comments

Arduino boards are convenient to control I/Os, link LEDs, and display info on small LCD displays, but if you want to output data to a larger monitor, it’s a bit more complex. NovaVGA shield for Arduino simplify the task of outputting data to a VGA monitor over SPI.

NovaVGA shield hardware specifications:

  • CPLD – Xilinx XC9572XL CPLD, user programmable via JTAG interface.
  • SRAM Framebuffer – 160×120 pixels @ 6-bit color (2^6 = 64 possible colors)
  • VGA Output – 640×480 @ 60Hz physical resolution (25.175MHz pixel clock)
  • Interface with MCU – SPI mode 1 interface (consumes only three Arduino pins)
  • Header pins not included

MicroNova provides an Arduino library with various examples such as color palette, Mandelbrot, Tetris and text console, as well as a user’s guide and PDF schematics that can all be downloaded directly on the product page.

NovaVGA shield sells for $29 on Tindie or directly on MicroNova store. Note that it’s not the first board of this kind, as Olimex MOD-VGA, based on GameDuino design, has been available for several years.

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

July 12th, 2016 5 comments

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself.

Freedom U500 Block Diagram

Freedom U500 Block Diagram

But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller.

Freedom U500 (Unleashed family) platform key specifications:

  • U5 Coreplex with 1 to 8 U54 cores @ 1.6GHz+
  • RV64GC Architecture (64- bit RISC-V)
  • Multicore, Cache Coherency Support
  • High Speed Peripherals: PCIe 3.0, USB3.0, GbE, DDR3/4
  • TSMC 28nm

The SoC supports Linux, and targets applications such as machine learning, storage, and networking.

Freedom E300 Block Diagram

Freedom E300 Block Diagram

Freedom E300 (Everywhere family) platform key specifications:

  • E3 Coreplex
  • RV32IMC/RV32EMC Architecture
  • On chip Flash, OTP, SRAM
  • TSMC 180nm

Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.

Open source SoCs are made to be customizable to match your applications exact needs, instead of picking on existing SoC matching your requirements but with some uneeded features. SiFive also explains that “storage customers talks about custom instructions for bit manipulation so they can use one not 10 instructions for 10x speed up”. But before you get to Silicon, you’d normally ruin and customize the core on FPGA boards and three boards are currently available for development and evaluation:

  • Freedom U500:
  • Freedom E300 – Digilent Arty FPGA development kit powered by Xilinx XC7A35T-L1CSG324I FPGA, with 256 MB RAM, 16 MB flash, and vairous expension ports. Price: $99
Click to Enlarge

Xilinx Virtex-7 FPGA VC707 devkit – Click to Enlarge

You also have detailed documentation about the SoCs, U5 nd U3 coreplex, the development kits, software and tools, as well as developer forums, on SiFive developers website. You can also directly checkout the code and SDK on github.

RISC-V instructions set is royalty-free, so compared to the entry level $40,000 ARM license for startups using Cortex M0 MCU, it should provide some savings. It does not help with manufacturing costs which should remain the same. but SiFive expects that open source SoC could be manufactured through a “moderate” crowdfunding campaign.  I have not been able to figure out SiFive business model yet, unless they plan on selling their own chips too, and/or provide customization services to customers.

Lots more information can be found on Sifive website.

Via EETimes

OpenAMP Open Source Framework Provides the Glue between Linux, RTOS, and Bare Metal Apps in Heterogeneous SoCs

January 27th, 2016 No comments

SoCs becoming more complex, and go beyond homogeneous multicore systems by mixing different type of cores such as high performance cores, low power real-time cores, or even FPGA fabric. Examples include NXP i.MX6 SoloX with an ARM Cortex A9 core for Linux apps, and an ARM Cortex M4 core for real-time tasks, or Xilinx Zynq UltraScale+ MPSoC with Cortex A53 core for higher level apps, Cortex R5 cores for real-time processing, and Ultrascale FPGA logic. All these different cores are running their own Linux based OS, real-time operating system or bare metal application, and all this makes software development an even greater difficult tasks. In order to reduce the complexity, and address some of the issues, the Multicore Association has launched a new working group targeting the management, expansion, and standardization of  OpenAMP (Open Asymmetric Multi Processing), an open source framework that allows operating systems to interact within a broad range of complex homogeneous and heterogeneous architectures and allows asymmetric multiprocessing applications to leverage parallelism offered by the multicore configuration”.

OpenAMP_ArchitectureKey features and benefits of OpenAMP listed by the association:

  • Configure, deploy, and manage multiple OS’s across homogeneous and heterogeneous cores
  • Availability of open source Linux implementations and proprietary RTOS and bare metal implementations
  • Android OS compatibility
  • Inter-OS & inter-processor communication
  • Shared memory protocol – Virtio/rpmsg
  • Lifecycle APIs – remoteproc
  • Proxy technologies emulate Linux processes
  • Compatibility with MCAPI to support high-performance use cases and zero-copy
  • Standardizes OS interaction between Linux and RTOS/bare-metal

Some RTOS support has already been implemented by FreeRTOS, Mentor, Micrium, NXP, Xilinx, and an open source implementation, as well as corresponding documentation, can be found on OpenAMP github repository.You can find out more on OpenAMP page, the mailing list, and the first 2-hour developer meeting that will take place later today (January 27, 2016) at 9:00 pm Pacific Standard Time, and go through OpenAMP governance, the working group goals, current OpenAMP capabilities, and issues, as well as time for an open discussion on architectural proposals.

Digilent ARTY is a $99 Xilinx Artix-7 FPGA Board with Arduino Headers

October 2nd, 2015 2 comments

Low cost FPGA boards with Arduino headers are nothing new, as we’ve seen before with Arduissimo and Papilio DUO, but both of these boards are based on Spartan 6 FPGA, while the recent Digilent ARTY board is powered by an Artix-7 FPGA. Beside the hardware differences, Spartan 6 FPGAs only support Xilinx ISE Design Suite, while Artix-7 parts are also supported by Vivado Design Suite, which according to Xilinx has a much better workflow and user interface.

Digilent_ARTYDigilent ARTY specifications:

  • FPGA – Xilinx XC7A35T-L1CSG324I with 33,280 logic cells, 1,800 Kb block RAM, 90 DSP slices, and 250 I/O pins
  • System memory – 256 MB DDR3L SDRAM
  • Storage – 16 MB of QSPI Flash
  • Connectivity – 10/100M Ethernet
  • Expansion interfaces
    • 4 Digilent compatible Pmod interfaces enabling 32 user I/O pins: 2 Pmods routed as differential pairs, paired to fit dual-wide Pmods
    • Arduino UNO R3 shield / chipKit interface
  • Debugging – USB-UART Interface, JTAG Programming/Configuration Port
  • Misc – 4x user RGB LEDs, 4x user LEDs, 4x user slide switches, 4x user push button switches
  • Power Supply – 7-15V input via DC jack or headers, 5V via micro USB port
  • Dimensions – N/A
ARTY Block Diagram

ARTY Block Diagram

Vivado Design Suite comes with various editions, starting from the free WebPACK Edition with limited features to the System Edition with the complete integration and verification feature set selling for close to $5,000. According to the product brief, ARTY evaluation kit includes the Design Edition, locked to XC7A35T device, and valued at $2,995.

However, ARTY development board / evaluation kit sells for just $99 on Digilent or Avnet. Technical documentation and design resources can be found on Arty Resource Center.

Xilinx Introduces Zynq UltraScale+ MPSoC with Cortex A53 & R5 Cores, Ultrascale FPGA

March 5th, 2015 2 comments

Xilinx Zynq-7000 dual core Cortex A9 + FPGA SoC family was announced in 2012, and provides a wide range of SoC with features and price range, and led to low cost ARM + FPGA such as ZedBoard, and more recently Parallela and MYiR Z-Turn boards. The company unveiled its successor with Zynq UltraScale+ MPSoC providing five times more performance per watt, with four ARM Cortex A53 cores, two ARM Cortex R5 real-time MCU cores, a Mali-400MP GPU, an UltraScale FPGA fabric manufactured with 16nm FinFET+ process.

Zynq_Ultrascale+_MPSoCThere are two main sub-families in Zynq Ultrascale+ MPSoC for “smarter control & vision”, and “smarter network”. Both share the same processing systems (CPU, GPU, MCU, Peripherals, Security), but the networking family has beefier FPGAs,  and lacks the H.264/H.265 video processing unit found in the control & vision version:

  • Processing Systems
    • Processor – Quad ARM Cortex A53 MPCore up to 1.3GHz
    • Real-time Processor – Dual ARM Cortex-R5 MPCore up to 600MHz
    • GPU – Mali-400MP2 up to 466MHz
    • External Memory I/F – DDR4, LPDDR4, DDR3, DDR3L, LPDDR3, 2x Quad-SPI, NAND
    • High-Speed Connectivity – 2x USB3.0, SATA 3.0, DisplayPort, 4x Tri-mode Gigabit Ethernet, PCIe Gen2x4
    • General Connectivity – 2xUSB 2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
    • Security – AES, RSA, and SHA
    • AMS System Monitor – 10-bit, 1 MSPS– Temperature, Voltage, and Current Monitor
  • Programmable Logic
    • FPGA
      • Control & Vision (C&V) – Up to 485K Effective LEs, 405K Logic Cells, 1,728 DSP Slices, 6.2 Mb distributed RAM,  11.2 Mb BlockRAM, 27 Mb UltraRAM
      • Networking (N) – Up to 1,095K Effective LEs, 920K Logic Cells, 3,528 DSP Slices, 11 Mb distributed RAM,  34.6 Mb BlockRAM, 36 Mb UltraRAM
    • PCI Express Interface – Gen4 x8;  Gen3 x16
    • 1x Video Codec Unit (C&V only) – H.264/H.265 up to 4Kx2Kp60 or 8Kx4Kp15
    • Serial Transceiver – C&V: 28 up to 16 Gb/s; N: 76 up to 33 Gb/s
    • Analog Mixed Signal (AMS) – System Monitor—10-bit, 1 MSPS ADCs with 17 Differential Inputs, Power supply line voltage monitoring & JTAG, PMBUS, I2C support

The processing systems and programmable logic are interfaced via 128-bit AMBA AXI4 interfaces.


Zynq UltraScale+ MPSoC Block Diagram (Click to Enlarge)

There are 5 parts for Control and Vision (XCZU2, XCZU3, XCZU4, XCZU5, and XCZU7), and 6 parts (XCZU6, XCZU9, XCZU11, XCZU15, XCZU1 and XCZU19) for Network, and even more if you include different packaging options. SKU details and nomenclature can be found in the product selection guide.

The Cortex A53 cores will run Linux, Cortex R5 cores FreeRTOS, and design tools include Vivado Design Suite, Xilinx SDK, and PetaLinux SDK. Zynq UltraScale+ MPSoCs can be used for connected control/machine-to-machine applications for manufacturing, 2D/3D vision application (video-processing, object detection…), wired and wireless networking, and data centers.

I could not find any availability information from Xilinx, but LinuxGizmos reports that “early access to the UltraScale+ processors starts in the second quarter, with samples coming later this year, and volume production due in 2016”.

Visit Xilinx Zynq UltraScale+ MPSoC page for more information.