Author: Jean-Luc Aufranc (CNXSoft)

We first found out about Tremont microarchitecture in April 2018 in some Intel documents and Linux mainline source showing it was likely meant to be Goldmont Plus successor. Last year, Intel formally announced Tremont architecture providing some of the details with a block diagram and key features. But this morning, we were informed by email of a new revision of the x86/x64 Software Optimization Manual (PDF) with even further details about Tremont architecture. If you want to know all the details, jump to 4.1 Tremont Architecture section of the document, but here are some of the highlights / improvements over Golmond Plus microarchitecture: Enhanced branch prediction unit. Increased capacity with improved path-based conditional and indirect prediction. New committed Return Stack Buffer. Clustered 6-wide out-of-order front-end fetch and decode pipeline. Banked ICache with dual 16B reads. Two 3-wide decode clusters enabling up to 6 instructions per cycle. Deeper back-end out-of-order windows. Dedicated integer and vector integer/floating-point store data ports. 33% increase …

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