Linux 5.8 Release – Main Changes, Arm, MIPS, and RISC-V Architectures

Linus Torvalds has just released Linux 5.8: So I considered making an rc8 all the way to the last minute, but decided it’s not just worth waiting another week when there aren’t  any big looming worries around. Because despite the merge window having been very large, there really hasn’t been anything scary going on in the release candidates. Yeah, we had some annoying noise with header file dependencies this week, but that’s not a new annoyance, and it’s also not the kind of subtle bug that keeps me up at night worrying about it. It did reinforce how nice it would be if we had some kind of tooling support to break nasty header file dependencies automatically, but if wishes were horses.. Maybe some day we’ll have some kind of SAT-solver for symbol dependencies that can handle all our different architectures and configurations, but right now it’s just a manual pain that occasionally bites us. Anyway.. Aside from silly header …

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Ingenic X2000 IoT Application Processor Combines 32-bit MIPS Xburst 2 Cores with Xburst 0 Real-time Core

In Arm’s world, heterogeneous processors are pretty common, with for example big.LITTLE / dynamIQ application processors mixing powerful Cortex-A7x cores with power-efficient Cortex-A5x cores., or  “industrial” processor such NXP i.MX 8M family with Cortex-A53 application cores combined with Cortex-M4F real-time core. Maybe I did not follow enough, but I hadn’t really seen anything equivalent in MIPS world, except if we count Ingenic T31 with RISC-V and MIPS cores. That is until today where I was informed about documents related to Ingenic X2000 IoT application processor with two 32-bit MIPS Xburst 2 core, one MIPS Xburst 0 real-time cores, as well as up to 256MB RAM built-into the SoC. Ingenic X2000 specifications: CPU Core – Dual XBurst 2, MIPS ISA based, frequency up to 1.5 GHz with 32KB L1 x2 Cache, 512KB L2 Cache, 32KB SRAM, FPU,128bit SIMD MCU Core – XBurst 0 MIPS core @ 300MHz for security and real-time control System Memory -128/256MB LPDDR2/3 in package Storage I/F SPI …

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Linux 5.7 Released – Main Changes, Arm, MIPS and RISC-V Architectures

OK… I’m a bit late on that one. Linus Torvalds released Linux 5.7 last week: So we had a fairly calm last week, with nothing really screaming “let’s delay one more rc”. Knock wood – let’s hope we don’t have anything silly lurking this time, like the last-minute wifi regression we had in 5.6.. But embarrassing regressions last time notwithstanding, it all looks fine. And most of the discussion I’ve seen the last week or two has been about upcoming features, so the merge window is now open  and I’ll start processing pull requests tomorrow as usual. But in the meantime, please give this a whirl. We’ve got a lot of changes in 5.7 as usual (all the stats look normal – but “normal” for us obviously pretty big and means “almost 14 thousand non-merge commits all over, from close to two thousand developers”), So the appended shortlog is only the small stuff that came in this last week since …

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QEMU 5.0 Supports Recent Armv8.x Features, Cortex-M7 CPU, Host Directory Access, and More

QEMU (Quick EMUlator) is an open-source emulator that’s great to run programs on various architectures such as Arm, RISC-V, and many others when you don’t own proper hardware. The developers have now released QEMU 5.0.0 will plenty of new features and such as support for Armv8.1 to Armv8.4 architectures, Arm Cortex-M7 processor, various changes to MIPS, PowerPC, RISC-V, s390… architectures, support for accessing a directory on the host filesystem from the guest using virtiofsd and more. There have been over 2800+ commits from 232 developers, so the list of changes to too long to write here, but some of the highlights include: Support for passing host filesystem directory to guest via virtiofsd Support for ARMv8.1 VHE/VMID16/PAN/PMU, ARMv8.2 UAO/DCPoP/ATS1E1/TTCNP, ARMv8.3 RCPC/CCIDX,  ARMv8.4 PMU/RCPC Added ARM Cortex-M7 CPU support New Arm boards: tacoma-bmc, Netduino Plus 2, and Orange Pi PC Allwinner SoC model now wires up the USB ports TPM support for ARM You’ll find the full list of change in the …

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Ingenic T31 AI Video Processor Combines MIPS & RISC-V Cores

Last week we asked “is MIPS dead?” question following the news that Wave Computing had filed for bankruptcy, two MIPS Linux maintainers had left, and China-based CIP United now obtained the exclusive MIPS license rights for mainland China, Hong Kong, and Macau. Ingenic is one of those Chinese companies that have offered MIPS-based processors for several years, but one commenter noted that Ingenic joined the RISC-V foundation, and as a result, we could speculate the company might soon launch RISC-V processors, potentially replacing their MIPS offerings. But Ingenic T31 video processor just features both with a traditional Xburst  MIPS Core combines with a RISC-V “Lite” core Ingenic T31 specifications: Processors XBurst 1 32-bit MIPS core clocked at 1.5GHz with Vector Deep Learning accelerator based on SIMD128, 64KB + 128KB L1/L2 Cache RISC-V independent lite core System Memory – Built-in 512Mbit (64MB) or 1Gbit (128MB) DDR2 Storage – Quad SPI flash, NAND flash, SD card I/F Display I/F – Supports Smart …

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Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More…

When in 2018, Blu posted a guest post entitled “Baikal T1 MIPS Processor – The Last of the Mohicans?” I thought maybe it was too pessimistic with regard to the future of MIPS architecture. At the time, MIPS belonged to Imagination Technologies, but soon the company had its own financial problems and had to sell MIPS assets to Wave Computing. The latter eventually announced the launch of MIPS Open Initiative early last year,  so there was some hope as interest might pick up to compete against RISC-V and Arm again. But in recent months, MIPS related news has not been so good. First, Wave Computing decided to end MIPS Open Initiative in November 2019, then Paul Burton and Ralf Baechle removed themselves from the Linux kernel MIPS maintainer list in February 2020, as their work with MIPS ended leaving Thomas Bogendoerfer as the only maintainer. But this month, things turned for the worse, with CIP United filing a lawsuit against …

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Linux 5.6 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linus Torvalds has just announced the release of Linux 5.6 on the Linux Kernel Mailing List: So I’ll admit to vacillating between doing this 5.6 release and doing another -rc. This has a bit more changes than I’d like, but they are mostly from davem’s networking fixes pulls, and David feels comfy with them. And I looked over the diff, and none of it looks scary. It’s just slightly more than I’d have preferred at this stage – not doesn’t really seem worth delaying a release over. So about half the diff from the final week is network driver fixlets, and some minor core networking fixes. Another 20% is tooling – mostly bpf and netfilter selftests (but also some perf work). The rest is “misc” – mostly random drivers (gpio, rdma, input) and DTS files. With a smattering of fixes elsewhere (a couple of afs fixes, some vm fixes, etc). The shortlog is appended, nothing really looks all that exciting, …

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Linux 5.5 Release – Main Changes, Arm, MIPS and RISC-V Architectures

Linux 5.5 has just been released by Linus Torvalds: So this last week was pretty quiet, and while we had a late network update with some (mainly iwl wireless) network driver and netfilter module loading fixes, David didn’t think that warranted another -rc. And outside of that, it’s really been very quiet indeed – there’s a panfrost driver update too, but again it didn’t really seem to make sense to delay the final release by another week. Outside of those, it’s all really tiny, even if some of those tiny changes touched some core files. So despite the slight worry that the holidays might have affected the schedule, 5.5 ended up with the regular rc cadence and is out now. That means that the merge window for 5.6 will open tomorrow, and I already have a couple of pull requests pending. The timing for this next merge window isn’t optimal for me – I have some travel and other things …

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