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Geniatech APC888 NXP i.MX 95-powered Edge AI Box PC takes M.2 AI accelerator from Hailo, MemryX, NXP, or DeepX

Geniatech APC888

Geniatech APC888 Edge AI Box PC is powered by an NXP i.MX 95 Cortex-A55/M7/M33 applications processor, and features an M.2 socket for AI accelerator from Hailo, MemryX, DeepX, or Kinara (now NXP). The system comes with 4GB LPDDR5 and 32GB eMMC flash by default, features two Gigabit Ethernet ports, optional WiFi, Bluetooth, cellular, and GNSS connectivity, and two USB 3.0 ports. It’s available in commercial and industrial temperature grades. Geniatech APC888 specifications: SoC – NXP i.MX 95 CPU Up to 6x Arm Cortex-A55 application cores clocked at 1.8 GHz with 32KB I-cache and D-cache, 64KB L2 cache, and 512KB L3 cache 1x Arm Cortex-M7 real-time core clocked at 800 MHz 1x Arm Cortex-M33 safety core clocked at 333 MHz GPU – Arm Mali-G310 V2 GPU for 2D/3D acceleration with support for OpenGL ES 3.2, OpenCL 3.0 VPU 1080p60/4Kp30 H.265 and H.264 encode and decode JPEG Encoder, JPEG Decoder Decoding – […]

Forlinx UP4 – A 40×40 mm LCC + LGA system-on-module family with Rockchip, NXP, and Allwinner CPU options

Forlinx UP4 system-on-module

Forlinx Embedded UP4 is a new family of pin-to-pin compatible system-on-modules currently offered with Rockchip RK3568J/RK3562J, NXP i.MX 9352, or Allwinner T527N/T536 processors. The UP4 modules measure just 40×40 mm and expose 487 pins through a hybrid LCC (Leadless Chip Carrier) and LGA (Land Grid Array) design with 1.0mm contact pitch and 1.27mm ball pitch, respectively. This should allow companies to design a single carrier board for multiple CPU variants. Forlinx UP4 specifications: SoC FET-MX9352-UP4 – NXP i.MX 9352 with 2x Arm Cortex-A55 cores @ up to 1.7 GHz, Cortex-M33 real-time core @ 250 MHz, 2D GPU only, 0.5 TOPS Arm Ethos U65 microNPU FET3568-UP4 – Rockchip RK3568B2/J with 4x Arm Cortex-A55 cores @ up to 2.0/1.8 GHz, Arm Mali-G52 MP2 3D GPU, 1 TOPS AI NPU FET3562J-UP4 – Rockchip RK3562J with 4x Arm Cortex-A53 cores @ 1.8 GHz,  Arm Mali-G52-2EE 3D GPU, 1 TOPS NPU FET527N-UP4 – Allwinner T527N […]

LimeSDR Micro M.2 2280 SDR card pairs NXP LA9310 baseband processor with LMS7002M RF transceiver (Crowdfunding)

LimeSDR Micro

The LimeSDR Micro M.2 2280 software-defined radio (SDR) card combines an NXP LA9310 baseband processor and a Lime Microsystems LMS7002M transceiver, and targets integration into portable or embedded solutions with a spare M.2 PCIe Gen3 x1 socket. The module is offered in a 1T2R configuration by default, but can be expanded to 1T4R via an FPC connector, supports a 30 MHz to 3.8 GHz frequency range, and up to 100 MHz bandwidth. Target applications include 4G LTE/5G, future RAN research, custom user equipment/modems, drone communications, IoT, satellite communications, and custom waveform generation. LimeSDR Micro M.2 SDR card specifications: SoC – NXP LA9310 programmable baseband processor Vector Signal Processing Accelerator (VSPA) Gen 2 up to 80 GFLOPs Control Processor – Arm Cortex-M4 at up to 307 MHz Storage – 512 Kbit EEPROM memory for NXP LA9310 initial configuration RF Lime Microsystems LMS7002M RF transceiver Channels – 1T2R expandable to 1T4R via […]

NXP i.MX 937 cost-effective Cortex-A55/M7/M33 MPU is a drop-in replacement for NXP i.MX 95 SoC family

NXP i.MX 937

The 1 .4 GHz NXP i.MX 937 quad-core Cortex-A55 microprocessor (MPU) for HMI and Edge AI applications aims to fill the gap between entry-level NXP i.MX 93 SoCs and higher-end parts like the NXP i.MX 952 processor family, while offering pin-to-pin compatibility with the latter. The i.MX 937 MPU also features a dedicated 667 MHz Arm Cortex -M7 for real-time workloads and a low-power Arm Cortex-M33 core for system management tasks, supports LPDDR4x or LPDDR5 memory, integrates an Arm Mali G310 3D GPU, a VPU for 1080p H.26x video encoding and decoding, and a 2 eTOPS NXP eIQ Neutron NPU for machine learning (ML) acceleration. Since it targets HMI applications, we’ll also find MIPI DSI and LVDS display interfaces, and a 4-lane MIPI CSI camera interface, plus various other I/Os. NXP i.MX 937 specifications: (highlights in bold compared to other i.MX 93 parts) CPU Up to 4x Arm Cortex-A55 cores […]

NXP i.MX 93W wireless MPU SiP pairs dual-core Arm Cortex-A55 processor with NXP iW610 WiFi 6, Bluetooth LE, and 805.15.4 radio

NXP i.MX 93W

NXP i.MX 93W is the company’s first integrated wireless MPU System-in-Package (SiP) and combines a dual-core Cortex-A55 processor (NXP i.MX 93) with an iW610 WiFi 6, Bluetooth LE, and 802.15.4 tri-radio into a single chip. The 14.2 x 12 mm package also includes all the external radio components needed for wireless connectivity, replacing up to 60 discrete components on the PCB. NXP says it reduces the PCB area, simplifies PCB design and regulatory approval, and speeds up time-to-market. NXP i.MX 93W specifications: CPU Dual-Core Arm Cortex-A55 at up to 1.7 GHz Arm Cortex-M33 core at 250 MHz for real-time control GPU – 2D graphics accelerator AI accelerator – Arm Ethos-U65 microNPU Memory I/F – Up to 3.7GT/s 16-bit LPDDR4/LPDDR4X with inline ECC Storage I/F – 2x SD 3.0/SDIO 3.0/eMMC 5.1 Display Interfaces MIPI DSI up to 1080p60 LVDS up to 720p60 24-bit parallel RGB Camera Interface – 2-lane MIPI CSI up […]

NXP TJA1410 and TJF1410 PMD transceivers enable “CAN-like” Single Pair Ethernet (SPE) connectivity

NXP TJA1410 and TJF1410 PMD transceivers

We’ve reported on 10BASE-T1S and 10BASE-T1L Single Pair Ethernet (SPE) chips from Microchip and Analog Devices in the past, which support Ethernet communication over a single twisted-pair cable. But those chips integrate a full Ethernet PHY or MAC-PHY inside the device. NXP takes a different approach with their TJA1410 (automotive) and TJF1410 (industrial) Physical Medium Dependent (PMD) transceivers. These new PMDs separate the analog physical layer from the digital Ethernet logic. By integrating the digital portion of the PHY into the host microcontroller or switch, the TJA1410 and TJF1410 only need to handle the essential analog functions for transmitting and receiving signals over the physical medium. They communicate with the host via a 3-pin OPEN Alliance (OA) interface. TJA1410 and TJF1410 PMD transceivers specifications: Networking – 10BASE-T1S (Compliant with IEEE 802.3cg and OPEN Alliance TC14,TC10 specifications) Host Interface – 3-pin OA interface (requires host MCU/switch with a 10BASE-T1S digital PHY) […]

NXP S32N79 octa-core Arm Cortex-A78E/12-core Cortex-R52 “Super-Integration Processor” targets Software-Defined Vehicles (SDV)

NXP S32N79 block diagram

NXP recently introduced the S32N79 “Super-Integration” automotive processor, part of the S32N7 series, equipped with up to eight Arm Cortex-A78E application cores and twelve Arm Cortex-R52 cores for real-time processing. Building on the earlier 5 nm S32N55 16-core Cortex-R52 + 2x Lockstep Cortex-M7 automotive processor, the S32N79 automotive processor is still designed for software-defined vehicles (SDV), but its Cortex-A78E applications cores further enable features such as ADAS sensor fusion and data AI services, as well as improved vehicle gateway/processing functions. NXP S32N79 key features and specifications: CPU Up to 8x split-lock Arm Cortex-A78AE cores operating at up to 1.8 GHz Up to 12x split-lock Arm Cortex-R52 cores operating at up to 1.4 GHz RISC-V-based accelerator for networking, math, and data-intensive workloads AI accelerator – eIQ Neutron neural processing unit (NPU) for vehicle core NeuroNetwork offload Memory Up to 2x LPDDR4X/5/5X DRAM interfaces Up to 36 MB platform SRAM Storage 2x […]

NXP i.MX 952 processor supports local dimming for AI-enhanced automotive and industrial HMIs

NXP i.MX 952 automotive industrial AI processor

NXP has recently introduced the i.MX 952 applications processor, a new member of the i.MX 95 series, designed for AI-powered automotive and industrial applications, including driver monitoring, child presence detection, and in-cabin HMIs. The i.MX 952 features up to four Arm Cortex-A55 cores with Cortex-M7 and M33 microcontroller cores, and is compliant with ISO 26262 ASIL B and SIL2/SIL3 standards. It integrates an eIQ Neutron NPU for AI-based sensor fusion, a 500 Mpixel/s ISP with RGB-IR support, and is the first processor with built-in local dimming for better display efficiency. Security features include EdgeLock Secure Enclave with post-quantum cryptography, meeting ISO 21434 and IEC 62443 standards. It can be interfaced with NXP’s PF09 PMIC, PF53 regulator, Trimension UWB, and IW693/AW693 Wi-Fi 6/6E SoCs, and is pin-to-pin compatible with other members of the i.MX 95 family. NXP i.MX 952 specifications: CPU Up to 4 Arm Cortex-A55 cores with 32KB + 32KB L1-cache, 64KB L2 […]