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Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on SiFive introduces RVA23-compliant Performance P570 Gen3 RISC-V core for consumer and AIoT applications

SiFive introduces RVA23-compliant Performance P570 Gen3 RISC-V core for consumer and AIoT applications

SiFive Performance P570 Gen3 Core Complex

SiFive has just launched the SiFive Performance P570 Gen 3 out-of-order RISC-V processor core, compliant with the RVA23 ISA profile, and designed for edge AI, high-end consumer, and commercial IoT applications running Android or enterprise-grade OS. Besides the CPU core, SiFive also provides system IP, such as the RISC-V standard-compliant advanced interrupt architecture (AIA), WorldGuard security, and a second-generation RISC-V standard-compliant IOMMU to build a complete SoC with up to 16x P570 Gen 3 cores. Performance P570 Gen3 specifications: Support for all mandatory RVA23 profile extensions for compatibility with modern operating systems such as Ubuntu 26.04 LTS and Red Hat Enterprise Adds extensions for enhanced security and performance, including Smepmp, Zvkng, Zvksg, Zicfilp, Zicfiss, Zfbfmin, Zvfbfmin, Zvfbfwma, and Zvdot4a8i Third-generation out-of-order core building on earlier P550 Gen1 and P470 Gen2 cores 3-wide, 13-stage fully out–of order execution superscalar pipeline Single 128-bit vector pipeline with dot product extensions Supports multicore coherence […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 6 Comments on Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 7.0

Linus Torvalds has just released Linux 7.0 on LKML: The last week of the release continued the same “lots of small fixes” trend, but it all really does seem pretty benign, so I’ve tagged the final 7.0 and pushed it out. I suspect it’s a lot of AI tool use that will keep finding corner cases for us for a while, so this may be the “new normal” at least for a while. Only time will tell. Anyway, this last week was a little bit of everything: networking (core and drivers), arch fixes, tooling and selftests, and various random fixes all over the place. Let’s keep testing, and obviously tomorrow the merge window for 7.1 opens. I already have four dozen pull requests pending – thank you to all the early people. Linus This follows the Linux 6.19 release about two months ago, which brought us PCIe link encryption and […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.19

Linus Torvalds has just released Linux 6.19 on the Linux Kernel Mailing List (LKML): No big surprises anywhere last week, so 6.19 is out as expected – just as the US prepares to come to a complete standstill later today watching the latest batch of televised commercials. The betting man would expect them all to be AI-generated, but maybe some enterprising company decides to buck the trend? Doubtful, but there’s always a slight chance. But for anybody outside the US, maybe taking the newest kernel out for a spin instead is an option? I have more than three dozen pull requests for when the merge window opens tomorrow – thank you to all the early maintainers. And as people have mostly figured out, I’m getting to the point where I’m being confused by large numbers (almost running out of fingers and toes again), so the next kernel is going to […]

Posted on by Debashis Das - 3 Comments on Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat introduces UP201 and UP301 ultra-low power RISC-V MCUs with always-on AI processing

Upbeat UP201 and UP301 Series AI MCUs No BG

Upbeat Technology, in collaboration with SiFive, has introduced UP201 and UP301 always-on AI MCUs for ultra-low-power AI and IoT applications such as wearables, drones, and sensor-based systems. The UP201 is designed for compact, battery-driven devices such as smartwatches, hearing aids, and IoT sensor nodes, whereas the UP301 targets AI and vision-based applications for more complex edge systems such as smart glasses, robotics, and industrial AI equipment. Both chips feature a dual-core RISC-V architecture. The SiFive E21 lightweight core is Always-On (AON), managing continuous low-power sensing, whereas the SiFive E34 performance core activates for higher workloads. The MCUs also integrate a 2.5D GPU and various I/O options. UP201 and UP301 MCU specifications: CPU cores (SiFive Essential RISC-V IP cores) E21 core in Always-On (AON) domain for continuous low-power sensing E34 performance core in the Non-AON domain for higher workloads Up to 400 MHz operating frequency Up to 717 DMIPS performance Near-threshold […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive introduces 2nd Gen Intelligence RISC-V AI CPUs: X160, X180, X280 Gen 2, X390 Gen 2, and XM Gen 2

SiFive Intelligence X180 Gen 2 Core Complex

SiFive has just launched its 2nd Generation Intelligence family, featuring five new RISC-V-based products: the new X160 Gen 2 and X180 Gen 2, and upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2 processors, all featuring scalar, vector, and matrix processing (XM only) capabilities designed for AI workloads. The original Intelligence X280 64-bit RISC-V CPU was introduced in 2021, following the Intelligence X390 NPU in 2023, and the Intelligence XM Series in September 2024. The X160 Gen 2  (32-bit) and X180 Gen 2 (64-bit) are entry-level AIoT CU cores targeting edge compute and IoT applications for automotive, autonomous robotics, industrial automation, and smart IoT applications. The upgrade models get support for the RVA23 profile and a few other changes. SiFive X160/X180 Gen 2 CPUs Key features and specifications: Scalar processing Intelligence X160 Gen 2 – 32-bit RISC-V ISA (RV32I) Intelligence X180 Gen 2 – 64-bit RISC-V ISA (RV64I) Dual […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 release arm linux mips

Linus Torvalds has just announced the release of Linux 6.16 on LKML: It’s Sunday afternoon, and the release cycle has come to an end. Last week was nice and calm, and there were no big show-stopper surprises to keep us from the regular schedule, so I’ve tagged and pushed out 6.16 as planned. It’s worth noting that the upcoming merge window for 6.17 is going to be slightly chaotic for me: I have multiple family events this August (a wedding and a big birthday), and with said family being spread not only across the US, but in Finland too, I’m spending about half the month traveling. That means that I will try very hard to get most of the merge window done the first week before my travels start, and I already ended upgiving a heads-up on that to the people who tend to send me the most pull requests. […]

Posted on by Sayantan Nandy - No Comments on Microchip PIC64HX1000 64-bit RISC-V AI MPU delivers post-quantum security for aerospace, defense, and automotive applications

Microchip PIC64HX1000 64-bit RISC-V AI MPU delivers post-quantum security for aerospace, defense, and automotive applications

Microchip PIC64HX1000 64 bit AI MPU

Microchip recently unveiled the PIC64HX1000 64-bit RISC-V AI microprocessor (MPU) family designed for mission-critical intelligent edge applications in the aerospace, defense, industrial, and medical sectors thanks to a quantum-resistant design. These new MPUs feature eight SiFive’s Intelligence X280 cores, each clocked at 1 GHz. The MPUs are engineered with a decoupled vector pipeline enabling 512-bit operations enabling the PIC64HX1000 to achieve up to 2 TOPS for AI/ML processing and come equipped with integrated Time-Sensitive Networking (TSN) Ethernet connectivity. This new microprocessor includes a dedicated system controller for runtime monitoring and fault management, WorldGuard architecture for workload isolation, and post-quantum defense-grade cryptography, which includes the NIST-standardized FIPS 203 and FIPS 204 cryptographic algorithms, ensuring protection against future quantum computing threats. PIC64HX1000 64-bit AI MPU specification MPU variants PIC64HX1000 – IN (Industrial) PIC64HX1000 – AV (Aviation) PIC64HX1000 – MI (Military) CPU – 8x 64-bit RISC-V cores (SiFive X280), up to 1 GHz, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

SiFive HiFive Premier P550 RISC-V mini-DTX motherboard

SiFive HiFive Premier P550 is a mini-DTX (203 x 170mm) motherboard powered by a 1.4 GHz ESWIN EIC7700X quad-core RISC-V SiFive P550 SoC with up to 19.95 TOPS of AI performance, and equipped with up to 32GB LPDDR5 memory and a 128GB eMMC flash all soldered on a system-on-module. The motherboard itself features a SATA III connector for data storage, includes an HDMI 2.0 port for 4K video output, a PCIe Gen3 x16 slot (working at x4), two gigabit Ethernet ports, an M.2 Key-E socket to add a WiFi/Bluetooth card, up to five USB interfaces, and more. HiFive Premier P550 specifications: SoC – ESWIN EIC7700X CPU 4x SiFive Performance P550 RV64GC RISC-V cores @ 1.4GHz (up to 1.8GHz when overclocked) with Cortex-A75-class performance 32KB(I) + 32KB(D) L1 Cache 256KB L2 Cache 4MB shared L3 Cache Cache supports ECC (support SECDED) NPU (Not currently supported in software) – Up to 19.95 […]