SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions

SiFive Performance RISC-V processors Roadmap

SiFive has announced two new RISC-V Performance cores with the P670 and P470 processors with RISC-V Vector Extension for AI/ML, media and sensor processing, and designed for high volume applications such as wearables, smart home, industrial automation, AR/VR, and other consumer devices. The P670 is comparable to the Cortex-A78, and the P470 is comparable to the Cortex-A55. Both support the standardized RISC-V RVA22 profile for better OS compatibility and implement RISC-V Vector v1.0 and Vector Cryptography extensions. The SiFive Performance P470 and P670 share the following features: Full RISC-V RVA22 profile compliance Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification RISC-V Vector Cryptography extensions SiFive WorldGuard system security Support for virtualization, including a separate IOMMU for accelerating virtualized device IO Advanced Interrupt Architecture (AIA) compliant interrupt controller with better support for Message Signal Interrupts (MSI) and virtualization Enhanced scalability with fully coherent multi-core, multi-cluster, with […]

Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5

When SiFive introduced its Performance P550 64-bit RISC-V processor in 2021, we were told that Intel would use it in the Horse Creek platform with “leading-edge interface IP such as DDR and PCIe” and manufactured with Intel’s 7nm process. We now have more details about the Horse Creek platform, as a development board was showcased for the first time in public at the Intel Innovation 2022 Developer Conference, and according to a report by Wikichip, the Cortex-A75 class quad-core RISC-V processor runs at up to 2.2 GHz, supports DDR5-5600 memory and eight PCIe 5.0 lanes, and was taped out with Intel 4 process. Horse Creek platform specifications: CPU – SiFive P500 quad-core RISC-V processor @ up to 2.2 GHz with a 13-stage, 3-issue, out-of-order (OoO) pipeline, private L2 cache, and common L3 cache Memory – DDR5-5600 interface PCIe – PCIe Gen5 through Intel’s PCIe PHY with 8 lanes, Synopsys PCIe […]

SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

RISC-V is coming to your car too, with the introduction of SiFive Automotive E6-A, X280-A, and S7-A RISC-V processors designed for automotive applications such as infotainment, cockpit, connectivity, ADAS, and electrification. Those are built on the existing SiFive Essential 6-series E6 32-bit real-time cores, SiFive Intelligence X280 64-bit RISC-V processor with AI extensions, and SiFive S7 64-bit real-time cores (equivalent to Cortex-R7/R8), but adds safety, security, and performance required by the automotive market such as ASIL compliance. Each new core targets specific applications within a vehicle: The SiFive E6-A series will be found in system control boards, hardware security modules (HSMs) and safety islands, as well as standalone in microcontrollers. The SiFive S7-A 64-bit  real-time core is said to be suited to the needs of SoCs with performant safety islands, requiring both low latency interrupt support and the same 64-bit memory space as the main application CPUs. The SiFive X280-A […]

Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 is out! Linus Torvalds has just announced the release on lkml: No unexpected nasty surprises this last week, so here we go with the 5.18 release right on schedule. That obviously means that the merge window for 5.19 will open tomorrow, and I already have a few pull requests pending. Thank you everybody. I’d still like people to run boring old plain 5.18 just to check, before we start with the excitement of all the new features for the merge window. The full shortlog for the last week is below, and nothing really odd stands out. The diffstat looks a bit funny – unusually we have parsic architecture patches being a big part of it due to some last-minute cache flushing fixes, but that is probably more indicative of everything else being pretty small. So outside of the parisc fixes, there’s random driver updates (mellanox mlx5 stands out, […]

Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel has just announced a $1 billion fund to support companies bringing innovations and new technologies to the foundry ecosystem. The company says the fund will prioritize investments in “capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures, and advanced packaging technologies.” What’s interesting is that it does not only cover x86 architecture but also Arm and RISC-V, with a focus on the latter, as Intel has just become a Premier member of RISC-V International, and partnered with several companies offering RISC-V solutions including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. Intel’s Open Chiplet Platform Part of the investment will go to the Open Chiplet Platform offering a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. This will allow designers to select the best IP and process technologies for a particular SoC. […]

Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linus Torvalds has just announced the release of Linux 5.16: Not a lot here since -rc8, which is not unexpected. We had that extra week due to the holidays, and it’s not like we had lots of last-minute things that needed to be sorted out. So this mainly contains some driver fixes (mainly networking and rdma), a cgroup credential use fix, a few core networking fixes, a couple of last-minute reverts, and some other random noise. The appended shortlog is so small that you might as well scroll through it. This obviously means that the merge window for 5.17 opens tomorrow, and I’m happy to say I already have several pending early pull requests. I wish I had even more, because this merge window is going to be somewhat painful due to unfortunate travel for family reasons. So I’ll be doing most of it on the road on a laptop […]

Sifive Essential 6-Series RISC-V processors target Linux, real-time applications

SiFive has been busy. Just a few days after SiFive Performance P650 announcement, the company has announced the SiFive Essential 6-Series RISC-V processor family starting with four 64-bit/32-bit real-time core, and two Linux capable application cores, plus the SiFive 21G3 release with various improvements to existing families. SiFive Essential 6-Series range of RISC-V processors There Essential 6-Seris family is comprised of three sub-families with two processors each: E6 Series with 1.91 DMIPS/MHz, 3.69 CoreMark/MHz E61-MC – Quad-core 32-bit embedded processor E61 – Mid-range performance 32-bit embedded processor (one-core) S6 Series with 2.07 DMIPS/MHz, 3.73 CoreMark/MHz S61-MC – Quad-core 64-bit embedded processor S61 – Mid-range performance 64-bit embedded processor (one-core) U6 Series with 2.07 DMIPS/MHz, 3.73 CoreMark/MHz U64-MC – Quad-core 64-bit application processor U64 – Mid-range performance Linux-capable processor (one-core) E6-Series and S6 Series real-time processors have practically the same features except for the 32-bit and 64-bit cores, and a different […]

SiFive Performance P650 RISC-V core to outperform Arm Cortex-A77 performance per mm2

About six months have passed since the SiFive announcement of the Performance P550 “fastest 64-bit RISC-V processor” ever, and the company has now introduced an even faster RISC-V core with the Performance P650 that’s expected to match Cortex-A77 performance. Building upon the Performance P550 design, the SiFive Performance P650 is scalable to sixteen cores using a coherent multicore complex, and delivers a 40% performance increase per clock cycle based on SiFive engineering estimated performance in SPECInt2006/GHz, thanks to an expansion of the processor’s instruction-issue width. The company compares P650 to the Arm family by saying it “maintains a significant performance-per-area advantage compared to the Arm Cortex-A77”. SiFive Performance P650 key features: 64-bit RISC-V (RV64GCB) core Sv39/Sv48 Virtual Memory Support Multi-core, multi-cluster processor configurations with up to 16 cores Performance > 11 SpecINT2006/GHz Thirteen stage, four-issue, out-of-order pipeline tuned for scalable performance Private L2 Caches and Streaming Prefetcher for improved memory […]