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Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on SiFive unveils P870 high-performance core, discusses future of RISC-V

SiFive unveils P870 high-performance core, discusses future of RISC-V

SiFive Hot Chips 2023 x86 vs Arm vs RISC-V

SiFive has just given a presentation at Hot Chips 2023 introducing the new high-performance P870 RISC-V core and its automotive equivalent the P870-A core, plus discussing RISC-V in general, its previous generation RISC-V cores, and what to expect going forward. SiFive has not officially announced the P870 and P870-A cores just yet, so most of the information we have from the English-speaking Internet is from ServeTheHome who managed to get some presentation slides, but this is also corroborated by various Chinese sources on Baidu and Guokr. SiFive P870 and P870-A The P870 and P870-A RISC-V cores are new cores from the SiFive Performance family compatible with the RISC-V RVA23 profile and succeeding the SiFive P670 core. The SpecINT2k6 benchmark reports 17 points per GHz on the P870 compared to 13.2 points per GHz for the P670 (comparable to the Arm Cortex-A78) or about a 29% higher performance at the same […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 10 Comments on HiFive Pro P550 “Horse Creek” RISC-V motherboard with 16GB RAM to launch this summer

HiFive Pro P550 “Horse Creek” RISC-V motherboard with 16GB RAM to launch this summer

HiFive Pro P550 Horse Creek SBC

SiFive HiFive Pro P550 RISC-V motherboard based on Intel “Horse Creek” quad-core SiFive Performance P550 processor will launch this summer with 16GB DDR5 memory, two PCIe expansion slots, Gigabit Ethernet networking, USB 3.x ports, and on-board graphics. Intel Horse Creek platform was first revealed when SiFive unveiled the SiFive Performance P550 64-bit RISC-core with Cortex-A75 class performance in June 2021. The companies then demonstrated an internal Intel Horse Creek board with 8GB DDR5 and PCIe Gen5 at the Intel Innovation 2022 Developer Conference last October, and it looks like the 7nm RISC-V processor, manufactured with an Intel 4 process, will finally be available to developers this summer with the launch of the HiFive Pro P550 motherboard/development system.   HiFive Pro P550 preliminary specifications: SoC – Intel-SiFive Horse Creek SoC equipped with 4x SiFive Performance P550 RV64GBC RISC-V cores with a 13-stage, 3-issue, out-of-order (OoO) pipeline GPU – “On-board graphics” [Update: […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions

SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions

SiFive Performance RISC-V processors Roadmap

SiFive has announced two new RISC-V Performance cores with the P670 and P470 processors with RISC-V Vector Extension for AI/ML, media and sensor processing, and designed for high volume applications such as wearables, smart home, industrial automation, AR/VR, and other consumer devices. The P670 is comparable to the Cortex-A78, and the P470 is comparable to the Cortex-A55. Both support the standardized RISC-V RVA22 profile for better OS compatibility and implement RISC-V Vector v1.0 and Vector Cryptography extensions. The SiFive Performance P470 and P670 share the following features: Full RISC-V RVA22 profile compliance Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification RISC-V Vector Cryptography extensions SiFive WorldGuard system security Support for virtualization, including a separate IOMMU for accelerating virtualized device IO Advanced Interrupt Architecture (AIA) compliant interrupt controller with better support for Message Signal Interrupts (MSI) and virtualization Enhanced scalability with fully coherent multi-core, multi-cluster, with […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 12 Comments on Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5

Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5

Horse Creek Features

When SiFive introduced its Performance P550 64-bit RISC-V processor in 2021, we were told that Intel would use it in the Horse Creek platform with “leading-edge interface IP such as DDR and PCIe” and manufactured with Intel’s 7nm process. We now have more details about the Horse Creek platform, as a development board was showcased for the first time in public at the Intel Innovation 2022 Developer Conference, and according to a report by Wikichip, the Cortex-A75 class quad-core RISC-V processor runs at up to 2.2 GHz, supports DDR5-5600 memory and eight PCIe 5.0 lanes, and was taped out with Intel 4 process. Horse Creek platform specifications: CPU – SiFive P500 quad-core RISC-V processor @ up to 2.2 GHz with a 13-stage, 3-issue, out-of-order (OoO) pipeline, private L2 cache, and common L3 cache Memory – DDR5-5600 interface PCIe – PCIe Gen5 through Intel’s PCIe PHY with 8 lanes, Synopsys PCIe […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

SiFive Automotive RISC V processor

RISC-V is coming to your car too, with the introduction of SiFive Automotive E6-A, X280-A, and S7-A RISC-V processors designed for automotive applications such as infotainment, cockpit, connectivity, ADAS, and electrification. Those are built on the existing SiFive Essential 6-series E6 32-bit real-time cores, SiFive Intelligence X280 64-bit RISC-V processor with AI extensions, and SiFive S7 64-bit real-time cores (equivalent to Cortex-R7/R8), but adds safety, security, and performance required by the automotive market such as ASIL compliance. Each new core targets specific applications within a vehicle: The SiFive E6-A series will be found in system control boards, hardware security modules (HSMs) and safety islands, as well as standalone in microcontrollers. The SiFive S7-A 64-bit  real-time core is said to be suited to the needs of SoCs with performant safety islands, requiring both low latency interrupt support and the same 64-bit memory space as the main application CPUs. The SiFive X280-A […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 release arm risc-v mips

Linux 5.18 is out! Linus Torvalds has just announced the release on lkml: No unexpected nasty surprises this last week, so here we go with the 5.18 release right on schedule. That obviously means that the merge window for 5.19 will open tomorrow, and I already have a few pull requests pending. Thank you everybody. I’d still like people to run boring old plain 5.18 just to check, before we start with the excitement of all the new features for the merge window. The full shortlog for the last week is below, and nothing really odd stands out. The diffstat looks a bit funny – unusually we have parsic architecture patches being a big part of it due to some last-minute cache flushing fixes, but that is probably more indicative of everything else being pretty small. So outside of the parisc fixes, there’s random driver updates (mellanox mlx5 stands out, […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 16 Comments on Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel RISC-V

Intel has just announced a $1 billion fund to support companies bringing innovations and new technologies to the foundry ecosystem. The company says the fund will prioritize investments in “capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures, and advanced packaging technologies.” What’s interesting is that it does not only cover x86 architecture but also Arm and RISC-V, with a focus on the latter, as Intel has just become a Premier member of RISC-V International, and partnered with several companies offering RISC-V solutions including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. Intel’s Open Chiplet Platform Part of the investment will go to the Open Chiplet Platform offering a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. This will allow designers to select the best IP and process technologies for a particular SoC. […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linux 5.16 release

Linus Torvalds has just announced the release of Linux 5.16: Not a lot here since -rc8, which is not unexpected. We had that extra week due to the holidays, and it’s not like we had lots of last-minute things that needed to be sorted out. So this mainly contains some driver fixes (mainly networking and rdma), a cgroup credential use fix, a few core networking fixes, a couple of last-minute reverts, and some other random noise. The appended shortlog is so small that you might as well scroll through it. This obviously means that the merge window for 5.17 opens tomorrow, and I’m happy to say I already have several pending early pull requests. I wish I had even more, because this merge window is going to be somewhat painful due to unfortunate travel for family reasons. So I’ll be doing most of it on the road on a laptop […]

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