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February 20, 2026February 20, 2026 by Jean-Luc Aufranc (CNXSoft) - No Comments

MediaTek Genio 360/360P hexa/octa-core Cortex-A76/A55 AIoT SoC features 8 TOPS NPU for cost-sensitive embedded applications

MediaTek Genio 360 and Genio 360P are respectively hexa-core and octa-core Arm Cortex-A76/A55 AIoT processors featuring a MediaTek NPU delivering up to 8 TOPS of AI performance, and designed for cost-sensitive embedded applications. The chips support up to 8GB of memory and eMMC 5.1, SPI NOR, and SD 3.0 storage interfaces. They feature two 4-lane MIPI DSI and one 4-lane DP/eDP interfaces for single or dual display setups, two 4-lane MIPI CSI camera interfaces, audio inputs/outputs, Gigabit Ethernet with TSN, optional WiFi 5 and Bluetooth 5.3 via MT6631N, USB 3.1 and USB 2.0 interfaces, PCIe Gen2 x1, and low-speed interfaces. MediaTek Genio 360/360P specifications: CPU MediaTek Genio 360 (MT8366) – Hexa-core processor 1x Arm Cortex-A76 core clocked at up to 1.9 GHz (industrial) / 2.0GHz (commercial) 5x Arm Cortex-A55 cores clocked at up to 1.7 GHz (industrial) / 2.0GHz (commercial) MediaTek Genio 360P (MT8367) – Octa-core processor 2x Arm Cortex-A76 […]

February 18, 2026February 21, 2026 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

NXP S32N79 octa-core Arm Cortex-A78E/12-core Cortex-R52 “Super-Integration Processor” targets Software-Defined Vehicles (SDV)

NXP recently introduced the S32N79 “Super-Integration” automotive processor, part of the S32N7 series, equipped with up to eight Arm Cortex-A78E application cores and twelve Arm Cortex-R52 cores for real-time processing. Building on the earlier 5 nm S32N55 16-core Cortex-R52 + 2x Lockstep Cortex-M7 automotive processor, the S32N79 automotive processor is still designed for software-defined vehicles (SDV), but its Cortex-A78E applications cores further enable features such as ADAS sensor fusion and data AI services, as well as improved vehicle gateway/processing functions. NXP S32N79 key features and specifications: CPU Up to 8x split-lock Arm Cortex-A78AE cores operating at up to 1.8 GHz Up to 12x split-lock Arm Cortex-R52 cores operating at up to 1.4 GHz RISC-V-based accelerator for networking, math, and data-intensive workloads AI accelerator – eIQ Neutron neural processing unit (NPU) for vehicle core NeuroNetwork offload Memory Up to 2x LPDDR4X/5/5X DRAM interfaces Up to 36 MB platform SRAM Storage 2x […]

February 10, 2026February 11, 2026 by Jean-Luc Aufranc (CNXSoft) - 7 Comments

TOPST D3-G maker SBC is powered by Telechips TCT8050 “Dolphin3” Cortex-A72/A53/R5 automotive-grade SoC

TOPST D3-G is a single board computer (SBC) powered by a Telechips TCT8050 “Dolphin3/3M” 9-core automotive-grade SoC with four Cortex-A72 cores, four Cortex-A53 cores, and one real-time Cortex-R5 core. The board features 4GB or 8GB LPDDR4 RAM, 32GB eMMC flash and a microSD card for storage, a Gigabit Ethernet port, a DisplayPort 1.2 connector capable of driving four display through MST, two MIPI CSI connectors, a PCIe Gen3x 1 slot, a few USB ports, a 40-pin GPIO header compatible with Raspberry Pi HAT+, and three CAN Bus interfaces. TOPST D3-G specifications: SoC – Telechips TCC8050 (Dolphin3) CPU(45,180 DMIPS) Quad-core Arm Cortex-A72 @ 1.69 GHz, 31,840 DMIPS Quad-core Arm Cortex-A53 @1.45 GHz, 13,340 DMIPS Real-time MCU core – Arm Cortex-R5 @ 600 MHz GPU – Imagination Technologies PowerVR 9XTP (GT9524) delivering up to 168 GFLOPS; Supported APIs: OpenGL ES 1.1 / 2.0 / 3.2, Vulkan 1.2, OpenCL 2.0 / 3.0 System […]

February 10, 2026 by Jean-Luc Aufranc (CNXSoft) - No Comments

Black Sesame Technologies Wudang C1200 “cross-domain” automotive SoCs feature up to 10x Cortex-A78AE cores

I found two interesting automotive SoCs in the Linux 6.19 changelog: Renesas R-Car X5H 16-/32-core Cortex-A720AE SoC and Black Sesame Technologies’ “Wudang” C1200 8-/10-core Cortex-A78AE processor family. While announced in 2024, there’s still no product page for the Renesas chip. So today, I’ll focus on the Wudang C1200 family. They are designed to be automotive-grade “cross-domain computing platforms” capable of handling multiple functions such as in-cabin sensing systems (e.g., driver attention monitoring), infotainment, auto-parking systems, safety information, autonomous driving, and more. Wudang C1296 10-core SoC Wudang C1296 specifications: CPU 10x Arm Cortex-A78AE automotive-grade cores Dual-Core Lockstep (DCLS) supported, ASIL-D compliance Up to 32K DMIPS (or 16K DMIPS in DCLS) GPU – Automotive-grade Arm Mali-G78AE GPU; DCLS supported, ASIL-D compliance NPU – DynamAl NN Engine Hybrid precision 4-bit/8-bit MAC array Overall 80% utilization of convolution layers MAC Array Sparse support for storage and acceleration INT8/INT16, FP16 GEMM and nonlinear functions acceleration […]

January 6, 2026January 7, 2026 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Broadcom updates its Wi-Fi 8 access point chips portfolio with BCM4918 APU, BCM6714 and BCM6719 dual-band radios

Broadcom Wi-Fi 8 chips BCM4918 BCM6719 BCM6714

Broadcom has just announced the launch of its next-generation chips for Wi-Fi 8 access points at CES 2026 with the BCM4918 Accelerated Processing Unit (APU), and two new dual-band Wi-Fi 8 radios: BCM6714 and BCM6719. The last two build upon the Broadcom BCM6718 WiFi 8 tri-band SoC with different antenna configurations, namely 4×4 2.4GHz and 4×4 5 GHz for the BCM6719, and 3×3 2.4GHz and 4×4 5 GHz for the BCM6714, and integrated 2.4 GHz PAs. The AP4918 builds upon the AP4916, but I was unable to obtain information about the improvements from a company representing Broadcom. Broadcom BCM4918 Wi-Fi 8 APU BCM4918 key features: High-performance Quad-core Armv8 CPU complex for general-purpose software workloads Integrated Broadcom Neural Engine (BNE) for on-device AI/ML inference and acceleration Advanced networking engines to offload both wired and wireless data paths, enabling complete CPU bypass of all networking traffic Integrated cryptographic protocol acceleration end-to-end data […]

January 4, 2026January 5, 2026 by Jean-Luc Aufranc (CNXSoft) - 9 Comments

Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder

Allwinner V861 is a new dual-core 32-bit/64-bit RISC-V C907 system-in-package (SiP) with 128MB on-chip DDR3L and designed for 4K AI camera applications with a 1 TOPS AI NPU. The chip also features a 32-bit RISC-V E907 low-power core, a 4Kp25 H.264/H.265 video encoder, a 1080p60 JPEG video decoder and encoder, MIPI CSI and parallel camera interfaces, audio codec with input and output interfaces, Fast Ethernet, USB 2.0, and a range of digital and analog I/Os. Allwinner V861M3-XXX specifications: CPU Dual-Core RISC-V XuanTie C907 (RV64GCBV/RV32GGCBV) clocked up to 1.4GHz with RVV 1.0 extensions Single-core RISC-V XuanTie E907 (RV32IMAFC) clocked up to 800MHz VPU Video Encoder H.264/H.265 up to 4K @ 25fps (M)JPEG up to 8192×8192 Video Decoder – (M)JPEG up to 1080p60 AI accelerator – 1 TOPS (INT8) NPU dubbed “AI-ISP 2.0” Memory 128MB DDR3/DDR3L (SiP) “SQPI” PSRAM interface Storage QSPI flash eMMC 4.41 SDIO 2.0/3.0 Display – SPI interface Camera […]

December 16, 2025December 18, 2025 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

VEGA AS2161 “DHRUV64” – A 1GHz dual-core 64-bit RISC-V microprocessor designed in India

The Government of India has been investing to spur up its semiconductor design and manufacturing industry at least since 2018/2019 with the SHAKTI and AJIT microprocessors. In 2022, they decided to focus on the RISC-V architecture with the VEGA processor family, starting with the THEJAS32 (VEGA ET1031) and THEJAS64 (VEGA AS1061) microprocessors, and the former was eventually found in the ARIES v3.0 Arduino UNO-inspired development board. Things continue to progress nicely, albeit slowly, and the government has now announced the launch of the DHRUV64 (VEGA AS2161) dual-core 64-bit RISC-V MPU clocked at 1 GHz and supporting Linux, which it describes as “a fully indigenous microprocessor developed by the Centre for Development of Advanced Computing (C-DAC) under the Microprocessor Development Programme (MDP)”. VEGA AS2161 (DHRUV64) specifications highlights: Architecture – RISC-V 64G (RV64IMAFD) Instruction Set 13-16 stage out-of-order pipeline implementation. Advanced branch predictor – BTB, BHT, RAS. Harvard architecture, separate Instruction and […]

December 11, 2025December 11, 2025 by Debashis Das - 7 Comments

Up to 16-core AMD EPYC Embedded 2005 Series Zen 5 processors support up 28 PCIe Gen5 lanes, offer 10-year availability

AMD EPYC Embedded 2005 Series Processors

After the release of the high-performance EPYC Embedded 9005, AMD has now introduced the EPYC Embedded 2005 Series, a mid-range processor family also based on the “Zen 5” architecture and designed for space-constrained networking, storage, and industrial edge applications. The new SoCs feature up to 16 cores (32 threads) with 64 MB L3 cache, support dual-channel DDR5-5600 memory with ECC, and offer 28 lanes of PCIe Gen5 connectivity. It also supports advanced RAS capabilities, BMC, PCIe Hot Plug, multi-SPI ROM, and AMD Infinity Guard security. The processors come in a compact 40 x 40mm BGA package, which, according to AMD, is up to 2.4x smaller than competing enterprise solutions (Intel Xeon 6500P-B). Yet, they are designed for 24/7 operation, with up to 10 years of availability with full open-source software support. These features make it suitable for networking switches/routers, cold storage systems, aerospace, robotics, and other high-reliability embedded infrastructure. EPYC […]