HiFive1 Rev B Board Gets FE310-G002 RISC-V Processor, WiFi & Bluetooth Module

HiFive1 Rev B

SiFive launched what may have been the very first RISC-V development board in 2016 thanks to their HiFive1 Arduino compatible board powered by Freedom E310 (FE310) open source RISC-V processor. The company has now launched an upgrade version of the processor and board. Meet FE310-G002 processor and HiFive1 Rev B development board. HiFive1 Rev B development board specifications with new features highlighted in bold or stricken-through: MCU – SiFive Freedom E310-G0002 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz) Storage – 32 Mbit SPI flash (was 128 Mbit in the first version) Connectivity – ESP32-SOLO-1 WiFi & Bluetooth module I/Os 19x Digital I/O Pins 19x external interrupt pins 1x external wakeup pin 9x PWM pins 1/3 SPI Controllers/HW CS Pins I/O Voltages –  3.3V or 5V supported; note: bidirectional level shifters removed so FE310-G002 can drive the I/O pins directly at 3.3V only. USB – 1x micro USB port for power, programming and debugging (via Segger J-Link) Power …

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RISC-V Compliance Tests Aim to Address RISC-V Fragmentation

RISC-V Fragmentation

In the x86 world, one operating system image can usually run on all hardware thanks to clearly defined instruction sets, hardware and software requirements. Arm provides most flexibility in terms of peripherals, while having a fixed set of intrusions for a given architecture (e.g. Armv8, Armv7…), and this lead to fragmentation, so that in the past you had to customize your software with board files and other tweaks, and provide one binary per board, leading to lots of fragmentation. With device trees, things improved a bit, but there are still few images that will run on multiple boards without modifications. RISC-V provides even more flexibility that Arm since you can mess up with the instructions set with designers able to add or remove instructions as they see fit for their application. One can easily imagine how this can lead to a complete mess with binary code only running on a subset of RISC-V platforms, and lots of compiler options to …

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FreeRTOS Kernel Now Supports RISC-V Architecture


FreeRTOS is one of the most popular operating systems found in embedded systems, and RISC-V open architecture is getting more and more traction, so it should come as no surprise that Amazon has now added RISC-V to their recently acquired FreeRTOS kernel. Jeff Barr, Chief Evangelist for AWS, explains both 32-bit and 64-bit RISC-V cores are supported, and several RISC-V boards are already supported out of the box: The kernel supports the RISC-V I profile (RV32I and RV64I) and can be extended to support any RISC-V microcontroller. It includes preconfigured examples for the OpenISA VEGAboard, QEMU emulator for SiFive’s HiFive board, and Antmicro’s Renode emulator for the Microchip M2GL025 Creative Board. There’s no a lot of information on Amazon announcement post, but FreeRTOS website has plenty of resources to help you get started with RISC-V. The page also lists some of the key features of the RISC-V port: Supports machine mode integer execution on 32-bit RISC-V cores only, but is …

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Linux 5.0 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linux 5.0 Changelog

Linus Torvalds has just released Linux 5.0: Ok, so the last week of the 5.0 release wasn’t entirely quiet, but it’s a lot smaller than rc8 was, and on the whole I’m happy that I delayed a week and did an rc8. It turns out that the actual patch that I talked about in the rc8 release wasn’t the worrisome bug I had thought: yes, we had an uninitialized variable, but the reason we hadn’t immediately noticed it due to a warning was that the way gcc works, the compiler had basically initialized it for us to the right value. So the same thing that caused not the lack of warning, also effectively meant that the fix was a no-op in practice. But hey, we had other bug fixes come in that actually did matter, and the uninitialized variable _could_ have been a problem with another compiler. Regardless – all is well that ends well. We have more than a …

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WCH CH572 is a RISC-V MCU with Bluetooth LE Connectivity

CH572 RISC-V Bluetooth LE MCU

Jiangsu Qinheng Co., Ltd, better known as WCH, is famous for their USB to TTL chip such as CH340, but the company also offers various wireless MCUs, including some Arm Cortex-M0 based Bluetooth / Zigbee parts such as CH579. But today, I was informed a new Bluetooth MCU showed up on WCH website: CH572 with a RISC-V MCU core @ 60 MHz. We have limited information about the MCU, but here’s what we need so far about CH572 specifications: Core – RISC-V MCU @ up to 60 MHz System Memory – 10K SRAM Storage – 96KB OTP (One-Time Programming) flash Connectivity – Bluetooth LE USB – 1x USB host, 1x USB device Other Peripherals and I/Os 11-ch 12-bit ADC 3x 26-bit timers 11x PWM 2x UART, 1x SPI 23x GPIOs RTC and Watchdog Supply Voltages – 3.3V/2.5V Package – QFN28 The main downside is that’s an OTP flash, so you’d develop software using an ICE (In-circuit emulator), and once you …

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ARIES M100PF PolarFire FPGA System-on-Module Targets Industrial Applications, RISC-V Development


MicroSemi unveiled PolarFire RISC-V FPGA SoC at the end of last year, bringing an alternative to Xilinx Zynq (Arm Cortex-A9 + FPGA) and UltraScale+ (Cortex A53 + FPGA) SoCs. The system-on-chip is expected to be mass produced later in 2019, so development is done on HiFive Unleashed RISC-V board and its FPGA expansion board. In the meantime, MicroSemi PolarFire FPGAs (without RISC-V hard core) are available now, and ARIES Embedded planning to showcase what they claim is the first PolarFire FPGA system-on-module at Embedded World 2019 with their M100PF SoM targeting industrial applications. ARIES Embedded M100PF key features and specifications: A choice of 3 PolarFire FPGAs MPF100T – 109KLE, 336 Math Blocks (18x18MACC) MPF200T – 192KLE, 588 Math Blocks (18x18MACC) MPF300T – 300KLE, 924 Math Blocks (18x18MACC) System Memory – 512 MiB / 1 GiB / 2 GiB DDR3 RAM Storage – 256 MiB configuration device, 4 GiB eMMC flash by default (Option up to 64GB) 2x Samtec QSH-090-01-F-D-A 180-pin …

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OpenISA VEGAboard Combines RISC-V and ARM Cortex-M Cores


OpenISA has launched an Arduino compatible RISC-V development called VEGAboard that features RV32M1 wireless microcontroller with a RISC-V RI5CY core, a RISC-V ZERO-RISCY core as well as Arm Cortex-M4F and Cortex-M0 cores, and a radio operating in the 2.36 GHz to 2.48 GHz range. An external NXP Kinetis K26 Arm Cortex-M4 MCU is added to the board for OpenSDA (Open-Standard Serial and Debug Adapter) debugging over a single USB cable. The board was offered for free, I’m just not sure when, but they are already out of stock. Hopefully, they’ll start selling the board soon enough. VEGAboard (RM32M1-VEGA) board key features and specifications: Ultra-low-power RV32M1 Wireless MCU supporting BLE, Generic FSK, and IEEE Std 802.15.4 (Thread) platforms IEEE Std. 802.15.4-2006 compliant transceiver supporting 250 kbps O-QPSK data in 5.0 MHz channels, and full spread-spectrum encoding and decoding Fully compliant Bluetooth v4.2 Low Energy (BLE) Reference design area with small-footprint, low-cost RF node: Single-ended input/output port Low count of external components …

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FOSDEM 2019 Open Source Developers Meeting Schedule


FOSDEM – which stands for Free and Open Source Software Developers’ European Meeting – is a free-to-participate event where developers meet on the first week-end of February to discuss open source software & hardware projects. FOSDEM 2019 will take place on February 2 & 3, and the schedule has already been published with 671 speakers scheduled to speak in 711 events themselves sorted in 62 tracks. Like every year, I’ll create a virtual schedule based on some of the sessions most relevant to this blog in tracks such as  open hardware, open media, RISC-V, and hardware enablement tracks. February 2 10:30 – 10:55 – VkRunner: a Vulkan shader test tool by Neil Roberts A presentation of VkRunner which is a tool to help test the compiler in your Vulkan driver using simple high-level scripts. Perhaps the largest part of developing a modern graphics driver revolves around getting the compiler to generate the correct code. In order to achieve this, extensive …

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