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ARM TechCon 2013 Schedule – ARM Servers, Internet of Things, Multicore, Hardware and Software Optimization and More

August 1st, 2013 No comments

ARM_Techcon_2013ARM Technology Conference (TechCon) 2013 will take place on October 29 – 31, 2013, in Santa Clara, and the detailed schedule for the event has just been made available. In the previous years, the conference was divided into  Chip Designs day (1 day), and the other 2 days were reserved for Software & System Design, but this year it does not appear to be the case. Whether you’ll be able to attend the event or not, it’s worth having a look at what will be discussed there in order to have a better understanding of what will be the key ARM developments in the near future in terms of hardware and software.

There will be around 90 sessions categorized into 15 tracks:

  • Accelerating Hardware Development – This track explores the resources, tools, and techniques that designers can employ to quickly bring hardware to market. Topics include multicore design, ARM IP, chip buses, analog integration, simulation, FPGA prototyping, design synthesis, debugging and certification.
  • Accelerating Software Development – Topics include open-source software, RTOSes, Android, Java, libraries, CMSIS, software development tools, development boards, hardware simulation, debug tools, optimization and analysis tools, test tools and certification.
  • Accelerating System Hardware Development – This track explores the tools and techniques for getting system hardware development rapidly launched and landed. Topics include single board computers (SBCs), development boards, RF modules, analog front ends, FPGAs, ESL tools, hardware simulation and novel techniques for rapidly assembling a functional design.
  • Applying New Technologies to New Opportunities – This track explores new chip design technologies and new applications and their impact on one another. Topics include 14nm and beyond, graphics and multimedia, servers and enterprise-class processing, gateways, high speed interfaces, ultra-low power, energy harvesting, machine vision, advanced networking, medical instrumentation, automotive systems and voice recognition.
  • Building a Foundation for Safety and Security – This track explores the chip-level and software foundations for system safety and security, including things such as as multi-core and redundant architectures, TrustZone system security technology, trusted execution environments, encryption, tamper detection and hardware/software security partitioning, as well as the hardware elements for safety-related systems such as healthcare and vision processing in advanced driver assist in automobiles.
  • Creating the Next Gen Mobile Platform – This track explores the kinds of features and system requirements mobile devices will need to provide, and the techniques and resources needed to bring those designs to market. Topics include multicore design, multimedia and graphics, GPU computing, haptics, networking, security, high speed and wireless interfaces, GUI design and development, operating systems and power management.
  • Empowering System Security – This track explores the requirements, tools, and techniques for providing security in system designs at both software and hardware levels. Topics include encryption, trusted execution environments (TEE), TrustZone system security architecture, biometrics, tamper detection, remote management, application whitelisting and blacklisting, software certificates, network attack vulnerabilities and key protection.
  • Enhancing the User Experience – This track explores the tools and techniques for enhancing a consumer’s experience of your device, from high-end through resource constrained. Topics include touchscreens, haptics, multimedia, gesture recognition, GPU computing, accelerometers, sensor fusion, voice recognition, voice synthesis and GUI design and development tools.
  • Kickstarting ARM Embedded Development – This track provides you with the information and insights needed to ease your path and begin development. Topics include ARM architectures, new device releases, development kits, development tools, software IP, libraries, 8- to 32-bit migration, code reuse, CMSIS and more.
  • Marrying Software and Hardware in Multicore Design – This track explores the interaction between hardware design and software structure as well as the techniques for ensuring an optimal working relationship between the two. Topics include big.LITTLE processing, graphics processing, redundant computing, distributed computing operating systems, software partitioning, multi-core debugging and software optimization.
  • Maximizing Chip Energy Efficiency – This track explores the processes, structures, and approaches that will help keep device power minimized without sacrificing performance. Topics include semiconductor processes, clocking and power management, big.LITTLE and other multicore architectures, sleep modes, smart peripherals, dynamic clocking, analog integration, RF integration and other design techniques for reducing device power requirements.
  • Next-Generation Networking – Rise of Software Defined Networking – This track explores advanced and high-performance networking architectures, approaches, and implementations, including such topics as software defined networking (SDN), network function virtualization (NFV), high speed interfaces, wireless, security and carrier-class platforms.
  • Optimizing System Software Blocks – This track explores options in system software and the tools and techniques for optimizing software performance and resource requirements. Topics include Android, Linux, OSes, RTOSes, GUI design, libraries, drivers, development tools, debugging tools, certification and software test tools.
  • Stacking Up for High Performance Design – This track explores multicore architecture and design, looking at criteria such as core selection and integration, clock and power management, and shared memory architectures as well as other approaches to increasing the processor resources available on chip in the light of their performance and power implications. Topics include such things as hardware accelerators, graphics processors, big.LITTLE processing, clocking and power management, high-speed interfaces and SoC design.
  • Taming the IoT Frontier – This track seeks to explore a wide range of techniques and technologies that will help system developers quickly stake their claim in the IoT frontier. Topics include RF modules, sensors, networking, gateways, WiFi, Bluetooth, Zigbee, battery-powered design, energy harvesting, analog interfaces, cloud services, and security.

I’ve used the schedule builder to select some of the tracks that I find interesting during this 3-day event:

Tuesday – 29th of October

This class discusses multicore from a more traditional embedded viewpoint.

According to Cisco, the Internet of Things (IoT) is expected to connect more than one trillion objects by 2020. Through extreme interconnectivity, devices and objects are morphing into connected experiences that will have a profound impact on everything from cities to healthcare to households. This live demonstration shows how anyone can build, connect, operate, and capitalize on the IoT opportunity. The combination of ARM mbed and the LogMeIn Xively platform accelerates time to market, as developers can rapidly progress from prototyping to volume deployment. Attendees will leave with an action plan for deploying their own IoT-enabled products.

Multicore ARM platforms are becoming the norm in embedded applications and smartphones. However, most developers do not understand the underlying hardware architecture and what that means to their software-development approach. This presentation leads attendees through the issues, such as process migration and caching control, that can increase application performance an order of magnitude or more. We discuss techniques to avoid multicore race conditions, common scheduling issues, and how to bind user threads and integrated services routers to specific processor cores in Linux and Android to guarantee the maximum performance and temporal correctness of applications and kernel code.

This session introduces both a development environment for people who are starting to use BeagleBone or BeagleBone-like ARM boards and the whole ecosystem behind OpenEmbedded. It goes through such tools and techniques as generating images, generating package feeds, customizing images, and adding your own software to images.  Developers can generate their own SDKs and use them outside of the Angstrom Linux distribution that’s shipped with BeagleBone so they can write applications. The loop is closed by showing how applications are knotted into Angstrom to become part of images. Angstrom also maintains feeds for BeagleBone, which means application developers can utilize it without rebuilding the platform software.

  • 15:30 – 16:20 – Server Solutions from ARM by Ian Forsyth, Senior Product Marketing Manager, High Performance Application Processors, ARM, and Aniket Saha  |  Product Manager, ARM

The server landscape is rapidly shifting, with workload profiles bifurcating into compute-intensive and scale-intensive. ARM designed its latest Cortex-A50 line of 64-bit processors for the needs of this evolving server workload in the enterprise data center. ARM servers can deliver high performance at a higher efficiency than similar technology based on x86-class processors. This paper details ARM-based server solutions and ecosystem developments.

Wednesday – 30th of October

SmartMesh IP is the latest generation of low-power wireless mesh solutions by the Dust Networks Product group at Linear Technology. It combines the ease of use of IPv6 and 6LoWPAN with the wired-like reliability of IEEE802.15.4e Time Synchronized Channel Hopping. It runs on the custom-built Eterna chip, which combines an ARM Cortex-M3 MCU, with an ultra low-power IEEE802.15.4 wireless radio. This gives a SmartMesh IP mote years of battery life. This session starts by discussing the challenges of building a reliable low-power wireless solution and how these were overcome in the development of SmartMesh IP. We then highlight how customers are integrating these networks, either by driving the mote with an external micro-controller over a serial port or by developing custom firmware directly on the SmartMesh IP device. Through a number of hands-on demonstrations, we present the ecosystem available to simplify integration.

GPU computing on the ARM Mali-T600 series of GPUs offers a host of benefits: it accelerates data-parallel computation while reducing system work load; reduces platform energy consumption while increasing system throughput; and enhances your system’s value by consolidating functionality while reducing programmer effort. In this talk, we show how ARM Mali-T600 processors deliver such benefits on shipping devices. By analyzing ecosystem partners’ use cases, we highlight trends in GPU computing: computational photography, computer vision, and image processing.

The Internet of Things (IoT) is a huge opportunity, as well as a huge design problem. Your key to success is to avoid trying to do everything yourself. We explore the barriers to growth and the practical steps to breaking them down, with insights from early companies in the field as well as ARM’s own engineers. Among the several key points: Today, online products are delivered vertically integrated: one vendor delivers devices, gateway, cloud services, analytics, and user-experience aspects. Increasingly, commercial necessity is forcing providers to think open and embrace a horizontal ecosystem. Different link layers such as ZigBee and WirelessHART are here for a while, but between them and the application is a layer of great commonality from application to application, ripe for standardization. The talk includes practical tips for designing devices and services for the IoT that take advantage of interoperability, lower cost, and better user experience, including easy pairing, pub-sub, and preparing for IPv6 in an IPv4 world.

As industry projections for entry-level smartphones soar, it is ever more important to achieve the required performance within ever tighter power, cost, and timescale constraints. This presentation describes how to build an extremely efficient processing subsystem, based on the very latest, lowest-power ARM Cortex-A class processors, Mali graphics and video processors, and CoreLink PD-System IP. Key factors explored are power management, cost/benefit of GPU coherency, optimal sharing of memory bandwidth, and minimizing area and IP costs.

Now that the RTX full-featured real-time operating system is under a BSD license, it really is free. RTX, part of the CMSIS-RTOS standard, has found applications in thousands of products. Created and maintained by Keil, it includes all source code. RTX is not crippled or limited in any way. Ports are provided for Keil MDK, GCC, and IAR.

This seminar looks at the overall features of RTX and shows how easy it is to implement in any project. Included are a live demonstration of the two kernel-awareness windows that are part of Keil MDK and CMSIS-RTOS and a discussion of implementation details.

Thursday – 31st of October

Understanding the compilation process is crucial to generating the tightest code from your source code. Compiler technology has not yet run it course, and new cutting-edge optimizations have made enormous savings in execution and code size. This talk surveys a few of my favorite optimizations: some are old but highly effective, others are virtually unknown outside the close community of compiler developers. All of them, in my opinion, are fascinating.

The mbed online environment (SDK,  online tools, active community of developers, and a large selection of reusable code) has been widely adopted by developers as the rapid prototyping environment of choice for ARM-powered microcontrollers. These tools combined with mbed-enabled hardware are great for prototyping designs, but what about taking those next steps to production? This session presents options for starting with mbed as a prototyping environment and moving to full production with the use of Freescale development hardware, the open-source mbed SDK and HDK, and the rich ARM ecosystem of hardware and software tools.

You can make your C code better uickly, cheaply, and easily. Simple techniques can yield surprising improvements in system performance, code size, and power consumption. This session looks at how software applications can make most efficient use of the underlying architecture to deliver significant improvements in performance, code size, and power consumption. All you need is a little inside knowledge about the ARM architecture. You will learn tricks that you can use the day you get back to your office.

ARM processors are increasingly used in automotive applications such as In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS), powertrain, chassis and body control. Moreover, there are emerging opportunities in Vehicle-to-Vehicle and Vehicle-to-Infrastructure (V2V, V2I) applications which further extend the scope and sophistication of computation systems in vehicles of the future.  These developments are driving the next generation of automobile electronics and ARM is enabling use of its technology throughout the automotive industry.  This presentation will introduce the technology behind some of these applications in more detail and describe where and how ARM processors are used in automotive electronics and associated infrastructure applications. Today’s automotive designs are challenged by the cost and complexity of so much advanced hardware and software.  However, ARM technology will deliver solutions to these challenges, such as processors capable of enabling.

In the embedded developer space, we are hearing more about open-source low-cost development platforms such as mbed, Arduino, Raspberry Pi, and BeagleBoard that provide powerful enablers to quickly develop proof-of-concepts demos. As these products move from proof of concept to product development, continued use of open source has obligations. These obligations and risks apply to the developer and the end-users.

This year’s topics are very much a continuation of last year’s, with sessions dealing with ARM servers, the Internet of things, software and power optimization, multicore handling, etc…

If you would like to attend ARM TechCon 2013, you can register online. An alternative is to pay on-site (Regular), but it will cost you, or your company.

  Super Early
Ends August 2
Early Bird
Ends September 6
Advanced
Ends October 25
Regular
All Access Pass $799
$999 $1,199 $1,399
2-Day Pass $699
$799 $899 $999
1-Day Pass $399
$499 $599 $799
Expo Pass $0 $0 $0 $0

The best discount ends tomorrow (2nd of August 2013). Professional working for academia or/and the government can get discount by contacting Linda Kuehn at [email protected].

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Tizen Developer Conference 2013 Presentation Slides, Audio Recording and Videos Are Now Available

July 28th, 2013 No comments

The Tizen Developer Conference took place in San Fransisco, on May 22-24, 2013. We’e already seen a few Tizen demos from the conference, but slides and media files (mostly audio, but also some videos) are now available for keynotes and technical presentations.

Tizen_Web_and_Native_Framework_640px

As this was just the second Tizen conference, there were still many sessions dealing with overall structure of the operating system, and explaining how to get started either with native or web development, such as:

Tizen enters a mobile world dominated by Android and iOS, so several sessions targeted app developers used to work with either operating systems in order to show them how to port their existing apps to Tizen:

Of course, they were also sessions, probably a bit more technical, focused on development of specific features:

And many more, as media files and slides are available for nearly 60 sessions and keynotes.

There’s also a 2-hour developer’s lab (Devlab) session entitled “Creating a Tizen Application: Start to Finish” divided into four parts:

  • Tizen Contest Announcement overview with Brian Warner and Distribution of Tizen USB Drives with Wesley Osaze
  • Tizen Native API Overview with Hod Greeley
  • Tizen Web API Overview with Bob Spencer
  • Live Code Session Overview with Stewart Christie

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Renesas RZ/A1 Cortex A9 Processors Feature Up to 10 MB On-chip RAM

July 6th, 2013 3 comments

Renesas Electronics has recently introduced the RZ/A1 group of ARM Cortex-A9 microprocessors (MPUs) for automotive, consumer and industrial applications requiring user interfaces with displays with a resolution up to 1280×768 (WXGA). The RZ/A1 series will come in three product groups: RZ/A1H, RZ/A1M and RZ/A1L with respectively 10MB, 5MB and 3MB on-chip RAM. These Renesas SoCs are an upgrade to SH7260 Series.

Renesas_RZA1

Key Features (Included in A1H and A1M, but not always in A1L):

  • Core – ARM Cortex A9 @ up to 400 MHz (with Jazelle and NEON)
  • GPU – OpenVG-compliant Renesas graphics processor (2D graphics)
  • Cache – 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache.
  • Built-in memory -  Up to 10-Mbyte large-capacity RAM (128 Kbytes are shared by the data-retention RAM) for A1H, 5MB for A1M, and 3MB for A1L
  • External memory
    • Up to 66.67 MHz bus
    • Direct connection to SRAM, byte select SRAM, SDRAM, and burst ROM (clock synchronous/clock asynchronous) using bus state controller. Address/data multiplexer I/O (MPX) interface supported.
    • Address space: 64 MB × 6.
    • Data bus width: external 8/16/32 bits
  • Graphics Functions:
    • OpenVG1.1 2D graphics accelerator
    • Video display controller (Up to 2 channels of video input and 2 channels of panel output,

    of which 1 channel supports LVDS)

    • Video decoder × 2 channels (analog composite direct input is possible)
    • Distortion correction engine × 2 channels (requires nondisclosure agreement)
    • Distortion correction engine for display (requires nondisclosure agreement)
    • Display out compare unit
    • JPEG codec unit
    • Capture engine unit (CMOS camera interface)
    • Pixel format converter × 2 channels
  • Audio functions
    • SCUX (with built-in asynchronous sampling rate conversion, digital volume & mute, and mixer function)
    • Serial sound interface × 6 channels (× 4 channels for A1L)
    • Renesas SPDIF interface
    • Sound generator × 4 channels
    • CD-ROM decoder
  • Timer functions
    • Multifunction 16-bit timer (MTU2) × 5 channels
    • 32-bit OS timer × 2 channels
    • Motor control PWM timer × 8 channels
    • Watchdog timer
    • Real-time clock
  • Interfaces:
    • USB 2.0 host/function module × 2 channels (host or functon selectable)
    • NAND flash interface
    • SD host interface × 2 channels (must obtain SD card license)
    • MMC host interface
    • Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII)
    • Ethernet AVB (IEEE802.1 Audio/Video Bridging) controller (requires nondisclosure agreement)
    • SPI multi I/O bus controller × 2 channels (up to 2 serial flash memory connectable to 1 channel, direct execution from CPU supported)
    • Serial communication interface with 16-stage FIFO (SCIF) × 8 channels (asynchronous and clock synchronous serial communication possible) Serial communication interface with 16-stage FIFO
    • Serial communication interface × 2 channels (smart card interface, IrDA 1.0)
    • Renesas serial peripheral interface × 5 channels (× 3 channels for A1L)
    • I2C bus interface × 4 channels
    • Media Local Bus (MediaLB Ver2.0)
    • Controller area network (CAN) × 5 channels (× 2 channels for A1L)
    • Local interconnect network interface (LIN) × 2 channels (x 1 channel for A1L)
  • System analog functions
    • Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit
    • Direct memory access controller × 16 channels
    • Interrupt controller (with ARM Generic Interrupt Controller [PL390])
    • A/D converter (12-bit resolution) × 8 channels
    • Debugging interface
    • CoreSight architecture
    • JTAG standard pin layout

     

  • Optional function – Encryption engine (requires nondisclosure agreement)
Renesas RZ/A1 Series Block Diagrams (Differences between RZ/A1H & M and RZ/A1L are shown in red)

Renesas RZ/A1 Series Block Diagrams (Differences between RZ/A1H & M and RZ/A1L are shown in red)

Thanks to the integrated on-chip RAM from 3MB to 10MB it’s possible to develop applications without external memory, lowering the BoM cost, EMI, and static power consumption.

Renesas has partnered with several partners including IAR systems, Green Hills Software, ARM, Express Logic, Micrium, and Altia to provide tools and middleware solutions for real-time operating systems (RTOS), networking, USB, graphics and file systems.. In particular, Renesas and ARM are jointly developing a version of RTX CMSIS (Cortex Microcontroller Software Interface Standard)-RTOS for the Cortex-A in order to facilitate transition of application software developed from Cortex-M processors to Cortex-A processors. It’s available in ARM DS-5 for Renesas RZ/A1.

GENMAI CPU Board (RTK772100BC00000BR#ES)


GENMAI CPU Board (R7S72100 CPU Board RTK772100BC00000BR)

To start development early, you can use those software tools on GENMAI CPU Board powered by a 324-pin BGA RZ/A1H processor with 64 MB x 2 NOR flash, 64 MB x 2 SDRAM, 64 MB x 3 Serial flash memory and 16KB EEPROM, as well as most ports supported by the SoC.

The company said samples of select RZ/A1L and RZ/A1H products will be available in July 2013. Further details are available on Renesas RZ/A1 page.

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Tizen Shows Up in Smartphones, Ultrabooks, and Cars

May 25th, 2013 1 comment

I’ve seen a lot of tweets about Tizen in the last fews days, mainly because Tizen Conference 2013 just took place. First there’s been Tizen 2.1 SDK release, and few demos have surfaced,  showcasing Tizen in their target devices: smartphones, tablets,smart TVs, laptops, and In-vehicle infotainment devices. Beside all the work done, the companies behind the project will also offer $4 million to developers who publish apps on Tizen store. There will be 9 categories. The best 3 games will get $200,000 each, and the best apps in the other 6 categories $120,000 each. Tizen App Challenge will start on June 3, 2013, and you can see details for this program here.

Tizen in a Laptop (Left) and an Automotive Infotainment System (Right)

Tizen in a Laptop (Left) and an Automotive Infotainment System (Right)

Let’s see the demos. First Tizen in Samsung developer smartphone running Qt 5.1, and the usual Qt5 Cinematic Experience demo, as well as 2 others apps, both super smooth. (via TizenExperts). You can find more information in Qt for Tizen page.

This is not the first time we see Tizen running on Samsung Developer platform, but Qt5.1 is very recent.

The next demo shows Tizen running on an Intel Core i7 Ivy Bridge UltraBook at Tizen Conference 2013 via TizenExperts. The desktop environment is based on GNOME 3 Shell, and beside the HTML5 apps, you’ll be able to run applications such as LibreOffice and Chrome, just like in any other Linux distributions. They also demo Stream in the device, running Team Fortress 2. Finally, they showed Tizen SDK, developing Tizen Apps, and running an OpenGL accelerated smartphone simulator.

Overall, I find the experience feels a little like Ubuntu. Th demo shown above runs the latest Tizen 2.1, but laptop support should be officially part of Tizen 3.0 release.

Jaguar Land Rover, Intel, and the Linux foundation collaborated to create the last demo I’ll show today (via TizenTalk). It’s an in-vehicle infotainment systems (IVI) running Tizen in a Land Rover. It features a standard car interface, support for gstreamer to play audio and video, a demo app store, and a demo GPS positioning system app. The demo is not a product per say, it’s said to be a fully open source demo, so that other people can work on it. You can find the detail on Linux Foundation Automative Grade Linux (AGL) page.

If you’re particularly interested in the work done for “alternative” mobile operating systems with project such as Sailfish, Mer, Tizen, and Qt, on ARM and x86 hardware, you may want to follow @vgrade on twitter.

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VIA Unveils VAB-600 Pico-ITX Board Powered by WM8950 Processor

May 2nd, 2013 1 comment

VIA Technologies has recently announced the VAB-600 Pico-ITX embedded board featuring WonderMedia WM8950 ARM Cortex A9 SoC clocked at 800MHz. VIA targets in-vehicle infotainment as well as mobile and healthcare applications for the board despite an operating temperature range between 0°C and 60°C.

VIA VAB-600 Pico-ITX Board (Click to Enlarge)

VIA VAB-600 Pico-ITX Board (Click to Enlarge)

Here are the key features of this embedded board:

  • SoC – Wondermedia WM8950 Cortex-A9 @ 800MHz  + Mali-400 GPU
  • System Memory – 1GB DDR3 SDRAM
  • Storage – 4GB eMMC Flash memory + 512KB SPI Flash for Boot Loader + microSD slot
  • Video Output – Mini HDMI, on-board DVO (Digital Video Output) for TTL or LVDS display
  • Video Codecs – MPEG2 MP@HL, MPEG4, H.264 BP/MP/[email protected], VC-1 SP/MP/AP, VP8 and JPEG/MJPEG.
  • USB -  2x mini USB 2.0 host ports
  • Connectivity – 10/100M Ethernet (VT6113), 3G (SIM card slot) and optional WiFi support (VIA VNT9271B6050 WiFi module shared with one USB port)
  • On-board Connectors:
    • 2x COM connectors
    • 1x RTC battery pin header
    • 1x USB 2.0 connector
    • 1x SPI connector for programming SPI Flash ROM
    • 1x Keypad connector
    • 1x CIR connector
    • 1x Front audio pin header for Line-in, Line-out and MIC-in
    • 1x Front panel pin header for system power-on, reset and power LED
    • 4-wire resistive touch screen FPC connector (through VT1603A)
    • 1x pin header for 1 I2C pair and 8 GPIO
    • Optional battery charger connector with Smart Battery function
  • Operating Temperature Range – 0°C to 60°C
  • Operating Humidity – 0% ~ 95% (relative humidity ; non-condensing)
  • Dimensions – 10cm x 7.2cm Pico-ITX form factor

VIA_VAB-600_Block_Diagram

The company provides board support packages (BSPs) for Android 4.0 and/or Embedded Linux (Kernel 3.0.8). Android 4.0 EVK is available for download here, but there’s nothing for Linux yet. Before downloading the file you’ll have to agree to a “Non-Disclosure and Recipient Acknowledgment for Short Term Sample Products Evaluation”, which I find a bit silly for a publicly available file…

VIA also offers a startker kit including VIA VAB-600 Pico-ITX board, VAB-600-A I/O card, VAB-600-C TTL Converter card, a 7” touch screen TTL panel, cables and a 18W AC adapter.

VIA VAB-600 Starter Kit (Click to Enlarge)

VIA VAB-600 Starter Kit (Click to Enlarge)

Sample units of the VIA VAB-600 Pico-ITX board are available now at an undisclosed price. Further information, including the board user’s manual and product brief, is available on VIA’s VAB-600 page.

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Renesas R-Car H2 is an Octo Core big.LITTLE Processor for Your Car

March 27th, 2013 No comments

Renesas announced a new automotive SoC called the R-Car H2 that features 4 Cortex-A15 cores together with 4 Cortex A7 cores (optional) in big.LITTLE configuration, as well as an Imagination PowerVR Series6 G6400 GPU. This SoC can optionally come with Renesas SH-4A, a real-time processing CPU core acting as a multimedia engine (MME) , and Renesas’ IMP-X4 core, a real-time image processing unit that enables developers to implement augmented reality application such as 360-degree camera views and image recognition.

This Renesas processor is a multimedia power house, as it can handle 4x 1080p video en/decoding, including Blu-Ray support at 60 frames per second, as well as image/voice recognition and high-resolution 3D graphics with virtually no CPU usage.

Renesas R-Car H2 Block Diagram

Renesas R-Car H2 Block Diagram

Here are R-Car H2′s specifications provided on Renesas website:

Product number R8A7790x
Power supply voltage 3.3/1.8 V (IO), 1.5/1.35 V (DDR3), 1.0 V (Core)
CPU core ARM Cortex-A15
Quad
ARM Cortex-A7
Quad (device option)
SH-4A core
(device option)
Cache memory L1 Instruction cache:
32 KB
L1 Operand cache:
32 KB
L2 Cache:
2 MB
L1 Instruction cache:
32 KB
L1 Operand cache:
32 KB
L2 cache:
512 KB
Instruction cache:
32 KB
Operand cache:
32 KB
External memory DDR3-SDRAM
Maximum operating frequency: 800 MHz
Data bus width: 32 bits × 2 ch (6.4 GB/s × 2)
Expansion bus Flash ROM and SRAM,
Data bus width: 8 or 16 bits
PCI Express 2.0 (1 lane)
Graphics PowerVR Series6 G6400 (3D)
Renesas graphics processor (2D)
Video Display Out × 3 ch (2 ch: LVDS, 1 ch: RGB888)
Video Input × 4 ch
Video codec module (H.264/AVC, MPEG-4, VC-1)
IP conversion module
JPEG accelerator
TS Interface × 2 ch
Video image processing (color conversion, image expansion, reduction, filter processing)
Distortion compensation module (image renderer) × 4 ch
High performance Real-time Image recognition processor (IMP-X4) (device option)
Audio Audio DSP
Sampling rate converter × 10 ch
Serial sound interface × 10 ch
MOST DTCP
Storage Interface USB 3.0 Host interface × 1 port (wPHY)
USB 2.0 Host interface × 3 port (wPHY)
SD Host interface × 4 ch (SDXC, UHS-I)
Multimedia card interface × 2 ch
Serial ATA interface × 2 ch
In car network and automotive peripherals Media local bus (MLB) Interface × 1 ch (6pin / 3pin interface selectable)
CAN Interface × 2 ch
IEBus Interface
GPS baseband module (Galileo, GLONASS) (device option)
Ethernet controller AVB (IEEE802.1BA, 802.1AS, 802.1Qav and IEEE1722, GMII/MII, without PHY)
Security Crypto engine (AES, DES, Hash, RSA)
SecureRAM
Other peripherals DMA controller
LBSC DMAC: 3 ch / SYS-DMAC: 30 ch / RT-DMAC: 3 ch / Audio-DMAC: 26 ch / Audio (peripheral)-DMAC: 29 ch
32bit timer × 12 ch
PWM timer × 7 ch
I2C bus interface × 8 ch
Serial communication interface (SCIF) × 10 ch
Quad serial peripheral interface (QSPI) × 1 ch (for boot)
Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
Ethernet controller (IEEE802.3u, RMII, without PHY)
Interrupt controller (INTC)
Clock generator (CPG) with built-in PLL
On chip debugger interface
Low power mode Dynamic Power Shutdown (CPU core, 3D, IMP)
AVS and DVFS function
DDR-SDRAM power supply backup mode
Package 831 pin Flip Chip BGA (27 mm × 27 mm)

For development, Renesas provides ICE for ARM CPU, as well as an evaluation board including car information system-oriented peripheral circuits. The platform supports QNX Neutrino RTOS, Windows Embedded Automotive, and Linux.

Renesas R-Car H2 samples are available now, and mass production is scheduled for mid-2014. More information is available on on Renesas R-Car H2 page.

Via Embedded.com

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$21 CARAPP APP327 Bluetooth OBD2 Car Diagnostic Scanner

February 26th, 2013 9 comments

As cars become more sophisticated, you’re now able to access all sort of data from your car and display this on a computer or tablet to diagnose problems or simply to create your own high-end dashboard. This morning, I’ve come across CARAPP APP327, a Bluetooth diagnostic scanner compatible with OBD2 standard (On-Board Diagnostic II), which could can just connect on an OBD2 connector if your car is recent enough. This has been around for many years (since 1996), but I had never heard about this technology until today.

OBD2 Connector (Left) - CARAPP APP327 Bluetooth Scanner (Right)

OBD2 Connector (Left) – CARAPP APP327 Bluetooth Scanner (Right)

Wikipedia OBD2 page explains the OBD2 connector (16-pins) should be within 2 feet (0.61 m) of the steering wheel according to the standard, which also specifies the type of diagnostic connector and its pinout, the electrical signaling protocols available, and the messaging format. After you connect the Bluetooth adapter, you just need to install the applications needed for your platform (e.g. Android, Windows, iOS, etc…) which you can get from an installation CD, or download an application that supports OBD2 standard such as Torque Pro or Torque Lite for your Android device.

Torque_Pro_ODB2_Interface

Torque Pro User Inteface

Let’s go back to CARAPP APP123 and its key features:

  • Function – Read trouble codes, check trouble codes, display current sensor data, calculate fuel oil consumption.
  • Wireless – Bluetooth with a transmission range up to 10 m
  • Interface – 16-pin OBD2
  • Software Platforms – Android, Win XP / Win 7 / PPC (Windows Mobile)
  • Protocols Supported – ISO15765-4 (CAN), ISO14230-4(KWP2000), J1850 PWM, J1850 VPW, ISO9141-2
  • Output Protocol – OBD2 @ 115.2Kbps
  • Power – 12 V / 35 mA working current

The device can report the engine and vehicle speed, load values, the temperature of the cooling liquid, the fuel system status, short-term fuel adjustment, long-term fuel trim, the air flow rate, oxygen sensor voltages, fuel pressure and more. Since it follows OBD2 standard I would think it’s compatible with Torque Pro/Lite, but could not find specific demo videos for this particular device.

CARAPP APP12 costs $21 on Dealextreme, but other cheaper and more popular ODB2 Bluetooth diagnostic scanners are also available such as Soliport ELM 327.

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Categories: Android, Hardware Tags: automotive, can, obd2