I2C (Inter-Integrated Circuit) is one of the most commonly used serial bus for interfacing sensors and other chips, and use two signals (Clock and Data) to control up to 128 chips thanks to its 7-bi address scheme. After announcing it was working of a new I3C standard in 2014, the MIPI Alliance has now formally introduced the MIPI I3C (Improved Inter Integrated Circuit) Standardized Sensor Interface, a backward compatible update to I2C with lower power consumption, and higher bitrate allowing it to be used for applications typically relying on SPI too.
I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved are 11.1,20, 23.5 and 33.3 Mbps.
The MIPI Alliance has also provided a tablet comparing I3C, I2C, and SPI features, advantages and disadvantages.
|Number of Lines||2-wire||2-wire (plus separate wires for each required interrupt signal)||4-wire (plus separate wires for each required interrupt signal)|
|Effective Data Bitrate||33.3 Mbps max at 12.5 MHz
(Typically: 10.6 Mbps at 12 MHz SDR)
|3 Mbps max at 3.4 MHz (Hs)
0.8 Mbps max at 1 MHz (Fm+)
0.35 Mbps max at 400 KHz (Fm)
|Approx. 60 Mbps max at 60 MHz for conventional implementations (Typically: 10 Mbps at 10 MHz)|
You’ll find more technical details by downloading MIPI I3C specifications and/or whitepaper (free email registration required). Note that only MIPI member can have access to the complete specifications.