Wave Computing to Open Source MIPS Architecture

There has been a lot of talks about RISC-V open source, royalty-free instructions set architecture this year,  including the launch of RISC-V MCUs and Linux capable RISC-V processors,  and corresponding development boards such as Hifive Unleashed. This even lead Arm to create a – now shutdown – microsite telling why people should stick with Arm instead of RISC-V.

While RISC-V was clearly on the rise this year, MIPS architecture once a dominant players in routers and set-top box has been on the decline, even prompting Blu to write a guest review entitled “Baikal T1 MIPS Processor – The Last of the Mohicans?” hinting at the near extincsion of MIPS based solutions. But there may be hope, or at least a last ditch effort, with Wave Computing purchasing MIPS from Imagination Technology earlier this year, and now announcing the MIPS Open Initiative to effectively open source 32-bit and 64-bit MIPS ISA next year, as well as making the ISA royalty-free, just like RISC-V.

MIPS Open Source

There’s does not seem to be any tricks based on the wording about the announcement:

Wave Computing… announced it will open source its MIPS instruction set architecture (ISA) to accelerate the ability for semiconductor companies, developers and universities to adopt and innovate using MIPS for next-generation system-on-chip (SoC) designs. Under the MIPS Open program, participants will have full access to the most recent versions of the 32-bit and 64-bit MIPS ISA free of charge – with no licensing or royalty fees.  Additionally, participants in the MIPS Open program will be licensed under MIPS’ hundreds of existing worldwide patents

Previous versions such as MIPS r5 won’t be open source, but MIPS Release 6 will be fully open source with the following components to be made open source:

  • The open source version of the 32 and 64-bit MIPS Instruction Set Architecture (ISA), Release 6
  • MIPS SIMD Extensions
  • MIPS DSP Extensions
  • MIPS Multi-Threading (MT)
  • MIPS MCU
  • microMIPS Architecture
  • MIPS Virtualization (VZ)

The launch is scheduled to take place in Q1 2019 with all resources available on MIPS Open Community website (not loading for me). RISC-V has all the hype, and people interested in royalty-free, open source SoC got involved, so it remains to be seen if people will jump back to MIPS once it comes with the same benefits. MIPS ISA does have the advantage of having a much mature ecosystem than RISC-V, and MIPS is already found in millions of commercial devices.

Wave Computing will still receive licensing revenues from the older MIPS ISA, but as I understand it not for MIPS r6 anymore, so they may monetize MIPS ISA by promoting the use of their AI Dataflow technology in MIPS based processors. We’ll learn more early next year.

Via EETimes

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willy
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willy

Well, maybe they only needed a CPU to support their technology, MIPS was affordable enough, and they figured that the revenue they could make out of it is much lower than what they can make by having their technology widely adopted, and that in the end opening MIPS could boost their adoption enough to cover their royalties losses. If so that’s an excellent move and a good understanding of how opensource works.

blu
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blu

I salute this move. MIPS has the maturity, the spectrum and the evolutionary spark that it would’ve been a huge loss for all this to vanish. Wave did the right thing at a dire moment.

blu
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blu

BTW, browsing through some of the responses on the interwebs, the amount of misinformation, lack of fact checking and sheer oblivion re MIPS is mind-boggling — people (who have hardly every touched a MIPS) complain about ‘the horrible architecture deficiencies’ of MIPS referring to things that were present in MIPS I (1985) or perhaps MIPS II (mips r1). Contemporary MIPS is at r5, and this open-sourcing initiative affects r6!

Arnd Bergmann
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Arnd Bergmann

I agree that opening MIPSr6 is a good step for them and for the industry, but I also get the feeling that MIPS themselves could have been a bit clearer about what they do to avoid the misinformation:
They keep citing the billions of MIPS devices that have been shipped as the main reason for the maturity of the architecture, but conveniently leave out the bit about almost all of them being r2 or older while the cleaned-up r6 is only partially compatible with that, and not compatible with the new nanomips at all. It is logical that they want to keep the licensing revenue from their older architecture releases.

Additionally, it’s not clear what exactly “open sourcing the ISA” means for them. From the little details put out so far, it sounds like you have to join their organization to get the patent license, but they have not said if you can make derived works or distribute what you get to non-members, or if they would incorporate changes in future releases. It’s not even clear what “source” is here, since there is no open HDL implementation initially, and the MIPS instruction set manual (in pdf form, not its source) has been available for public download for a while.

There are also several open source MIPS32r1 (or older) compatible cores listed on opencores.org, since those patents have apparently all expired (r2 has a number of extensions that will likely require a patent license for a couple more years), so there is no fundamental change here, rather than gradually opening up additional versions of the architecture.

We’ll have to wait until next year if there is more to it than lowering the cost of a single product they never sold (MIPSr6 architecture license) to zero as a clever marketing move to benefit from the hype about RISC-V, and if anyone still cares enough to actually start using it.

blu
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blu

I agree — things most definitely need some clarifying by Wave Computing. But even taking the news at face value — i.e. r6 free of licencing, and even if we assumed derived work (i.e. r6 with somebody’s extensions) would be automatically open-source (i.e. a worse-case scenario for chip vendors), this is still an ISA IP breakthrough and a big deal, as vendor’s added-value sauce is usually in the uarch, not so much in the ISA. Clearly here I’m leaning more towards the ‘standardization over a good ISA’ side of things, vs the Xtensa side of things.

theguyuk
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theguyuk

Well they need a mass market product adoption going forward. As for phones apple have their own SoC and Android are arm as far as I am aware. TV box?, TV, tablet market dies, laptop, mini PC, router, which ones

slackstick
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slackstick

MIPS R6 is not upward compatible with previous versions, was established in 2014 and has AFAIK zero implementations. Why should one move to R6 and not to RISC-V directly? Sorry, MIPS, too little, too late. A more clever move for Wave would be to move their cores to RISC-V.

theguyuk
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theguyuk

MIPS need to produce a mass market chip ( fabless )

blu
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blu

That’s what Imagination used to do back in the day — they sold stock cores, same way Arm does.

blu
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blu

> Why should one move to mips r6 and not to risc-v directly?

That’s a very good question. Some possible answers:

1. Better ISA extensions availability — SIMD & DSP — I can attest to the former being a modern SIMD extension akin to ASIMD2 and AVX128, and available since r5. Unless things have progressed rapidly since I checked last, RV is yet to get its SIMD ISA — its draft is developing rather well but some paradigms there will need to be tested in practice.
2. Better compiler support, particularly under excessive ISA segmentation. Compilers handle all MIPS revisions well. Now consider the following rudimentary code snippet on rv32ima: https://godbolt.org/z/TkIk76

Notice how clang does not bother to emit the two atomic instructions it’d take rv32ima to do the requested exchange, but instead: (1) sets up a stack frame, and (2) calls a lib routine that executes the exchange? When will clang get proper support for all the possible combinations of RV extensions? How about gcc?

For comparison, here’s what the 2014-introduced mips r6 gets from the same code: https://godbolt.org/z/tAoKDP

slackstick
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slackstick

Atomic Extension for RV was defined in 2017. I wouldn’t consider it too difficult to use these instruction directly inside a compiler. Of course, good compiler support takes time. However, implementing a chip also takes time.

Member

LLVM support for RISC-V is relatively recent and immature, IIRC it was upstreamed only this year. Given the fast pace of development in the RISC-V world though it should mature pretty quickly.