MuseLab USB-HS-Bridge is an inexpensive ($5) board based on WCH CH347 chip with a USB 2.0 Type-C interface that acts as a bridge for I2C, SPI, UART, and JTAG interfaces, as well as GPIOs. It’s notably useful to debug and download bitstreams to FPGA development boards, but it can also be used to connect various peripherals such as I2C sensors, SPI flash devices, UART devices to basically any host with a spare USB 2.0 host port. USB-HS-Bridge specifications: Chip – WCH CH347 high-speed USB to UART, I2C, SPI and JTAG chip (See link to the datasheet for details) USB – 1x USB 2.0 Type-C port with up to 480 Mbps data rate I/Os – 2x 16-pin header with 2x UART interfaces up to 9 Mbps baudrate 1x I2C for EEPROM or sensors 1x SPI master interface with 2 chip select signals to control up to 2x SPI slave devices. The […]
There are already several serial terminal programs such as Putty and minicom, and in recent times, I’ve been using Bootterm myself. But that does not mean there isn’t room for more and Martin Lund has developed tio serial device I/O tool for Linux. Martin found out many of the existing tools are very modem focused or a bit cumbersome to use, so he developed tio as the simpler alternative which puts less focus on classic terminal/modem features and more focus on the needs of embedded developers and hackers.
As a StarFive Technology in-house developed RISC-V 64-bit ultra-high-performance core, Dubhe showcases the best performance RISC-V CPU core IP yet. It utilizes the latest RISC-V instruction set which includes RV64GC, bit operation extension (B), vector extension (V) V1.0, and hypervisor extension H (Hypervisor), making it ideal for high-performance computing. To pair with the Dubhe performance core, StarFive is now releasing “StarFive Perf Performance Profiling Tool”. StarFive has made Perf compatible with the hardware performance monitor (HPM) and micro-architecture events at the hardware level. Perf provides a reliable performance verification platform that not only facilitates customers to further discuss the Dubhe technical specifications but also accelerates the implementation of high-performance applications with RISC-V processors. Perf is an open-source and Linux-based performance analyzing tool capable of providing performance monitoring of the hardware events, tracepoints, firmware events, and dynamic probes. With the Perf profiling tool, we can monitor the performance of the predefined […]
WCH CH340 family of USB to serial chip is very popular, and often found on development boards for debugging/access to the serial console, but the company has now introduced the CH343 “Gen3” chip – just like CH9102F apparently – with a higher 6 Mbps baud rate, support for 1.8V, 2.5V, 3.3V, and 5V IO voltage, and the ability to request custom USB VID/PID numbers. Three variants exist with CH343P, CH343G, and CH343K with different packages: QFN16, SOP16, and ESSOP10 respectively. CH343P contains an EEPROM for easy customization, while CH343G and CH343K PID/VID can still be customized for larger orders. CH343 key features and specifications: Full-speed USB 2.0 device interface Hardware full-duplex serial UART interface with baud rate varies from 50bps to 6Mbps. Automatic identification and dynamic adaptation of common communication baud rate of 115200bps and below. Supports 5, 6, 7, or 8 data bits, as well as odd, even, space, […]
Espressif’s ESP USB Bridge is a project based on the ESP-IDF that leverages ESP32-S2 or ESP32-S3 USB interface to use the board as a USB to UART or USB to JTAG debug board. It can serve as a substitute for USB to TTL debug boards based on CH340 or CP2104 for instance, be used with OpenOCD in JTAG bridge mode, and also flash UF2 firmware file to the target board. As just mentioned, there are three main use cases: Serial bridge mode with a terminal program or a firmware flashing tool like esptool. In that case, it just works like your typical USB to TTL debug board JTAG bridge mode for JTAG debugging with OpenOCD, and if the target board is based on ESP32, you can use openocd-esp32 project Mass storage device where the board can be accessed by a file manager on the host computer. One of the specific […]
If you need to control or debug multiple devices over UART devices, you’d be glad to learn WCH has just launched the CH348 USB to serial chip with eight UART ports. Two models are offered CH348L in an LQFP100 package and CH348Q in an LQFP48 package. Both offer eight UART interfaces, but CH348L comes with more CTS/RTS and DTR/hardware flow control signals, as well as DTR, DCD, RI signals, and support for independent voltage for I/Os. CH348 key features specifications: High-speed USB device interface Hardware full-duplex serial port, integrated independent transmit-receive buffer Baud rate varies from 1200bps to 6Mbps. The serial ports support 8 data bits, odd, even, and none parity, 1/2 stop bit. Each serial port comes with a 2048-byte receiving FIFO and a 1024-byte transmitting FIFO. Signals RTS, DTR, DCD, RI, DSR, and CTS supported for hardware flow control The MODEM interface signal pins and 485 transmit and […]
Linus Torvalds released Linux 5.15, an LTS version, this past Sunday: It’s been calm, and I have no excuse to add an extra rc, so here we are, with v5.15 pushed out, and the merge window starting tomorrow. Which is going to be a bit inconvenient for me, since I also have some conference travel coming up. But it’s only a couple of days and I’ll have my laptop with me. Sometimes the release timing works out, and sometimes it doesn’t.. Anyway, the last week of 5.15 was mainly networking and gpu fixes, with some random sprinkling of other things (a few btrfs reverts, some kvm updates, minor other fixes here and there – a few architecture fixes, couple of tracing, small driver fixes etc). Full shortlog appended. This release may have started out with some -Werror pain, but it calmed down fairly quickly and on the whole 5.15 was […]
The Arm DevSummit 2021 is taking place on October 19-21, and the first announcements from Arm are related to IoT with “Arm Total Solutions for IoT delivering a full-stack solution to significantly accelerate IoT product development and improve product ROI”, “Project Centauri” aiming to achieve for an extensive Arm Cortex-M software ecosystem in the way that Project Cassini does for the Cortex-A ecosystem, starting with support for PSA Certified and Open-CMSIS-CDI cloud-to-device specification, and Arm Virtual Hardware based on Corstone-300 IoT platform with a Cortex-M55 MCU core and an Ethos-U55 microNPU accessible from Amazon Web Services. The first two are quite abstract right now, and more information may become available in the future, but the Arm Virtual Hardware is available now from AWS as a public beta, with 100 hours of free AWS EC2 CPU credits for the first 1,000 qualified users. The virtual hardware does not emulate only the […]