SiFive Partners with Western Digital to Produce 1 Billion RISC-V Cores

Architecture like Arm and x86 are well established, and initiatives like RISC-V opens source ISA have potential, but market acceptance and commercial success are not guaranteed. But RISC-V just got a big boost, as SiFive announced it raised $50.6 million in a Series C round from existing and new investors, as well as strategic partners such as Huami, SK Telecom and Western Digital. Even more importantly, Sifive and Western Digital signed a multi-year license for the Freedom Platform, with Western Digital pledging to produce 1 billion RISC-V cores. The announcement does not explicitly mention which Freedom platform, but Western Digital statement makes it quite clear they’ll use one of the more powerful (and Linux capable) core: RISC-V delivers a platform for innovation unshackled from the proprietary interface of the past. This freedom allows us to bring compute closer to data to optimize special purpose compute capabilities targeted at Big Data and Fast Data applications. The next generation of applications like Machine …

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How to Run Linux on RISC-V with QEMU Emulator

RISC-V open source architecture is starting to become more and more interesting thanks the growing RISC-V hardware & software ecosystem, and with the recent release of HiFive Unleashed, we even have a board capable of running Linux. The only problem: it costs $999. But luckily, it’s possible to experiment with Linux on RISC-V without extra hardware, just using your current PC. Imperas offers a commercial solution working on both Windows and Linux that relies on busybear-linux RISC-V Linux root filesystem comprised of busybox and dropbear SSH server. The rootfs also works with QEMU, so I tried it in Ubuntu 16.04. The instructions on Github are quite easy to follow. My computer is powered by an AMD FX8350 processor coupled with 16GB RAM, and the whole process took around 2 hours, so better use the fastest computer possible. It also requires around 26 GB of storage on your build machine. First, let’s create a working directory, and retrieve the RISC-V toolchain: …

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RISC-V Keynote at Embedded Linux Conference 2018 (Video)

The Embedded Linux Conference and OpenIoT Summit 2018 have just started, and the Linux Foundation has already uploaded a few keynote videos to YouTube, including the one by Yunsup Lee, Co-Founder and CTO, SiFive, entitled “Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware”. Yunsup explains the current problem with chip development, and go through the open source RISC-V solutions offered by Sifive. Currently design a chip has a high upfront (NRE = non-recurring engineering) costs, is time-consuming (1.5 to 2 years at least) and silicon vendors normally target high volume production, but now many applications like IoT or machine learning require custom chips that may not be (yet) manufactured in such high volume. The solution is to adapt some idea from open source software to open source hardware in order to lower the costs, enable fast prototyping, and involve the community of designers and software developers. He took Instagram as an example, as it sold for $1 billion …

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GreenWaves GAP8 is a Low Power RISC-V IoT Processor Optimized for Artificial Intelligence Applications

GreenWaves Technologies, a fabless semiconductor startup based in Grenoble, France, has designed GAP8 IoT application processor based on RISC-V architecture, and optimized for image and audio algorithms including convolutional neural network (CNN) inference with high energy efficiency thanks to an 8-core computational cluster combined with a convolution hardware accelerator. The design is based on RISC-V based Parallel Ultra Low Power (PULP) computing open-source platform. The new processor targets industrial and consumer products integrating artificial intelligence, and advanced classification such as image recognition, counting people and objects, machine health monitoring, home security, speech recognition, consumer robotics, wearables and smart toys. Some of GAP8 processor specifications: 1x extended RISC-V fabric controller core with 16 kB data and 4 kB instruction cache for system control 8x extended RISC-V compute cores with 64 kB shared data memory and 16 kB shared instruction cache 1x Hardware optimized synchronization unit 1x Hardware Convolution Engine (HWCE) Multi channel 1D/2D DMA, specialized multi-channel micro DMA for autonomous peripheral …

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Embedded Linux Conference & IoT Summit 2018 Schedule

The Embedded Linux Conference 2018 and the OpenIoT Summit 2018 will jointly take place next month, on March 12 – 14, 2018 in Portland, Oregon, USA. The former is a “vendor-neutral technical conference for companies and developers using Linux in embedded products”, while the latter is a “technical conference for the developers and architects working on industrial IoT”. The Linux Foundation has already published the schedule, and it’s always useful to learn what will be discussed about even for people who won’t attend. With that in mind, here’s my own virtual schedule with some of the talks I find interesting / relevant to this blog. Monday, March 12 10:50 – 11:40 – Progress in the Embedded GPU Ecosystem by Robert Foss, Collabora Ltd. Ten years ago no one would have expected the embedded GPU ecosystem in Linux to be what it is now. Today, a large number of GPUs have Open Source support and for those that aren’t supported yet, …

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SiFive Introduces HiFive Unleashed RISC-V Linux Development Board (Crowdfunding)

RISC-V free and open architecture has gained traction in the last couple of years. SiFive has been one of the most active companies with RISC-V architecture, introducing Freedom U500 and E500 open source RISC-V SoCs in the summer of 2016, before launching their own HiFive1 Arduino compatible board, and later the official Arduino Cinque board. That’s fine if you are happy with MCU class boards, but RISC-V is getting into more powerful processors, and recently got initial support o Linux 4.15, so it should come as no surprise the company has now launched HiFive Unleashed, the first RISC-V-based, Linux-capable development board. HiFive Unleashed key features and specifications: SoC – SiFive Freedom U540 with 4x U54 RV64GC application cores @ up to 1.5GHz with Sv39 virtual memory support, 1x E51 RV64IMAC Management Core, 2 MB L2 cache;  28 nm TSMC process System Memory – 8GB DDR4 with ECC Storage –  32MB Quad SPI Flash from ISSI, MicroSD card for removable storage …

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SiFive U54-MC Coreplex is the First Linux Ready RISC-V based 64-bit Quad-Core Application Processor

We first covered SiFive when they unveiled their open source Freedom RISC-V SoCs. Since then, they moved away from open source for their customizable IP, since their customers did not require fully open source designs, but kept releasing more RISC-V cores such as 32-bit E31 Coreplex & 64-bit E51 Coreplex, as well as offering their one-time fee pricing without recurring royalties, contrary to what some competitors – such as Arm – are doing. The company has now just announced U54-MC Coreplex quad core real-time capable application processor with support for full featured operating systems such as Linux. U54-MC Coreplex main specifications / features: Fully compliant with the RISC-V ISA specification 4x RV64GC U54 Application Cores 32KB L1 I-cache with ECC, 32KB L1 D-cache with ECC 8x Region Physical Memory Protection 48x Local Interrupts per core Sv39 Virtual Memory support with 38 Physical Address bits 1x RV64IMAC E51 Monitor Core 4KB L1 I-Cache with ECC 8KB DTIM with ECC 8x Region …

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LoFive is a Tiny Open Source Hardware Board based on SiFive FE310 RISC-V Open SoC

Do you remember HiFive1? It’s an Arduino compatible board based on the SiFive FE310 open source RISC-V SoC. Michael Welling has now started working on LoFive board using the same processor, but in a much smaller & breadboard friendly form factor. LoFive board specifications: MCU – SiFive Freedom E310 (FE310) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz) Storage – 128-Mbit SPI flash (ISSI IS25LP128) Expansion – 2x 14-pin headers with JTAG, GPIO, PWM, SPI, UART, 5V, 3.3V and GND Misc – 1x reset button, 16 MHz crystal Power Supply – 5V via pin 1 on header; Operating Voltage: 3.3 V and 1.8 V Dimensions – 38 x 18 mm (estimated) The board will be programmable with Arduino IDE + Cinco just like HiFive1 board. The board is also open source hardware, so beside the aforelinked info on Hackster,io, you’ll also find the KiCAD schematics, PCB layout, and 3D renders, released under CERN Open Hardware License v1.2, on …

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