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Posts Tagged ‘soc’

Qualcomm Provides Details about 64-bit ARM Falkor CPU Cores used in Centriq 2400 Server-on-Chip

August 21st, 2017 8 comments

Qualcomm officially announced they started sampling Centriq 2400 SoC with 48 ARMv8 cores for datacenters & cloud workloads using a 10nm process, but at the time the company did not provide that many details about the solution or the customization made to the CPU cores.

Qualcomm has now announced that Falkor is the custom CPU design in Centriq 2400 SoC with the key features listed by the company including:

  • Fully custom core design – Designed specifically for the cloud datacenter server market, with a 64-bit only micro-architecture based on ARMv8 (Aarch64).
  • Scalable building block The Falkor core duplex includes two custom Falkor CPUs, a shared L2 cache and a shared bus interface to the Qualcomm System Bus (QSB) ring interconnect.
  • Designed for performance, optimized for power
    • 4-issue, 8-dispatch heterogeneous pipeline designed to optimize performance per unit of power, with variable length pipelines that are tuned per function to maximize throughput and minimize idle hardware.
    • power management techniques: independent p-state control for each of the CPUs and L2, with entry to and exit from low-power states controlled by hardware state machines, and hardware state retention for power-collapsed sleep states with ultra-fast recovery.
  • Performance under memory-intensive workloads Falkor is designed to fulfill the demand for larger instruction footprints using an innovative split instruction cache comprised of a single-cycle, low-power 24KB L0 I-cache complementing its 64KB L1 I-cache. The core also supports a 32KB L1 D-cache with a 3-cycle load-use latency. The L1 D-cache is augmented by a sophisticated multi-level hardware prefetch engine that dynamically adapts to system conditions.
  • Datacenter features
    • ARM Execution Levels (EL0-EL3) and TrustZone secure execution environment.
    • ARMv8 instruction extensions to accelerate cryptographic transform and secure hash operations such as AES, SHA1, and SHA2-256
    • RAS mechanisms needed to keep a datacenter running, such as fault isolation, reporting, and handling techniques.
  • System on a chip – The 48 Falkor CPUs are brought together in a fully-integrated SoC with high-bandwidth and low-latency ring interconnect, large L3 cache and multiple memory controllers. It also includes an on-die hardware-based immutable root of trust that authenticates firmware before the first line of firmware is ever executed

Centriq 2400 SoC is scheduled to start shipping later this year. You’ll find an in-depth overview of Falkor micro-architecture, and more slides on Anandtech.

Qualcomm Snapdragon 845 Octa-core Processor To Feature ARM Cortex A75 Cores (Reports)

May 22nd, 2017 7 comments

According to reports from China, Qualcomm’s next application processor (or rather mobile platform) will be Snapdragon 845, and if accurate, the comparison table below between the Snapdragon processor and Hisilicon Kirin 970 SoC shows the former will be powered by some customized (魔改) version of yet-to-be announced ARM Cortex 75 cores.

Snapdragon 845 octa-core processor will be manufactured using Samsung 10nm LPE processor, come with four custom Cortex A75 cores, four Cortex A53 cores, an Adreno 630 GPU, and an LTE X20 modem supporting LTE Cat 18 for up to 1.2 Gbps download speed. Other features like 802.11ad (High bandwidth, short range WiFi), UFS 2.1, and LPDDR4X were already found on earlier model.

I’ve been unable to find further details about ARM Cortex A75 right now, and we have to wait until ARM Techcon 2017 before getting more details. Mobile phones powered by Snapdragon 845 are supposed to start shipping in Q1 2018.

Via Wccftech

SiFive Launches 32-bit E31 Coreplex & 64-bit E51 Coreplex RISC-V Processors, Reveals Pricing

May 5th, 2017 4 comments

SiFive unveiled their Freedom U500 and E500 open source RISC-V SoCs last year, and a little layer launched HiFive1 Arduino compatible development board based on SiFive Freedom E310 processor. The company has now launched their non-open source Coreplex IP also based on RISC-V ISA with the 32-bit E31 Coreplex and 64-bit E51 Coreplex, and explained details about pricing.

E51 Coreplex – Click to Enlarge

Some of the key features of the processors are listed below:

  • E31 Coreplex
    • 32-bit RV32IMAC core @ 900 to 1.5 GHz (with 28nm process)
    • Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support
    • Up to 16 local interrupts with vectored addresses
    • Performance – 1.61 DMIPS/MHz  ; 2.73 Coremark/MHz
    • Power Consumption
      • 28nm HPC process – Core only: 150 DMIPS/mW ; Coreplex: 41 DMIPS/mW
      • 55nm LP process – Core only: 95 DMIPS/mW; Coreplex: 16 DMIPS/mW
    • Applications: Edge Computing, Smart IoT or Wearables.
    • Suited to replace the Cortex-M3 and Cortex-M4, but provides even higher performance without sacrificing area or power.
  • E51 Coreplex
    • 64-bit RV64IMAC embedded core @ 900 to 1.5 GHz (28nm process)
    • Advanced Memory Subsystem – 16KB, 2-way Instruction Cache, Instruction Tightly Integrated Memory (ITIM) option, up to 64KB Data Tightly Integrated Memory (DTIM) support
    • Support for up to 40 physical address bits
    • Up to 16 local interrupts with vectored addresses
    • Performance – 1.8 DMIPS/MHz  ; 2.76 Coremark/MHz
    • Power Consumption
      • 28nm HPC process – Core only: 125 DMIPS/mW ; Coreplex: 36 DMIPS/mW
      • 55nm LP process – Core only: 36 DMIPS/mW; Coreplex: 15 DMIPS/mW
    • Applications:
      • System or host control core within a larger 64-bit SoC
      • SSD controllers and network processors which require 64-bit compute without the requirement of virtual memory or full-featured operating systems.

SiFive R31 Coreplex Block Diagram – Click to Enlarge

If you want to manufacture an ARM processor, you first need to buy a license before accessing any information, and once you’re shipping your chips, you’ll pay royalties for each SoC sold with one or more ARM cores. SiFive business model is different. First, it’s free to try Coreplex IP on FPGA boards such as Digilent Arty, or evaluate RTL code in your own environment, so you don’t need to commit to any large investment before knowing whether you’ll go ahead with the cores. SiFive Coreplex IP is also royalty-free so how much you pay does not depend on how many chips you sell, and the way they make money is through a one-time license that costs $275,000 and up for E31 Coreplex, and $595,000 and up for E51 Coreplex with the exact price depending on options.

You’ll find the full details on Sifive Coreplex IP product page.

Categories: Hardware Tags: fpga, risc-v, sifive, soc

Imagination Technologies Announces MIPS Warrior I-class I6500 Heterogeneous CPU with up to 384 Cores

October 13th, 2016 No comments

Imagination has just unveiled the successor of MIPS I6400 64-Bit Warrior Core with MIPS Warrior I-class I6500 heterogeneous CPU supporting up to 64 cluster, with up to 6 cores each (384 cores max), themselves up to 4 thread (1536 max), combining with IOCU (IO coherence units), and external IP such as PowerVR GPU or other hardware accelerators.

mips-i6500-scalable-computeThe main features of MIPS I6400 processor are listed as follows:

 

  • Heterogeneous Inside – In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels.
  • Heterogeneous Outside – The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system efficiency.
  • Simultaneous Multi-threading (SMT) – Based on a superscalar dual issue design implemented across generations of MIPS CPUs, this  feature enables execution of multiple instructions from multiple threads every clock cycle, providing higher utilization and CPU efficiency.
  • Hardware virtualization (VZ) – I6500 builds on the real time hardware virtualization capability pioneered in the MIPS I6400 core. Designers can save costs by safely and securely consolidating multiple CPU cores with a single core, save power where multiple cores are required, and dynamically and deterministically allocate CPU bandwidth per application.
  • SMT + VZ – The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, makes the I6500 ideal for applications which require deterministic code execution.
  • Designed for compute intensive, data processing and networking applications – The I6500 is designed for high-performance/high-efficiency data transfers to localized compute resources with data scratchpad memories per CPU, and features for fast path message/data passing between threads and cores.
  • OmniShield-ready – Imagination’s multi-domain security technology used across its processing families enables isolation of applications in trusted environments, providing a foundation for security by separation.

The processor is also based on the standard MIPS ISA, so developer will be able to leverage existing software and tools such as compilers, debuggers, operating systems, hypervisors and application software already optimized for the MIPS ISA.

mips-i6500-soc

 

The figure above shows what an SoC based on MIPS I6500 may look like with one cluster with 4 CPU cores, 2 IOCUs, another cluster with any CPU cores but instead eight IOCUs interlinked with third party accelerators, and one PowerVR GPU.

Target applications include advanced driver assistance systems (ADAS), autonomous vehicles, networking, drones, industrial automation, security, video analytics, machine learning, and more. One of the first customer for the new processor is Mobileye EyeQ5 SoC designed for  Fully Autonomous Driving (interestingly shortened as “FAD”) vehicles will eight multi-threaded MIPS CPU cores coupled with eighteen cores of Mobileye’s Vision Processors (VPs). EyeQ5 SoC should be found in vehicles as early as 2021.

MIPS I6500 CPU can be licensed now, with general availability planned for Q1 2017.You’ll find more technical details on the product page, and blog post for the announcement.

Amlogic S905L Processor Drops VP9 Codec, TS Inputs for Tuners, and the Camera Interface

September 20th, 2016 8 comments

[Update: I’ve received updated documentation for Amlogic S905X too, and the main differences are only the lack of VP9 codec, and HDMI 2.0b interface]

Amlogic has apparently decided to launch yet another quad core Cortex A53 processor with Amlogic S905L, which appears to be based on  Amlogic S905X with built-in stereo audio codec and 10/100M Ethernet PHY & MAC, HDR support, but without VP9 codec, camera interface, nor TS inputs, so it looks like a cost-down version purely designed for OTT/IP TV boxes.

Click to Enlarge

Click to Enlarge

The document I have is dated June 2016, before the 1.5 GHz “limit” was discovered on Amlogic processors, and the maximum frequency is rated @ 2.0 GHz in the document. Amlogic S905L specifications (based on S905L Quick Referent Manual):

  • CPU – Quad core ARM Cortex-A53 CPU up to 2GHz (DVFS) with Neon and Crypto extensions, unified L2 cache
  • 3D GPU – Penta-core ARM Mali-450 GPU up to 750 MHz+ (DVFS)
  • 2.5D GPU – Fast bitblt engine with dual inputs and single output, programmable raster operations (ROP) and polyphase scaling filter, etc..
  • Crypto Engine – AES/AES-XTS block cipher with 128/192/256 bits keys, DES/TDES block cipher, built-in hardware True Random Number Generator (TRNG), CRC and SHA-1/SHA-2/HMAC SHA engine
  • Video/Picture CODEC
    • Amlogic Video Engine (AVE) with dedicated hardware decoders and encoders
    • Supports multiple “secured” video decoding sessions and simultaneous decoding and encoding
    • Video/Picture Decoding
      • H.265 HEVC MP-10@L5.1 up to 4Kx2K@60fps
      • H.264 AVC HP@L5.1 up to 4Kx2K@30fps
      • H.264 MVC up to 1080p @60fps
      • MPEG-4 ASP@L5 up to 1080P@60fps (ISO-14496)
      • WMV/VC-1 SP/MP/AP up to 1080P@60fps
      • AVS-P16(AVS+) /AVS-P2 JiZhun Profile up to 1080P@60fps
      • MPEG-2 MP/HL up to 1080P@60fps (ISO-13818)
      • MPEG-1 MP/HL up to 1080P@60fps (ISO-11172)
      • RealVideo 8/9/10 up to 1080P@60fps
      • WebM up to VGA
      • MJPEG and JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
      • Supports JPEG thumbnail, scaling, rotation and transition effects
    • Video/Picture Encoding
      • Independent JPEG and H.264 encoder with configurable performance/bit-rate
      • JPEG image encoding
      • H.264 video encoding up to 1080P@60fps with low latency
  • Video Post-Processing Engine – HDR10 & HLG HDR processing, motion adaptive 3D noise reduction filter, advanced motion adaptive edge enhancing de-interlacing engine, 3:2 pull-down support, deblocking fliters, etc..
  • Video Output
    • Built-in HDMI 2.0b transmitter including both controller and PHY with CEC, HDR and HDCP 2.2, 4Kx2K@60 max resolution output
    • CVBS 480i/576i standard definition output
  • Audio Decoder and Input/Output
    • Supports MP3, AAC, WMA, RM, FLAC, Ogg and programmable with 7.1/5.1 down-mixing
    • I2S audio interface supporting 8-channel (7.1) input and output
    • Built-in serial digital audio SPDIF/IEC958 output and PCM input/output
    • Built-in stereo audio DAC
    • Stereo digital microphone PDM input
    • Supports concurrent dual audio stereo channel output with combination of Analog+PCM or I2S+PCM
  • Memory and Storage Interface
    • 16/32-bit SDRAM memory interface running up to DDR2133
    • Supports up to 2GB DDR3/4, DDR3L, LPDDR2, LPDDR3 with dual ranks
    • Supports SLC/MLC/TLC NAND Flash with 60-bit ECC
    • SDSC/SDHC/SDXC card and SDIO interface with 1-bit and 4-bit data bus width supporting up to UHS-I SDR104
    • eMMC and MMC card interface with 1/4/8-bit data bus width fully supporting spec version 5.0 HS400
    • Supports serial 1, 2 or 4-bit NOR Flash via SPI interface
    • Built-in 4k bits One-Time-Programming memory for key storage
  • Network
    • Integrated 10/100M MAC controller with 10/100M PHY interface
    • Supports Energy Efficiency Ethernet (EEE) mode
  • Integrated I/O Controllers and Interfaces
    • Dual USB 2.0 high-speed USB I/O, one USB Host and one USB OTG
    • Multiple UART, I2C and SPI interface with slave select
    • Multiple PWMs
    • Programmable IR remote input/output controllers
    • Built-in 10bit SAR ADC with 2 input channels
    • General Purpose IOs with built-in pull up and pull down
  • System, Peripherals and Misc. Interfaces
    • Integrated general purpose timers, counters, DMA controllers
    • 24 MHz crystal input
    • Embedded debug interface using ICE/JTAG
  • Power Management
    • Multiple external power domains controlled by PMIC, and internal ones controlled by software
    • Multiple sleep modes for CPU, system, DRAM, etc.
    • Multiple internal PLLs for DVFS operation
    • Multi-voltage I/O design for 1.8V and 3.3V
    • Power management auxiliary processor in a dedicated always-on (AO) power domain that can communicate with an external PMIC
  • Security
    • Trustzone based Trusted Execution Environment (TEE)
    • Secured boot, encrypted OTP, encrypted DRAM with memory integrity checker, hardware key ladder and internal control buses and storage
    • Protected memory regions and electric fence data partition
    • Hardware based Trusted Video Path (TVP) , video watermarking and secured contents (needs SecureOS software)
    • Secured IO and secured clock
  • Package – LFBGA,13x13mm, 20×20 ball matrix, 0.65 ball pitch, RoHS compliant

Other notable changes include HDMI 2.0b support, and the Gigabit Ethernet MAC found in Amlogic S905X is now gone, and that’s fine since nobody has used it so far…

Amlogic S905L does not bring new features, but closely matches the requirements of the vast majority of TV boxes on the market, since the camera and tuner interfaces are seldom used, and 4K VP9 videos are still a rarity, except through YouTube app which does not enable 4K on such devices as Android TV operating system is required. All that means is that we should expect more $20 TV boxes soon.

Categories: AMLogic, Android, Hardware Tags: 4k, amlogic, hevc, soc, TV box

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

July 12th, 2016 5 comments

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself.

Freedom U500 Block Diagram

Freedom U500 Block Diagram

But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller.

Freedom U500 (Unleashed family) platform key specifications:

  • U5 Coreplex with 1 to 8 U54 cores @ 1.6GHz+
  • RV64GC Architecture (64- bit RISC-V)
  • Multicore, Cache Coherency Support
  • High Speed Peripherals: PCIe 3.0, USB3.0, GbE, DDR3/4
  • TSMC 28nm

The SoC supports Linux, and targets applications such as machine learning, storage, and networking.

Freedom E300 Block Diagram

Freedom E300 Block Diagram

Freedom E300 (Everywhere family) platform key specifications:

  • E3 Coreplex
  • RV32IMC/RV32EMC Architecture
  • On chip Flash, OTP, SRAM
  • TSMC 180nm

Three real-time operating systems, including FreeRTOS, have already been ported to Freedom E300 for embedded micro-controllers, IoT, and wearable markets.

Open source SoCs are made to be customizable to match your applications exact needs, instead of picking on existing SoC matching your requirements but with some uneeded features. SiFive also explains that “storage customers talks about custom instructions for bit manipulation so they can use one not 10 instructions for 10x speed up”. But before you get to Silicon, you’d normally ruin and customize the core on FPGA boards and three boards are currently available for development and evaluation:

  • Freedom U500:
  • Freedom E300 – Digilent Arty FPGA development kit powered by Xilinx XC7A35T-L1CSG324I FPGA, with 256 MB RAM, 16 MB flash, and vairous expension ports. Price: $99
Click to Enlarge

Xilinx Virtex-7 FPGA VC707 devkit – Click to Enlarge

You also have detailed documentation about the SoCs, U5 nd U3 coreplex, the development kits, software and tools, as well as developer forums, on SiFive developers website. You can also directly checkout the code and SDK on github.

RISC-V instructions set is royalty-free, so compared to the entry level $40,000 ARM license for startups using Cortex M0 MCU, it should provide some savings. It does not help with manufacturing costs which should remain the same. but SiFive expects that open source SoC could be manufactured through a “moderate” crowdfunding campaign.  I have not been able to figure out SiFive business model yet, unless they plan on selling their own chips too, and/or provide customization services to customers.

Lots more information can be found on Sifive website.

Via EETimes

FOSDEM 2015 Schedule – January 31 – February 1 2015

January 29th, 2015 8 comments

FOSDEM (Free and Open Source Software Developers’ European Meeting) takes place every year during the first week-end of February. This year the developer-oriented event expects to bring over 5000 geeks to share ideas and collaborate on open source projects. Contrary to most other events, it’s free to attend, and you don’t even need to register, just show up. FOSDEM 2015 will take place on January 31- February 1 in Brussels.

Fosdem_2015There will be 551 sessions divided into 5 keynotes, 40 lightning talks, 6 certification exams, and with the bulk being developer rooms and main tracks,  divided into 7 main tracks this year: Languages, Performance, Time, Typesetting, Hardware, Security and Miscellaneous.

I’m not going to attend, but it’s still interested to see what will be talked about, and I’ve concocted my own little virtual program out of the main tracks and developers’ rooms. There’s a few minutes overlap between some talks on Sunday.. Oh well.

If you won’t be able to attend, you should be able to watch the video and access the slides in a few weeks, as most sessions will be recorded.

What is the current status of Allwinner support in upstream u-boot and the kernel, which SoCs are supported, and which features (sound, video, etc.) are supported ?

The linux-sunxi community has been slowly but steadily working on getting Allwinner SoCs like the A10 supported in upstream u-boot and the kernel.

This talk will present the current status of Allwinner support upstream. Which SoCs are supported and which ones are not (yet) supported ? Which blocks if the supported SoCs are supported, and which are not ? Why are some SoCs / blocks not supported, and what are the plans to get them supported ? This are some of the questions this talk tries to answer.

Not all free operating systems are feature-full POSIX systems. FreeRTOS is a minimal operating system which is designed to run on micro-controllers, and provide real-time scheduling. It is used in industrial automation and automotive.

A brief introduction to FreeRTOS, depending on audience preference, will be followed by either a hands-on workshop using PCs, or a demonstration on a board. The workshop includes how to get started, what can be done with it, and what type of features and pitfalls to expect from FreeRTOS.

As ADAS and infotainment require more electronics, using an hypervisor is a solution to gather multiple boards into one. Xvisor is an open source lightweight hypervisor for embedded systems that perfectly fits the needs of the automative industry. It is a complete monolithic type-1 hypervisor with full virtualization and paravirtualisation support, showing better performances than KVM. We, OpenWide and the Institute for Technological Research SystemX, are working on its port on i.MX6 boards.

F*watch is an infinitely hackable GPS watch with many sensors based on a 100% Free design. Everything is Free, from the PCB and watch housing design to the software stack. Moreover, only Free software tools have been used during the development.

F*watch. Why should your watch be different?

The talk describes the development process and shows a first prototype, along with performance measurements and future plans.

The lowRISC project was established in the summer of 2014 with the aim of producing a complete open-source System-on-Chip in volume, with low-cost development boards. Alex Bradbury, one of the co-founders of the project will discuss the progress to date and the path to the first test chip. lowRISC implements the open RISC-V instruction set architecture and is exploring ideas on improving security via tagged memory and increasing flexibility through the addition of RISC-V ‘Minion’ cores to implement soft peripherals. This talk will discuss the potential benefits of a fully open-source hardware ecosystem, the challenges of getting to first silicon, and how the open source community at large can help.

Digital cameras provide almost every feature you could want. But if they don’t, you are forced to upgrade or go without. CHDK is a project which allows you to program new functionality to the majority of Canon cameras, in either C, Lua, or Basic. The talk features background on the project, code, tools, and the methods of compiling and introducing a new firmware into the camera.

Over the course of 1 hour, Steven Goodwin will guide the audience through the entire process of taking a normal (proprietary) camera and converting it into an open source version by installing custom firmware on it. He will then cover some of the features available (such as the on-device scripting language) and continue by explaining how to build and debug your own functionality. Starting with simple grids, continuing with games, and time-lapse code. And ending with a fully recompiled firmware running on the device.

The video4linux kernel subsystem reports which colorspace the captured video uses. But what does that really mean, and what do you have to do to correctly reproduce those colors? This talk will dive into the crazy world of colorspaces and give you a practical guide to colorspace handling. I will also demonstrate colorspace handling, both right and wrong.

Kernel profiling tools status on ARM and ARM64: – perf status, – ARM and ARM64 support, – callchain unwinding mechanisms and support, – patches status: merged, pending, in development, – links to discussions (LKML) and patches.

The profiling tools in the kernel are changing at a fast pace. This talk is about the support for ARM and ARM64 architecture and the development of features for these architectures, namely the callchain unwinding. The presentation goes over: – the detailed description of the feature, – the methods used to do the callchain unwinding (fp, exidx, dwarf etc.), – the status of the on-going patches, – the remaining work to be done, – the links to patches, discussions on the mailing lists, – -if needed and if time allows- a demo of the feature.

Building a medical device requires to follow certain rules specially when health care depend on it. The presentation will explain how Yocto help us in Kaptalia to solve this issue. In particular we will focus on fast boot, update with unskilled user base, Bluetooth Low Energy, security and data privacy.

During this event we will show how our team succeeded to build our first OS, start from a company with medical expert only and no prior expertise on embedded systems. At the end, a live demonstration for using the the monitor and sensor will be held.

LAVA is a python service created by Linaro for testing software on hardware which accepts test jobs to perform on selected hardware to provide a black box to continuous integration tests. Bisecting is a technique for finding commit in version control system that broke the software. Git provides the powerful “git bisect” subcommand for this purposes. In this talk we give and introduction to LAVA and explain howto combine LAVA and git bisect to automatically find offending commits in the Linux kernel.

Prospero Technologies has made a Linux based Digital Video Recorder which constantly records all UK broadcast TV so that the consumer no longer needs to schedule recordings. This will be a talk on the technologies used to achieve this, the open source software on the consumer device and how you can build your own 30 channel DVR.

The final version of the DVR uses a Freescale i.MX6 CPU with a video processing unit running a Linux built with Yocto. The talk will cover how well this is supported by gstreamer and how we built a QT application to display our HTML5 interface.

More and more embedded projects require support for advance connectivity. With it, comes the requirement to enforce a better security as well as private data protection. Using the layer model of Yocto, we show how we can extract from a complex project such as Tizen, advance connectivity and security and apply it to any embedded project.

The Internet of Things (IoT) is growing fast and opens large opportunities to embedded Linux. Unfortunately traditional embedded Linux has been weak when it comes to security and complex connectivity enabling. Tizen which has been developed as a Linux base OS for connected object (phone, TV, car) is on the other side very well equipped in that area. We will start by explaining what is Tizen architecture and how it provides Security and Connectivity facilities on top of a base Linux. We will then show how Yocto and Tizen-meta can be used to create embedded devices which benefit from several years of work done by the Tizen community. In particular we will review : – the mandatory access control enabling in an embedded device – the enforcement of good behavior by applications – resource access control – connectivity layers – HTML5 App enabling. – multi user mode enabling.

The ARM LLVM backend has been around for many years and generates high quality code, yet there are still standard benchmarks where GCC is generating more efficient code than LLVM. The goal of this talk is to get a better understanding of why the GCC-generated code for those benchmarks is executing more efficiently and also about finding out what we need to do on the LLVM side to address those code generation deficiencies. This talk presents current performance numbers for the SPEC CPU benchmark suites on ARM, comparing the performance of LLVM and GCC, with the main focus on the SPEC CPU integer benchmarks. To dive a little bit deeper, we will also have a closer look at the generated assembly code of selected benchmarks where LLVM is performing worse than GCC and use the results of this performance analysis to point out potential code generation opportunities for LLVM.

Connectivity is crucial for Internet of Things concept. For moving devices like position data loggers is typical solution GSM network. I will show you how you can use different types of GSM network for your IoT projects.

GSM network is easy way how to connect almost any device to internet. There are lot of GSM modules on market from different vendors but all devices has one thing in common – AT commands. There is standardized AT commands set for GSM networks. Using AT command you can send text messages, read phone number from list on SIM card, connect to internet and much more. I will show you basic command set for HTTP communication using basic GSM module SIM900 and Arduino.

This talk will give an overview over the Linux backports project and how to use it. The Linux backports project makes it possible to use a driver from a recent Linux mainline kernel with an older kernel version.

When you have a vendor board support package which does not use a bleeding edge mainline kernel, like it is the case most times, but you want to use some driver from a bleeding edge Linux kernel you can use backports. Backports “automatically” generates a tar with many drivers from a specific Linux mainline kernel which can be used with older kernel versions.

In this talk I will describe how the backports project, with its compatibility layer, the spatches and the normal patches. For practical usage I will show how to use backports with your own kernel in addition I will give a brief overview on how to add a new driver to backports.

Patchwork is a toolkit for connecting various devices into a network of things or, in a more broad case – Internet of Things (IoT). The main goal of creating this toolkit is to have a lightweight set of components that can help to quickly integrate different devices (i.e. Arduino, Raspberry Pi, Plugwise, etc) into a smart environment and expose specific devices’ capabilities as RESTful/SOAP/CoAP/MQTT/etc services and data streams.

The key features of patchwork include:

  • Lightweight (no RAM-consuming sliced pie of Java and OSGi, only bare necessities)
  • Cross-platform (can be deployed on OSX/Linux/Windows, tested on Raspberry Pi and BeagleBone Black boards)
  • Language-agnostic (device agents can be written in any programming language, APIs can be consumed by app written in any programming language)
  • Easily deployable (no JARs, no Eggs or Wheels for the core components, just a single native binary with statically linked dependencies)
  • Easily extendable (integrate new devices without modification of the core components, drop in solution)
  • Interchangeable (not happy with current existing Device Gateway or Catalog? replace it with another implementation without breaking the infrastructure)
  • Not re-inventing the wheel (we re-use as many existing technologies and components as possible)

libcurl is the world’s most used and most popular Internet transfer library, already used in every imaginable sort of embedded device out there. How did this happen and how do you use libcurl to transfer data to or from your device?

Embedded devices are very often network connected these days. Network connected embedded devices often need to transfer data to and from them as clients, using one or more of the popular internet protocols.

Daniel once founded the project and is still lead developer and maintainer of the curl project, making curl and libcurl. He is also active within IETF and maintain several other open source projects. Daniel is employed by Mozilla.

This presentation will reveal the process of porting Tizen:Common to open source hardware developer boards with SoC manufactured by Allwinner, Rockchip or Intel such as OLinuXino, Radxa Rock, Minnowboard. The following topics will be covered:

  • Building Tizen ARMv7 and x86 images from scratch
  • Adapting the Linux kernel, bootloader and Tizen:Common to popular single board computers
  • Do it yourself (DIY) open-source hardware Tizen tablet or laptop
  • Sharing knowledge and experience of the community.
The presentation will also provide information about U-Boot, Yocto project, the Linux-Sunxi and Linux-Rockchip, Minnowboard communities.

Although Tegra K1 uses the same Kepler architecture as NVIDIA desktop cards that Nouveau already supports, there are other challenges that need to be addressed before Nouveau can drive K1’s graphic acceleration: the fact that the GPU does not reside on the PCI bus requires architectural changes in the Nouveau core. The absence of dedicated GPU memory directly interferes with the way Nouveau is used to do memory management and leads to potentially sub-optimal behavior. Also, in a system where all devices share the same system memory, PRIME support is mandatory to perform any useful work and the relevance of a driver-agnostic memory allocator becomes perceptible.

This talk will discuss these challenges, and in particular the consequences of using a unified memory architecture, in the hope of triggering discussions that will help improving the general support of GPU architectures for new mobile platforms.

A brief look at the past, present, and future of the KiCad project. The discussion will be primarily on what near and long term future development is planned for the project as well as discussing the potential for collaboration with other EDA projects.

Yocto has an alleged steep learning curve. It can be a challenge for modules and evaluation board manufacturers to add support for their devices in Yocto as they don’t necessarily have a software background. This talk will highlight the steps required, techniques and good practices to create a well integrated machine configuration allowing to build images using the Yocto Linux build system. The Crystalfontz support from meta-fsl-arm-extra will be used to illustrate the talk.

The bitbox console is a small open hardware & open source game console. I will present the rationale behind it and the current status of the project, detail the hardware conception and particularly video signal generation from a cortex-m4 chip with no video subsystem. I will then proceed to show the different elements of the software stack : kernel, video engines, the boot loader and, finally, current programs and games, including a Gameboy emulator and a full motion video player.

If you want to build your own schedule before going, you can check the full list of events by subjects, but an easier way to organize your day is to check the sessions in chronological order, by checking out Saturday and Sunday schedules.

LG NUCLUN Octa-core ARM SoC Powers G3 Screen Smartphone

October 25th, 2014 5 comments

LG has been making mobile devices since 1997, has entered the smartphone market in 2010, and they’ve now decided to foray into mobile SoC, with their very first SoC being an octa-core Cortex A15/A7 processor called NUCLUN, and found in their latest G3 Screen smartphone running Android 4.4.4.

LG_G3_Screen_NUCLUN_Processor

Details about NUCLUN processor are sparse, but the company did provide some specifications for LG G3 Screen smartphone:

  • SoC – LG NUCLUN (LG7111) Octa-Core big.LITTLE processor with four ARM Cortex A15 cores @ 1.5GHz, four ARM Cortex A7 cores @ 1.2GHz.
  • System Memory – 2GB RAM
  • Storage – 32GB  eMMC + MicroSD slot
  • Display – 5.9″ Full HD IPS touchscreen
  • Camera – 13MP OIS+ rear camera, 2.1MP front-facing camera
  • Network – LTE-A Cat.6 for up to 225Mbps download speed.
  • Battery – 3,000mAh
  • Dimensions – 157.8x 81.8x 9.5mm
  • Weight – 182g

The phone,  also codenamed as LG Liger F490L, F490K or F490S (depending on carrier) , runs Android 4.4.4 KitKat on top of Linux 3.10.40+. The GPU was not listed, but based on some CPU-Z screenshots a PowerVR GPU (Series 6?) is used in NUCLUN. The firmware may not be optimized for performance just yet, as Antutu 5.1.5 score is just 25,460 points.

LG_G3_Screen_CPU-Z_Antutu

LG G3 Screen will only be available later this week in Korea, but price has not been disclosed yet.

Via Liliputing, GSMArea, and kenhcongnghe