Last year, WCH introduced their first RISC-V MCU with CH572 Bluetooth LE microcontroller which came with 10KB SRAM and a not so convenient 96KB OTP flash. But I’ve just been informed the company has introduced their first general-purpose RISC-V MCU family with several CH32V103 microcontrollers featuring up to 64KB Flash and 20KB SRAM, and all sort of peripherals you’d expect from a general-purpose MCU.
WCH CH32V103 key features and specifications:
- CPU Core – 32-bit RISC-V (RV32IMAC) core @ up to 72/80 MHz called ” RISC-V3A”
- Memory – 10KB or 20KB SRAM
- Storage – 32KB or 64KB flash
- 1x USB 2.0 Full Speed Host/Device
- Up to 2x SPI (master/slave), up to 2x I2C, up to 3x USART
- Up to 16x 12-bit ADC/touch key
- 37x or 51x GPIOs
- Up to 3x general-purpose timers, 1x advanced timer, 2x watchdog timers, 1x Systick
- Supply Voltage – 2.7 to 5.5V
- Package – LQFP48, QFN48 or LQFP64
- Temperature Range – -40°C to 85°C
There are currently four CH32V103 parts:
- CH32V103C6T6 with 32KB flash, 10KB SRAM in LQFP48 package
- CH32V103C8T6 with 64KB flash, 20KB SRAM in LQFP48 package
- CH32V103C8U6 with 64KB flash, 20KB SRAM in QFN48X7 package
- CH32V103R8T6 with 64KB flash, 20KB SRAM in LQFP64M package
The new family appears to offer an alternative to the company’s CH32F103 Arm Cortex-M3 microcontrollers with the RISC-V MCU having likely a lower power consumption. You’ll find a list of both Arm and RISC-V MCUs on WCH website (Chinese version only for now). For more details, you may want to check out the datasheet, again written in Chinese language. We will have to wait a little longer for development boards and get more information about software tools as I was able to find any details about either.
The launch of WCH CH32V103 microcontroller also means GigaDevice GD32V general-purpose RISC-V MCU gets some competition. The latter does have a larger family however with up to 128KB flash and 32KB SRAM, an RV32IMAC core clocked at 108 MHz, and a choice of 36-pin, 48-pin, 64-pin, and 100-pin packages.
Thanks to Kali Prasad for the tip.