Zynq UltraScale+ Arm FPGA FZ3 Deep Learning Accelerator Card Supports Baidu Brain AI Tools

FZ3 Card

MYIR’s FZ3 card is a deep learning accelerator board powered by Xilinx Zynq UltraScale+ ZU3EG Arm FPGA MPSoC delivering up to 1.2TOPS for artificial intelligence products based on Baidu Brain AI open platform. The FZ3 card also features 4GB RAM, 8GB eMMC flash, USB 2.0 & USB 3.0 ports, Gigabit Ethernet, DisplayPort (DP) output, PCIe interface, MIPI-CSI and more. MYIR FZ3 card specifications: SoC – Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784E (ZU3EG) MPSoC Quad-core Arm Cortex-A53 @ 1.2 GHz Dual-core Arm Cortex-R5 processor @ 600MHz Arm Mali-400MP2 GPU FPGA fabric System Memory – 4GB DDR4 Storage – 8GB eMMC flash, 32MB QSPI flash, 32KB EEPROM, MicroSD card slot Video Output – 1x Mini DisplayPort up to 4Kp30 Camera I/F 1 x MIPI-CSI Interface (25-pin 0.3mm pitch FPC connector) 1 x BT1120 Camera Interface (32-pin 0.5mm pitch FPC connector) Connectivity – 1x Gigabit Ethernet USB – 1x USB 2.0 Host, 1x USB 3.0 Host  Expansion 1x PCIe 2.1 Interface (1-lane) Two 2.54mm pitch 2×20-pin …

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Sipeed TANG Hex is a Low-Cost Xilinx Zynq-7020 Arm FPGA Board

Sipeed TANG Hex

Last year, Sipeed launched a $5 FPGA board called Sipeed Tang and based on an entry-level Gowin GW1N-1-LV FPGA. But I had not noticed the company had also worked on a more powerful, yet still low-cost Xilinx Zynq-7020 board in a business card form factor not too dissimilar from the Raspberry Pi model B form factor. Meet Sipeed TANG Hex. So far a low-cost Zynq-7010 or Zynq-7020 board met you had to spend $99 to $199 with products such as MyIR Z-Turn and Digilent PYNQ-Z1. But Sipeed Tang HEX can be purchased for as little as $73 shipping on Aliexpress,  or 439 RMB ($62) on Taobao for people based in mainland China. It might be tempting to get a low-cost board to get started, but is it worth it? Read on to find out. Sipeed TANG Hex specifications: SoC – Xilinx Zynq-7020 (XC7Z020-1CLG484) dual-core Arm Cortex-A9 processor and FPGA with 85K logic cells, 4.9Mb Block RAM, 220 DSP slices System …

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4K Vision Edge Computing Platform Features Xilinx Zynq UltraScale+ ZU3EG MPSoC

VECP Vision Edge Computing Platform

Last year, MyIR Tech introduced MYD-CZU3EG development board powered by a Xilinx Zynq UltraScale+ ZU3EG MPSoC with Arm Cortex-A53 cores and FPGA fabric designed for applications such as cloud computing, machine vision, flight navigation, and other complex embedded applications. The company has now announced another Zynq Ultrascale+ ZU3EG based platform dedicated to machine vision. The VECP Starter Kit (Vision Edge Computing Platform) is comprised of MYD-CZU3EG-ISP development board fitted with the company’s MYC-CZU3EG Zynq UltraScale+ MPSoC CPU module, a fansink, and a SONY IMX334 4K camera sensor. MYD-CZU3EG-ISP development board specification: MYC-CZU3EG SoM MPSoC – Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784E (ZU3EG, 784 Pin Package) MPSoC with quad-core Arm Cortex-A53 processor @ 1.2 GHz, dual-core Cortex-R5 processor @ 600 MHz, Arm Mali-400MP2 GPU, and 16nm FinFET+ FPGA fabric (154K logic cells, 7.6 Mb memory, 728 DSP slices) System Memory – 4GB DDR4 @ 2,400MHz Storage – 4GB eMMC Flash, 128MB QSPI Flash PS unit (Processing Subsystem i.e. Arm Cortex cores) Storage – …

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NetBSD 9.0 Released with Aarch64 Support, Arm ServerReady Compatibility

NetBSD 9.0

Yesterday, we wrote about Raspberry Pi 4 getting UEFI+ACPI firmware for Arm SSBR compliance allowing the board to run operating systems designed for “Arm ServerReady” servers out of the box. NetBSD 9.0 was just released on February 14, 2020, with support for Aarch64 (64-bit Arm) which had been in the works for a few years, and includes support for “Arm ServerReady” compliant machines (SBBR+SBSA). NetBSD 9.0 main changes related to hardware support: Support for AArch64 (64-bit Armv8-A) machines Compatibility with “Arm ServerReady” compliant machines (SBBR+SBSA) using ACPI. Tested on Amazon Graviton and Graviton2 (including bare metal instances), AMD Opteron A1100, Ampere eMAG 8180, Cavium ThunderX, Marvell ARMADA 8040, QEMU w/ Tianocore EDK2 Symmetric and asymmetrical multiprocessing support (big.LITTLE) Support for running 32-bit binaries via COMPAT_NETBSD32 on CPUs that support it Single GENERIC64 kernel supports ACPI and device tree based booting Supported SoCs Allwinner A64, H5, H6 Amlogic S905, S805X, S905D, S905W, S905X Broadcom BCM2837 (Raspberry Pi 3B) NVIDIA Tegra X1 …

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ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC’s with Accelerators

ESP RISC-V & Sparc Platform

FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled “Open ESP – The Heterogeneous Open-Source Platform for Developing RISC-V Systems” with an excerpt of the abstract reading: ESP is an open-source research platform for RISC-V systems-on-chip that integrates many hardware accelerators. ESP provides a vertically integrated design flow from software development and hardware integration to full-system prototyping on FPGA. For application developers, it offers domain-specific automated solutions to synthesize new accelerators for their software and map it onto the heterogeneous SoC architecture. For hardware engineers, it offers automated solutions to integrate their accelerator designs into the complete SoC. If we go to the official website, we can see ESP (Embedded Scalable Platform) actually supports both 32-bit Leon3 (Sparc) and 64-bit Ariane (RISC-V) cores, and various hardware accelerators from the platform or third parties. Highlights: Architecture Tile-based architecture: processor, memory and accelerator tiles NoC (Network-on-Chip) …

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OpenWiFi Open-Source Linux-compatible WiFi Stack Runs on FPGA Hardware

OpenWiFi

WiFi is omnipresent on most connected hardware, and when it works it’s great, but when there are issues oftentimes they can not be solved because the firmware is a closed-source binary. I understand companies do that either to protect their IP and/or make sure end-users do not break FCC compliance. OpenWiFi project aims to deliver a completely open-source SDR (Software Defined Radio) WiFi implementation compatible with Linux and running on FPGA hardware. OpenWiFi currently supported features: 802.11a/g; 802.11n MCS 0~7; 20MHz Mode tested: Ad-hoc; Station; AP DCF (CSMA/CA) low MAC layer in FPGA Configurable channel access priority parameters: duration of RTS/CTS, CTS-to-self SIFS/DIFS/xIFS/slot-time/CW/etc Time slicing based on MAC address Easy to change bandwidth and frequency: 2MHz for 802.11ah in sub-GHz 10MHz for 802.11p/vehicle in 5.9GHz The developers tested OpenWiFi on Xilinx ZC706 FPGA evaluation kit coupled Analog Devices fmcomms2/fmcomms4 RF board to form an access point, and connected it to a client with TL-WDN4200 N900 dual-band WiFi USB Adapter. iperf …

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Digilent Offers 2 Zynq-Based Linux Development Boards Supporting SYZYGY Expansion

Digilent Announces SYZYGY high-speed SBCs Digilent has announced two new SBCs that are ultra-high-speed and built to be more modular than its other boards.  The company, which has a great deal of experience in Pmod lower speed FPGA standards has now entered the open-source, SYZYGY high-speed standards with its Eclypse Z7 and the Genesys ZU  development SBCs. Background on the Digilent Zybo FPGA SoC SBC We reported on the Zybo development board FPGA SoC from Digilent and that seems to have lead to the latest format for the Eclypse Z7. Zmod There is also a release planned for the new Zmod modules, built to work with both the Eclypse Z7 and the Genesys ZU  as SYZYGY compliant expansion modules. Opal Kelly and Zmod expansion The Zmods are Opal Kelly module standard, called SYZYGY, first seen in the Opal Kelly SYZYGY Brain-1 SBC. The standard was developed to jump the gap between Pmod and the more developed VITA 57.1 FMC (FPGA …

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Linaro Connect San Diego 2019 Schedule – IoT, AI, Optimizations, Compilers and More

Linaro Connect San Diego 2019

Linaro has recently released the full schedule of Linaro Connect San Diego 2019 that will take place on  September 23-27. Even if you can’t attend, it’s always interested to check out the schedule to find out what interesting work is done on Arm Linux, Zephyr OS, and so on. So I’ve created my own virtual schedule with some of the most relevant and interesting sessions of the five-day event. Monday, September 23 14:00 – 14:25 – SAN19-101 Thermal Governors: How to pick the right one by Keerthy Jagadeesh, Software Engineer, Texas Instruments With higher Gigahertz and multiple cores packed in a SoC the need for thermal management for Arm based SoCs gets more and more critical. Thermal governors that define the policy for thermal management play a pivotal role in ensuring thermal safety of the device. Choosing the right one ensures the device performs optimally with in the thermal budget. In this presentation Keerthy Jagadeesh, co-maintainer of TI BANDGAP AND …

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