OpenWiFi Open-Source Linux-compatible WiFi Stack Runs on FPGA Hardware

OpenWiFi

WiFi is omnipresent on most connected hardware, and when it works it’s great, but when there are issues oftentimes they can not be solved because the firmware is a closed-source binary. I understand companies do that either to protect their IP and/or make sure end-users do not break FCC compliance. OpenWiFi project aims to deliver a completely open-source SDR (Software Defined Radio) WiFi implementation compatible with Linux and running on FPGA hardware. OpenWiFi currently supported features: 802.11a/g; 802.11n MCS 0~7; 20MHz Mode tested: Ad-hoc; Station; AP DCF (CSMA/CA) low MAC layer in FPGA Configurable channel access priority parameters: duration of RTS/CTS, CTS-to-self SIFS/DIFS/xIFS/slot-time/CW/etc Time slicing based on MAC address Easy to change bandwidth and frequency: 2MHz for 802.11ah in sub-GHz 10MHz for 802.11p/vehicle in 5.9GHz The developers tested OpenWiFi on Xilinx ZC706 FPGA evaluation kit coupled Analog Devices fmcomms2/fmcomms4 RF board to form an access point, and connected it to a client with TL-WDN4200 N900 dual-band WiFi USB Adapter. iperf …

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Digilent Offers 2 Zynq-Based Linux Development Boards Supporting SYZYGY Expansion

Digilent Announces SYZYGY high-speed SBCs Digilent has announced two new SBCs that are ultra-high-speed and built to be more modular than its other boards.  The company, which has a great deal of experience in Pmod lower speed FPGA standards has now entered the open-source, SYZYGY high-speed standards with its Eclypse Z7 and the Genesys ZU  development SBCs. Background on the Digilent Zybo FPGA SoC SBC We reported on the Zybo development board FPGA SoC from Digilent and that seems to have lead to the latest format for the Eclypse Z7. Zmod There is also a release planned for the new Zmod modules, built to work with both the Eclypse Z7 and the Genesys ZU  as SYZYGY compliant expansion modules. Opal Kelly and Zmod expansion The Zmods are Opal Kelly module standard, called SYZYGY, first seen in the Opal Kelly SYZYGY Brain-1 SBC. The standard was developed to jump the gap between Pmod and the more developed VITA 57.1 FMC (FPGA …

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Linaro Connect San Diego 2019 Schedule – IoT, AI, Optimizations, Compilers and More

Linaro Connect San Diego 2019

Linaro has recently released the full schedule of Linaro Connect San Diego 2019 that will take place on  September 23-27. Even if you can’t attend, it’s always interested to check out the schedule to find out what interesting work is done on Arm Linux, Zephyr OS, and so on. So I’ve created my own virtual schedule with some of the most relevant and interesting sessions of the five-day event. Monday, September 23 14:00 – 14:25 – SAN19-101 Thermal Governors: How to pick the right one by Keerthy Jagadeesh, Software Engineer, Texas Instruments With higher Gigahertz and multiple cores packed in a SoC the need for thermal management for Arm based SoCs gets more and more critical. Thermal governors that define the policy for thermal management play a pivotal role in ensuring thermal safety of the device. Choosing the right one ensures the device performs optimally with in the thermal budget. In this presentation Keerthy Jagadeesh, co-maintainer of TI BANDGAP AND …

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MYIR Announces Xilinx Zynq UltraScale+ MPSoC SoM and Development Board

MYD-CZU3EG development board

MYIR Technology has been selling Xilinx Zynq-7000 FPGA + Arm systems-on-module since 2016, but the Chinese company has now announced new modules based on the more powerful Xilinx Zynq Ultrascale+ MPSoC with Arm Cortex-A53 cores, Arm Cortex-R5 cores, and Ultrascale FPGA fabric, as well as a corresponding development board. MYC-CZU3EG Zynq UltraScale+ MPSoC CPU Module CPU module specifications: Mechanical Parameters MPSoC – Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784E (ZU3EG, 784 Pin Package) MPSoC with quad-core Arm Cortex-A53 processor @ 1.2 GHz, dual-core Cortex-R5 processor @ 600 MHz, Arm Mali-400MP2 GPU, and 16nm FinFET+ FPGA fabric (154K logic cells, 7.6 Mb memory, 728 DSP slices) System Memory – 4GB DDR4 @ 2,400MHz Storage – 4GB eMMC Flash, 128MB QSPI Flash On-module chips Gigabit Ethernet PHY USB PHY Intel Power Module Clock Generator 2x Samtec 0.5mm pitch 160-pin high-speed headers bringing out Networking – Gigabit Ethernet USB – USB 2.0 interface 4x PS GTR transceivers along with 2 GTR reference clock inputs 4x PL GTH …

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Xilinx Arm FPGA, Snapdragon SoM’s, and Wandboard SBC Field Trip to Space

SpaceX Starlink Satellites Falcon Rocket

Most embedded systems are used here on planet earth, but some do take off heading for space, and this week I come accross two separate projects leveraging Arm processors and FPGAs, as well as Ubuntu/ROS and Android operating systems: SpaceX Starlink communication satellites and Astrobee robots roaming in the international space station (ISS) SpaceX Starlink Satellites with Xilinx Ultrascale+ Arm + FPGA SoC SpaceX is about to launch a cloud of 60 Starlink communication satellites that aims to provide internet communication anywhere in the world. That’s just a start as eventually the plan is to get up to 12,000 of those satellites. Usually, we would not know many technical details about the satellites, but as one reader pointed out (Thanks Lawrence!), a Reddit thread about the launch, also pointed to a NASA document revealing the satellites are powered by Xilinx Ultrascale+ quad core Cortex-A53 processor with FPGA fabric. Milestone 2 in Article 4 of the document explains a bit more: …

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Ultra96-V2 96Boards AI Platform Adds Certified WiFi, PMICs, Industrial Temperature Range

96Boards Xilinx Ultrascale+ Board

Avnet Ultra96 was unveiled last year as one of the four 96Boards AI platforms designed to develop applications leveraging hardware to accelerated artificial intelligence workloads. The 96Boards CE compliant board comes with a Xilinx Zynq UltraScale+ MPSoC, 2GB RAM, a 16GB microSD card, WiFi and Bluetooth connectivity and more. The company has now launched an upgraded version with Ultra96-V2 featuring most of the same specifications but with a WiFi & Bluetooth module certified in 75 countries, industrial temperature range, and Infineon’s PMIC’s for additional power control and monitoring. Ultra96-V2 specifications: SoC – Xilinx Zynq UltraScale+ MPSoC ZU3EG A484 with four Cortex A53 cores, two Cortex-R5 core, Arm Mali-400MP2 GPU, and FPGA Fabric System Memory – 2 GB (512M x32) LPDDR4 Memory Storage – 16 GB MicroSD card + adapter pre-loaded with PetaLinux environment Video Output – Mini DisplayPort (MiniDP) Connectivity – Microchip ATWILC3000 certified 802.11 b/g/n WiFi 4 / Bluetooth 5 module (FCC, CMIIT, ANATEL, etc..?) USB – 1x USB …

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PYNQ-Z2 Python FPGA Board Adds Raspberry Pi Header, 24-Bit Audio Codec

PYNQ-Z2

PYNQ-Z1 is a board by Digilent powered by Xilinx Zynq-7020 Arm Cortex-A9 + FPGA SoC that’s designed specifically for PYNQ, an open-source project that aims to ease the design of embedded systems with Xilinx Zynq Systems on Chips (SoCs) by leveraging the Python language and libraries. PYNQ-Z2 is very similar to PYNQ-Z1, but it’s made by Taiwanese company TUL, and the board is slightly longer to allow for an extra 40-pin Raspberry Pi compatible header, and Analog Devices ADAU1761 24-bit audio codec. PYNQ-Z2 board specifications: SoC – Xilinx Zynq-7020 (XC7Z020-1CLG400C) dual core Arm Cortex-A9 processor @ 650 MHz with FPGA with 13,300 logic slices, each with four 6-input LUTs and 8 flip-flops System Memory – 512MB DDR3 Storage – Micro SD card slot, 16MB QSPI Flash with factory programmed globally unique identifier (48-bit EUI-48/64 compatible). Video – HDMI In and HDMI Out Audio – Mic in, Line Out  ADAU1761 codec with 3.5mm HP + Mic jack, 3.5mm Line in jack …

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Embedded Recipes 2018 Videos and Slides Released

Upstream Multimedia Amlogic-SoC-Embedded Recipes 2018 Videos

Embedded Recipes 2018 happened in Mozilla building in Paris, France on September 24 & 25, where developers talked about “open source solutions in the embedded world: developer, contributor, tools, platforms…” We previously mentioned the event in a post about an open source video decoder driver for Amlogic S905, S905X and S912 processors with BayLibre scheduled to talk about their work there. There’s now released slides and videos for the event for all sessions including: SoC+FPGA support in 2018 by Marek Vasut Shared memory and telemetry by Yves-Marie Morgan Updating an embedded system with swupdate by Charles-Antoine Couret Finding sources of latency in your system by Steven Rostedt Io(M)T Security: A year in review by Rayna Stamboliyska Using yocto to generate container images for yocto by Jérémy Rosen linuxboot by Jean-Marie Verdun and  Trammell Hudson End-to-end software production for embedded by Guy Lunardi WooKey: the USB Battlefront Warrior by Mathieu Renard, Ryad Benadjila EBBR: Standard Boot for Embedded Platforms by Alexander …

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